Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56345 )
Change subject: [WIP] soc/amd/cezanne/mca: add and use mca_bank_name[] ......................................................................
[WIP] soc/amd/cezanne/mca: add and use mca_bank_name[]
This enables the MCAX checking and BERT entry generation for Cezanne.
TODO: verification
Change-Id: Ibe8047ce5bb5e7136a8786693bcced4d2225b1fd Signed-off-by: Felix Held felix-coreboot@felixheld.de --- M src/soc/amd/cezanne/mca.c 1 file changed, 38 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/56345/1
diff --git a/src/soc/amd/cezanne/mca.c b/src/soc/amd/cezanne/mca.c index 77006a7..778b8e7 100644 --- a/src/soc/amd/cezanne/mca.c +++ b/src/soc/amd/cezanne/mca.c @@ -1,19 +1,54 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <amdblocks/mca.h> +#include <cpu/x86/msr.h> #include <types.h>
+static const char *const mca_bank_name[] = { + [0] = "Load-store unit", + [1] = "Instruction fetch unit", + [2] = "L2 cache unit", + [3] = "Decode unit", + [4] = "", + [5] = "Execution unit", + [6] = "Floating point unit", + [7] = "L3 cache unit", + [8] = "L3 cache unit", + [9] = "L3 cache unit", + [10] = "L3 cache unit", + [11] = "L3 cache unit", + [12] = "L3 cache unit", + [13] = "L3 cache unit", + [14] = "L3 cache unit", + [15] = "", + [16] = "", + [17] = "UMC", + [18] = "UMC", + [19] = "CS", + [20] = "CS", + [21] = "", + [22] = "", + [23] = "", + [24] = "", + [25] = "", + [26] = "", + [27] = "PIE", +}; + bool mca_has_expected_bank_count(void) { - return true; + return ARRAY_SIZE(mca_bank_name) == mca_get_bank_count(); }
bool mca_is_valid_bank(unsigned int bank) { - return false; + return (bank < ARRAY_SIZE(mca_bank_name) && mca_bank_name[bank] != NULL); }
const char *mca_get_bank_name(unsigned int bank) { - return ""; + if (mca_is_valid_bank(bank)) + return mca_bank_name[bank]; + else + return ""; }