[coreboot-gerrit] Change in coreboot[master]: soc/amd/common/espi: Print set eSPI peripheral config

[Raul Rangel (Code Review)]

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held.
Hello Jason Glenesk, Marshall Dawson, Felix Held,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/52952

to look at the new patch set (#2).

Change subject: soc/amd/common/espi: Print set eSPI peripheral config
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soc/amd/common/espi: Print set eSPI peripheral config

This will print the config we are setting on the eSPI peripheral.

e.g.,
Setting general configuration: slave: 0x98a00000 controller: 0xe2000000
eSPI Slave configuration:
    CRC checking enabled
    Dedicated Alert# used to signal alert event
    eSPI quad IO mode selected
    Only eSPI single IO mode supported
    Alert# pin is open-drain
    eSPI 33MHz selected
    eSPI up to 20MHz supported
    Maximum Wait state: 0

BUG=b:187122344, b:186135022
TEST=Boot guybrush

Signed-off-by: Raul E Rangel 
Change-Id: I1a2382d8ab3d3f0d14a139c57470cb895112eca9
---
M src/soc/amd/common/block/lpc/espi_util.c
1 file changed, 2 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/52952/2