[coreboot-gerrit] Change in coreboot[master]: mainboard/google/volteer: Enable long cr50 ready pulses

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44359 )

Change subject: mainboard/google/volteer: Enable long cr50 ready pulses
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Patch Set 12:

(1 comment)

https://review.coreboot.org/c/coreboot/+/44359/12/src/mainboard/google/volte... 
File src/mainboard/google/volteer/mainboard.c:

https://review.coreboot.org/c/coreboot/+/44359/12/src/mainboard/google/volte... 
PS12, Line 35: mainboard_update_s0ix_disable_mask
There is a callback used in the `fsp_params.c` file specifically for when a mainboard needs to override FSP-S UPDs, `mainboard_silicon_init_params(FSP_S_CONFIG *params)`. I think the intention may be more clear by updating the UPDs directly.
Also otherwise you're relying on the mainboard chip_init happening before the SoC chip init , because FSP-S is called from the SoC chip init.