Stefan Reinauer (stefan.reinauer@coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11086
-gerrit
commit c5373d8214f40c1e52c543d6e4b8f88577e010a1 Author: Stefan Reinauer reinauer@chromium.org Date: Thu Jul 30 16:25:33 2015 -0700
RD890: 64bit fixes
Change-Id: I326c070398c72a877054969d3a03e6e427edc304 Signed-off-by: Stefan Reinauer stefan.reinauer@coreboot.org --- src/northbridge/amd/cimx/rd890/late.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/src/northbridge/amd/cimx/rd890/late.c b/src/northbridge/amd/cimx/rd890/late.c index bc51543..3bdce27 100644 --- a/src/northbridge/amd/cimx/rd890/late.c +++ b/src/northbridge/amd/cimx/rd890/late.c @@ -86,7 +86,8 @@ static void rd890_enable(device_t dev) /* CIMX configuration defualt initialize */ rd890_cimx_config(&gConfig, &nb_cfg[0], &ht_cfg[0], &pcie_cfg[0]); if (gConfig.StandardHeader.CalloutPtr != NULL) { - gConfig.StandardHeader.CalloutPtr(CB_AmdSetPcieEarlyConfig, (u32)dev, (VOID*)NbConfigPtr); + gConfig.StandardHeader.CalloutPtr(CB_AmdSetPcieEarlyConfig, + (uintptr_t)dev, (VOID*)NbConfigPtr); } /* Reset PCIE Cores, Training the Ports selected by port_enable of devicetree * After this call EP are fully operational on particular NB @@ -122,7 +123,7 @@ static void ioapic_init(struct device *dev) void *ioapic_base;
pci_write_config32(dev, 0xF8, 0x1); - ioapic_base = (void *)(pci_read_config32(dev, 0xFC) & 0xfffffff0); + ioapic_base = (void *)(uintptr_t)(pci_read_config32(dev, 0xFC) & 0xfffffff0); clear_ioapic(ioapic_base); setup_ioapic(ioapic_base, 1); }