[coreboot-gerrit] Change in coreboot[master]: mainboard/google/volteer: Enable long cr50 ready pulses

[Jes Klinke (Code Review)]

Jes Klinke has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44359 )

Change subject: mainboard/google/volteer: Enable long cr50 ready pulses
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Patch Set 10:

(1 comment)

Subrata, please let us know if we need to do more than clearing bit7 of the Lpm enable register, in order to allow Tiger Lake to recognize 4us interrupt pulses.

https://review.coreboot.org/c/coreboot/+/44359/10/src/mainboard/google/volte... 
File src/mainboard/google/volteer/mainboard.c:

https://review.coreboot.org/c/coreboot/+/44359/10/src/mainboard/google/volte... 
PS10, Line 37: 		cfg->LpmStateDisableMask = LPM_S0i3_4;
> I think you will also have to handle gpio_pm_config here: […]

I have not heard the Intel engineers mention anything besides the Lpm bit7 being cleared, as necessary for Tiger Lake to recognize interrupt pulses as short as 4us.

Subrata, can you please confirm?