[coreboot-gerrit] [S] Change in coreboot[master]: soc/intel/xeon_sp: Cache DRAM with TSEG for FSP-S execution time

[Lean Sheng Tan (Code Review)]

Attention is currently required from: Patrick Rudolph, Johnny Lin, Paul Menzel, Christian Walter, Arthur Heymans, Shuming Chu (Shuming).

Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71085 )

Change subject: soc/intel/xeon_sp: Cache DRAM with TSEG for FSP-S execution time
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Patch Set 6: Code-Review+2