Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80792?usp=email )
Change subject: soc/intel/xeon_sp: Encode domain type ......................................................................
soc/intel/xeon_sp: Encode domain type
Use the unused 'name' property of the domain device and store the domain type. Every IIO stack can have multiple domain devices, each owning a subset of the available bus range within the stack.
The name can be used in future changes to easily identify the domain or to generate ACPI names in SSDT code generation.
Change-Id: Ic4cc81d198fb88300394055682a3954bf22db570 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/soc/intel/xeon_sp/chip_common.c M src/soc/intel/xeon_sp/include/soc/chip_common.h M src/soc/intel/xeon_sp/spr/ioat.c 3 files changed, 33 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/80792/1
diff --git a/src/soc/intel/xeon_sp/chip_common.c b/src/soc/intel/xeon_sp/chip_common.c index 0c1d52b..4ec7da6 100644 --- a/src/soc/intel/xeon_sp/chip_common.c +++ b/src/soc/intel/xeon_sp/chip_common.c @@ -194,6 +194,8 @@ .domain_path = dp.domain_path };
+ /* Only expect 2 UBOX buses here */ + assert(bus_base + 1 == bus_limit); for (int i = bus_base; i <= bus_limit; i++) { new_path.bus = i;
@@ -208,6 +210,7 @@ die("%s: out of memory.\n", __func__);
domain->ops = &ubox_pcie_domain_ops; + domain->name = (i == bus_base) ? DOMAIN_TYPE_UBX0 : DOMAIN_TYPE_UBX1;
struct bus *const bus = alloc_bus(domain); bus->secondary = i; @@ -226,9 +229,10 @@
for (int s = 0; s < hob->PlatformData.numofIIO; ++s) { for (int x = 0; x < MAX_LOGIC_IIO_STACK; ++x) { - if (s == 0 && x == 0) + if (s == 0 && x == 0) { + dev->name = DOMAIN_TYPE_PCIE; continue; - + } const STACK_RES *ri = &hob->PlatformData.IIO_resource[s].StackRes[x]; if (ri->BusBase > ri->BusLimit) continue; @@ -249,6 +253,7 @@ die("%s: out of memory.\n", __func__);
iio_domain->ops = &iio_pcie_domain_ops; + iio_domain->name = DOMAIN_TYPE_PCIE; } else if (CONFIG(HAVE_IOAT_DOMAINS)) soc_create_ioat_domains(dn, dev->upstream, ri); } diff --git a/src/soc/intel/xeon_sp/include/soc/chip_common.h b/src/soc/intel/xeon_sp/include/soc/chip_common.h index 3727777..a010bd1 100644 --- a/src/soc/intel/xeon_sp/include/soc/chip_common.h +++ b/src/soc/intel/xeon_sp/include/soc/chip_common.h @@ -15,6 +15,20 @@ }; };
+/* + * Every STACK can have multiple PCI domains with an unique domain type. + * This is only of cosmetic nature and generates more readable ACPI code, + * but isn't technical necessary. + */ +#define DOMAIN_TYPE_CPM0 "PM" +#define DOMAIN_TYPE_CPM1 "PN" +#define DOMAIN_TYPE_DINO "DI" +#define DOMAIN_TYPE_HQM0 "HQ" +#define DOMAIN_TYPE_HQM1 "HR" +#define DOMAIN_TYPE_PCIE "PC" +#define DOMAIN_TYPE_UBX0 "UC" +#define DOMAIN_TYPE_UBX1 "UD" + void iio_pci_domain_read_resources(struct device *dev); void iio_pci_domain_scan_bus(struct device *dev); void attach_iio_stacks(struct device *dev); diff --git a/src/soc/intel/xeon_sp/spr/ioat.c b/src/soc/intel/xeon_sp/spr/ioat.c index 0d81d0d..60aae24 100644 --- a/src/soc/intel/xeon_sp/spr/ioat.c +++ b/src/soc/intel/xeon_sp/spr/ioat.c @@ -26,7 +26,8 @@ static void create_ioat_domain(const union xeon_domain_path dp, struct bus *const upstream, const unsigned int bus_base, const unsigned int bus_limit, const resource_t mem32_base, const resource_t mem32_limit, - const resource_t mem64_base, const resource_t mem64_limit) + const resource_t mem64_base, const resource_t mem64_limit, + const char *name) { union xeon_domain_path new_path = { .domain_path = dp.domain_path @@ -44,6 +45,7 @@ die("%s: out of memory.\n", __func__);
domain->ops = &ioat_domain_ops; + domain->name = name;
struct bus *const bus = alloc_bus(domain); bus->secondary = bus_base; @@ -94,14 +96,16 @@ mem64_limit = mem64_base + CPM_MMIO_SIZE - 1; bus_base = sr->BusBase + CPM_BUS_OFFSET; bus_limit = bus_base + CPM_RESERVED_BUS; - create_ioat_domain(path, bus, bus_base, bus_limit, 0, -1, mem64_base, mem64_limit); + create_ioat_domain(path, bus, bus_base, bus_limit, 0, -1, mem64_base, mem64_limit, + DOMAIN_TYPE_CPM0);
/* HQM0 */ mem64_base = mem64_limit + 1; mem64_limit = mem64_base + HQM_MMIO_SIZE - 1; bus_base = sr->BusBase + HQM_BUS_OFFSET; bus_limit = bus_base + HQM_RESERVED_BUS; - create_ioat_domain(path, bus, bus_base, bus_limit, 0, -1, mem64_base, mem64_limit); + create_ioat_domain(path, bus, bus_base, bus_limit, 0, -1, mem64_base, mem64_limit, + DOMAIN_TYPE_HQM0);
/* CPM1 (optional) */ mem64_base = mem64_limit + 1; @@ -109,7 +113,8 @@ bus_base = sr->BusBase + CPM1_BUS_OFFSET; bus_limit = bus_base + CPM_RESERVED_BUS; if (bus_limit <= sr->BusLimit) - create_ioat_domain(path, bus, bus_base, bus_limit, 0, -1, mem64_base, mem64_limit); + create_ioat_domain(path, bus, bus_base, bus_limit, 0, -1, mem64_base, mem64_limit, + DOMAIN_TYPE_CPM1);
/* HQM1 (optional) */ mem64_base = mem64_limit + 1; @@ -117,7 +122,8 @@ bus_base = sr->BusBase + HQM1_BUS_OFFSET; bus_limit = bus_base + HQM_RESERVED_BUS; if (bus_limit <= sr->BusLimit) - create_ioat_domain(path, bus, bus_base, bus_limit, 0, -1, mem64_base, mem64_limit); + create_ioat_domain(path, bus, bus_base, bus_limit, 0, -1, mem64_base, mem64_limit, + DOMAIN_TYPE_HQM1);
/* DINO */ mem64_base = mem64_limit + 1; @@ -125,5 +131,5 @@ bus_base = sr->BusBase; bus_limit = bus_base; create_ioat_domain(path, bus, bus_base, bus_limit, sr->PciResourceMem32Base, sr->PciResourceMem32Limit, - mem64_base, mem64_limit); + mem64_base, mem64_limit, DOMAIN_TYPE_DINO); }