[coreboot-gerrit] Change in coreboot[4.11_branch]: soc/intel/fsp_broadwell_de: examine ACM status at romstage entry

[Philipp Deppenwiese (Code Review)]

Philipp Deppenwiese has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42713 )

Change subject: soc/intel/fsp_broadwell_de: examine ACM status at romstage entry
......................................................................

soc/intel/fsp_broadwell_de: examine ACM status at romstage entry

When INTEL_TXT is set, at romstage entry check if startup ACM worked correctly
by probing TXT_ERROR register.

Signed-off-by: Philipp Deppenwiese 
Signed-off-by: Jonathan Zhang 
Change-Id: I6f423df8b05dc44220a9bad3674f687bac94e335
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42713
Reviewed-by: Angel Pons 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/fsp_broadwell_de/romstage/romstage.c
1 file changed, 9 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Angel Pons: Looks good to me, approved

diff --git a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c
index 8438b10..9699927 100644
--- a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c
+++ b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c
@@ -38,6 +38,9 @@
 #include <soc/ubox.h>
 #include <build.h>

+#include <security/intel/txt/txt.h>
+#include <security/intel/txt/txt_register.h>
+
 static void init_rtc(void)
 {
    u16 gen_pmcon3 = pci_read_config16(PCI_DEV(0, LPC_DEV, LPC_FUNC), GEN_PMCON_3);
@@ -156,6 +159,12 @@
    early_iio_hide();
    timestamp_add_now(TS_BEFORE_INITRAM);
    post_code(0x48);
+
+	if (CONFIG(INTEL_TXT)) {
+		printk(BIOS_DEBUG, "Check TXT_ERROR register\n");
+		intel_txt_log_acm_error(read32((void *)TXT_ERROR));
+	}
+
    /*
     * Call early init to initialize memory and chipset. This function returns
     * to the romstage_main_continue function with a pointer to the HOB