[coreboot-gerrit] Change in coreboot[master]: [WIP] soc/intel/denverton_ns: Use common SMBus support code

[Kyösti Mälkki (Code Review)]

Attention is currently required from: Mariusz Szafrański, Suresh Bellampalli, Vanessa Eusebio, Michal Motyl, Patrick Rudolph.
Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59469 )

Change subject: [WIP] soc/intel/denverton_ns: Use common SMBus support code
......................................................................

[WIP] soc/intel/denverton_ns: Use common SMBus support code

Change-Id: I233d198b894f10fbf0042a5023ae8a9c14136513
Signed-off-by: Kyösti Mälkki 
---
M src/soc/intel/common/block/smbus/smbus.c
M src/soc/intel/denverton_ns/Kconfig
M src/soc/intel/denverton_ns/include/soc/pci_devs.h
M src/soc/intel/denverton_ns/include/soc/smbus.h
4 files changed, 6 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/59469/1

diff --git a/src/soc/intel/common/block/smbus/smbus.c b/src/soc/intel/common/block/smbus/smbus.c
index 4a46143..d0eb9ce 100644
--- a/src/soc/intel/common/block/smbus/smbus.c
+++ b/src/soc/intel/common/block/smbus/smbus.c
@@ -91,6 +91,7 @@
    PCI_DEVICE_ID_INTEL_ADP_P_SMBUS,
    PCI_DEVICE_ID_INTEL_ADP_S_SMBUS,
    PCI_DEVICE_ID_INTEL_ADP_M_SMBUS,
+	PCI_DEVICE_ID_INTEL_DENVERTON_SMBUS_LEGACY,
    0
 };

diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig
index 0643384..37d6ee5 100644
--- a/src/soc/intel/denverton_ns/Kconfig
+++ b/src/soc/intel/denverton_ns/Kconfig
@@ -34,6 +34,7 @@
    select SOC_INTEL_COMMON_BLOCK_FAST_SPI
    select SOC_INTEL_COMMON_BLOCK_GPIO
    select SOC_INTEL_COMMON_BLOCK_PCR
+	select SOC_INTEL_COMMON_BLOCK_SMBUS
    select TSC_MONOTONIC_TIMER
    select TSC_SYNC_MFENCE
    select UDELAY_TSC
diff --git a/src/soc/intel/denverton_ns/include/soc/pci_devs.h b/src/soc/intel/denverton_ns/include/soc/pci_devs.h
index 0cb4c98..9fa38e4 100644
--- a/src/soc/intel/denverton_ns/include/soc/pci_devs.h
+++ b/src/soc/intel/denverton_ns/include/soc/pci_devs.h
@@ -139,9 +139,11 @@
 #define PCH_DEV_SLOT_LPC 0x1f
 #define PCH_DEVFN_LPC _PCH_DEVFN(LPC, 0)
 #define PCH_DEVFN_PMC _PCH_DEVFN(LPC, 2)
+#define PCH_DEVFN_SMBUS _PCH_DEVFN(LPC, 4)
 #define PCH_DEVFN_SPI _PCH_DEVFN(LPC, 5)
 #define PCH_DEV_LPC _PCH_DEV(LPC, 0)
 #define PCH_DEV_SPI _PCH_DEV(LPC, 5)
+#define PCH_DEV_SMBUS _PCH_DEV(LPC, 4)

/* VT-d support value to match FSP settings */
 /* "PCH IOAPIC Config" */
diff --git a/src/soc/intel/denverton_ns/include/soc/smbus.h b/src/soc/intel/denverton_ns/include/soc/smbus.h
index e51d8a7..240a0e9 100644
--- a/src/soc/intel/denverton_ns/include/soc/smbus.h
+++ b/src/soc/intel/denverton_ns/include/soc/smbus.h
@@ -41,6 +41,8 @@
 #define SMLINK_PIN_CTL 0xe
 #define SMBUS_PIN_CTL 0xf

+#define SMBUS_SLAVE_ADDR		0x24
+
 /*
  * SMBus Private Config Registers (PID:SMB)
  */