Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36255 )
Change subject: drivers/intel/fsp1_0: Fake microcode update to make FSP happy ......................................................................
drivers/intel/fsp1_0: Fake microcode update to make FSP happy
The FSP loops through microcode updates and at the end checks if the microcode revision is not zero. Since we update the microcode before loading FSP, this is the case and a fake microcode can be passed to the FSP.
Change-Id: I63cfb7b19e9795da85566733fb4c1ff989e85d03 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/drivers/intel/fsp1_1/cache_as_ram.S 1 file changed, 24 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/36255/1
diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.S b/src/drivers/intel/fsp1_1/cache_as_ram.S index 007b974..b7e21f7 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.S +++ b/src/drivers/intel/fsp1_1/cache_as_ram.S @@ -235,17 +235,39 @@ * esp is set to this location so that the call into and return from the FSP * in find_fsp will work. */ + +/* Put something sensible in here */ +#define MCU_DATA_SIZE 0x10 +#define MCU_HEADER_SIZE 0x30 +#define MCU_TOTAL_SIZE (MCU_HEADER_SIZE + MCU_DATA_SIZE) + .align 4 fake_fsp_stack: .long find_fsp_ret .long CONFIG_FSP_LOC /* FSP base address */
CAR_init_params: - .long CONFIG_CPU_MICROCODE_CBFS_LOC /* Microcode Location */ - .long CONFIG_CPU_MICROCODE_CBFS_LEN /* Microcode Length */ + .long fake_microcode /* Microcode Location */ + .long MCU_TOTAL_SIZE /* Microcode Length */ .long 0xFFFFFFFF - CONFIG_ROM_SIZE + 1 /* Firmware Location */ .long CONFIG_ROM_SIZE /* Firmware Length */
CAR_init_stack: .long CAR_init_done .long CAR_init_params + +fake_microcode: +fake_microcode_header_start: + .long 1 /* Header Version */ + .long 1 /* Microcode revision */ + .long 0x10232019 /* Date: Time of writing 23-10-2019 */ + .long 0x00010ff0 /* Sig: (non existing) Family: 0xf, Model: 0x1f, stepping: 0 */ + .long 0 /* Checksum: not checked by FSP, so won't care */ + .long 1 /* Loader Revision */ + .long 1 /* Processor Flags */ + .long MCU_DATA_SIZE /* Data Size */ + .long MCU_TOTAL_SIZE /* Total Size */ + .space 12 /* Reserved */ +fake_microcode_header_end: + .space MCU_DATA_SIZE +fake_microcode_end: