[coreboot-gerrit] Change in ...coreboot[master]: rockchip: rk3399: increase heap and memory for fit payload.

[Marty E. Plummer (Code Review)]

Marty E. Plummer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32373

Change subject: rockchip: rk3399: increase heap and memory for fit payload.
......................................................................

rockchip: rk3399: increase heap and memory for fit payload.

Change-Id: Iee0ed9f7958588ceda54bb32253c84cac68abea2
Signed-off-by: Marty E. Plummer 
---
M src/soc/rockchip/rk3399/Kconfig
M src/soc/rockchip/rk3399/include/soc/memlayout.ld
2 files changed, 5 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/32373/1

diff --git a/src/soc/rockchip/rk3399/Kconfig b/src/soc/rockchip/rk3399/Kconfig
index 6e45df3..67e36ff 100644
--- a/src/soc/rockchip/rk3399/Kconfig
+++ b/src/soc/rockchip/rk3399/Kconfig
@@ -34,4 +34,7 @@
      used to modulate the frequency of the Silicon Creations' Fractional
      PLL in order to reduce EMI.

+config HEAP_SIZE
+	default 0x100000
+
 endif
diff --git a/src/soc/rockchip/rk3399/include/soc/memlayout.ld b/src/soc/rockchip/rk3399/include/soc/memlayout.ld
index 73fc499..f2512b0 100644
--- a/src/soc/rockchip/rk3399/include/soc/memlayout.ld
+++ b/src/soc/rockchip/rk3399/include/soc/memlayout.ld
@@ -20,8 +20,8 @@
 {
    DRAM_START(0x00000000)
    BL31(0, 0x100000)
-	POSTRAM_CBFS_CACHE(0x00100000, 1M)
-	RAMSTAGE(0x00300000, 256K)
+	POSTRAM_CBFS_CACHE(0x00100000, 16M)
+	RAMSTAGE(0x01100000, 2M)
    DMA_COHERENT(0x10000000, 2M)

/* 8K of special SRAM in PMU power domain. */