[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Speed up postcar loading using intermediate cac...

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34791 )

Change subject: soc/intel/cannonlake: Speed up postcar loading using intermediate caching
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Patch Set 10:

(1 comment)

https://review.coreboot.org/c/coreboot/+/34791/9/src/soc/intel/cannonlake/ro... 
File src/soc/intel/cannonlake/romstage/romstage.c:

https://review.coreboot.org/c/coreboot/+/34791/9/src/soc/intel/cannonlake/ro... 
PS9, Line 167: 	/* Cache the ROM as WP just below 4GiB. */
> i hope you like to add this right ? […]

From provided sample:

0:1st timestamp                                     12,942
  99:selfboot jump                                     663,930 (472)

663,930 - 12,942 = 650,988

0:1st timestamp                                     12,006
  99:selfboot jump                                     662,138 (467)

662,138 - 12,006 = 650,132

to payload:    650,988 - 650,132  = 0,856 ms  improvement
  to OS kernel:  821,421 - 818,805  = 2,616 ms  improvement

I think you are only measuring noise and normal fluctuation of udelay(). I would remove any arguments about 4 ms being saved you have put in the commit message.