Rui Zhou has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85875?usp=email )
Change subject: mb/google/nissa/var/rull: Match VBT with SSFC
......................................................................
mb/google/nissa/var/rull: Match VBT with SSFC
We want to configure different VBT timings for panels of different sizes
and distinguish them through SSFC. We select the reserved bit 6 of SSFC
as the flag bit. When using a AUO panel, set this bit to 1.
Without splitting, the platform_BootPerf test will fail.
BUG=b:379835056
TEST=can match VBT with SSFC
-When SSFC is set to 0x40:
$ cat /sys/firmware/log | grep vbt
Bit 6 of SSFC is 1, use vbt-teliks-auo.bin
Change-Id: I413179af0a1346b7d21f17d728d6846c30707978
Signed-off-by: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/rull/variant.c
1 file changed, 58 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/85875/1
diff --git a/src/mainboard/google/brya/variants/rull/variant.c b/src/mainboard/google/brya/variants/rull/variant.c
index 4f8fd47..d98db5f 100644
--- a/src/mainboard/google/brya/variants/rull/variant.c
+++ b/src/mainboard/google/brya/variants/rull/variant.c
@@ -2,6 +2,9 @@
#include <baseboard/variants.h>
#include <chip.h>
+#include <console/console.h>
+#include <drivers/intel/gma/opregion.h>
+#include <ec/google/chromeec/ec.h>
#include <fw_config.h>
#include <sar.h>
#include <soc/gpio_soc_defs.h>
@@ -41,3 +44,58 @@
graphics_gtt_rmw(TRANS_DDI_FUNC_CTL2_A, ~TRANS_DDI_AUDIO_MUTE_OVERRIDE_BITS_FIELDS,
TRANS_DDI_AUDIO_MUTE_OVERRIDE_BITS_FIELDS);
}
+
+static int get_ssfc(uint32_t *val)
+{
+ static uint32_t known_value;
+ static enum {
+ SSFC_NOT_READ,
+ SSFC_AVAILABLE,
+ } ssfc_state = SSFC_NOT_READ;
+
+ if (ssfc_state == SSFC_AVAILABLE) {
+ *val = known_value;
+ return 0;
+ }
+
+ /*
+ * If SSFC field is not in the CBI then the value of SSFC will be 0 for
+ * further processing later since 0 of each bits group means default
+ * component in a variant. For more detail, please refer to cbi_ssfc.h.
+ */
+ if (google_chromeec_cbi_get_ssfc(&known_value) != 0) {
+ printk(BIOS_DEBUG, "SSFC not set in CBI\n");
+ return -1;
+ }
+
+ ssfc_state = SSFC_AVAILABLE;
+ *val = known_value;
+ printk(BIOS_INFO, "SSFC 0x%x.\n", known_value);
+ return 0;
+}
+
+const char *mainboard_vbt_filename(void)
+{
+ uint32_t ssfc;
+ if (get_ssfc(&ssfc)) {
+ printk(BIOS_INFO, "Failed to read SSFC, using default vbt-rull.bin\n");
+ return "vbt-rull.bin";
+ }
+
+ /*
+ * Determine if the panel is auo based on the SSFC register.
+ *
+ * Bit 6 of the SSFC register indicates the panel vendor:
+ * 0: other pannel
+ * 1: auo panel
+ */
+ bool is_panel_auo = (ssfc >> 6) & 0x1;
+
+ if (is_panel_auo) {
+ printk(BIOS_INFO, "Bit 6 of SSFC is 1, use vbt-rull-auo.bin\n");
+ return "vbt-rull-auo.bin";
+ }
+
+ printk(BIOS_INFO, "Bit 6 of SSFC is 0, use vbt-rull.bin\n");
+ return "vbt-rull.bin";
+}
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Change subject: soc/mediatek/mt8196: Correct the argument type of MT6363
......................................................................
Patch Set 3: Code-Review+2
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Change subject: soc/mediatek/mt8196: Fix MT6363 buck5 enablement
......................................................................
Patch Set 2: Code-Review+2
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Change subject: soc/amd/cezanne: Disable I2S internal clock based on mainboard config
......................................................................
Patch Set 3:
(3 comments)
File src/soc/amd/cezanne/chip.h:
https://review.coreboot.org/c/coreboot/+/85865/comment/5449ecee_f76b8664?us… :
PS2, Line 112:
> Remove extra spaces here
Done
File src/soc/amd/cezanne/fch.c:
https://review.coreboot.org/c/coreboot/+/85865/comment/564fc216_666d8ac9?us… :
PS2, Line 89: /*M
> Add space between comment symbols and text, and correct 'disabled'. […]
Done
https://review.coreboot.org/c/coreboot/+/85865/comment/edeaec2c_6701851b?us… :
PS2, Line 90: used
> using?
Done
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Change subject: soc/amd/cezanne: Disable I2S internal clock based on mainboard config
......................................................................
soc/amd/cezanne: Disable I2S internal clock based on mainboard config
Change-Id: I0c1bee121f528d28d591dace260507b345dfec26
Signed-off-by: Anand Vaikar <a.vaikar2021(a)gmail.com>
---
M src/soc/amd/cezanne/chip.h
M src/soc/amd/cezanne/fch.c
2 files changed, 14 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/85865/3
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Change subject: util/chromeos/crosfirmware: Add special handling for REEF board
......................................................................
Patch Set 3: Code-Review+2
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Hello Felix Singer, build bot (Jenkins),
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Change subject: util/chromeos/crosfirmware: Add special handling for REEF board
......................................................................
util/chromeos/crosfirmware: Add special handling for REEF board
The layout of an extracted REEF shellball doesn't conform to the
usual ones used by other boards, so add a special-case handler for it.
TEST= run `bash croshfirmware.sh reef` and receive the correct firmware
image for the board.
Change-Id: Ib391f30a77b6aa75aa130ffb525e6e1d1239a588
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
M util/chromeos/crosfirmware.sh
1 file changed, 8 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/85873/3
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Change subject: util/chromeos/crosfirmware: Add special handling for REEF board
......................................................................
Patch Set 2:
(1 comment)
File util/chromeos/crosfirmware.sh:
https://review.coreboot.org/c/coreboot/+/85873/comment/6f5602eb_dc239c1f?us… :
PS1, Line 110: \
> While on it, maybe put it in between single quotation marks?
Done
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Hello Felix Singer, build bot (Jenkins),
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The following approvals got outdated and were removed:
Code-Review+2 by Felix Singer, Verified+1 by build bot (Jenkins)
Change subject: util/chromeos/crosfirmware: Add special handling for REEF board
......................................................................
util/chromeos/crosfirmware: Add special handling for REEF board
The layout of an extracted REEF shellball doesn't conform to the
usual ones used by other boards, so add a special-case handler for it.
TEST= run `bash croshfirmware.sh reef` and receive the correct firmware
image for the board.
Change-Id: Ib391f30a77b6aa75aa130ffb525e6e1d1239a588
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
M util/chromeos/crosfirmware.sh
1 file changed, 7 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/85873/2
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