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Change subject: mb/google/brox/jubilant: Modify FP IRQ pin
......................................................................
Patch Set 8:
(1 comment)
Patchset:
PS8:
> Will this affect any devices that have shipped to labs or otherwise? […]
Hi, Bob
Since Jubilant & Jubileum is still in proto stage and we don't ship any boards/system now, then there is no device that will be affected. FYI~
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Change subject: mb/google: amd projects: Add signed verstage files
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
> Could we get release notes and license files added please? […]
I'll file a bug to add.
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Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
......................................................................
Patch Set 71:
(2 comments)
File src/soc/intel/pantherlake/elog.c:
https://review.coreboot.org/c/coreboot/+/83798/comment/ccf7f1b7_5911b64d?us… :
PS71, Line 140:
> should we be adding GPE1 as well here? […]
Yes. The code is ready once GPE1 changes CLs are merged, I will work with
Saurabh to include the changes, including GPE1 changes in include/soc/pm.h and include/soc/gpe.h, as well as tcss ASL files in https://review.coreboot.org/c/coreboot/+/83772.
File src/soc/intel/pantherlake/pmutil.c:
https://review.coreboot.org/c/coreboot/+/83798/comment/b1f8b37c_9f9bf541?us… :
PS71, Line 110:
> should we add GPE1 as well here […]
Yes. The code is ready once GPE1 changes CLs are merged, I will work with
Saurabh to include the changes, including GPE1 changes in include/soc/pm.h and include/soc/gpe.h, as well as tcss ASL files in https://review.coreboot.org/c/coreboot/+/83772.
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Hello Anil Kumar K, Bora Guvendik, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/84104?usp=email
to look at the new patch set (#8).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: soc/intel/common/block/pmc: Add GPE1 functions
......................................................................
soc/intel/common/block/pmc: Add GPE1 functions
- Requires CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_GPE1 flag.
- The existing static gpe functions has been renamed with gpe0.
- Add gpe1 functions.
- Remove functions that enables GPE events. This is not used and should
not be used during boot.
BUG=362310295
TEST=Build with CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_GPE1 flag, boot DUT,
and check if GPE1 sts bits have been printed during boot.
Signed-off-by: Cliff Huang <cliff.huang(a)intel.com>
Change-Id: I7ac1fbe6d45cbe0c86c3f72911900d92a186168d
---
M src/soc/intel/common/block/include/intelblocks/pmclib.h
M src/soc/intel/common/block/pmc/pmclib.c
2 files changed, 72 insertions(+), 16 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/84104/8
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