coreboot-gerrit September 2024

coreboot-gerrit@coreboot.org

1 participants
2100 discussions

[M] Change in coreboot[main]: soc/intel/cnvi: Add CNVW OpRegion
by Sean Rhodes (Code Review) 02 Sep '24

02 Sep '24

Attention is currently required from: Matt DeVillier, Nico Huber, Sean Rhodes. Hello Matt DeVillier, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83556?usp=email to look at the new patch set (#15). The following approvals got outdated and were removed: Code-Review+1 by Matt DeVillier, Verified+1 by build bot (Jenkins) Change subject: soc/intel/cnvi: Add CNVW OpRegion ...................................................................... soc/intel/cnvi: Add CNVW OpRegion The CNVi driver is relatively basic in coreboot and most noticeably, recent Linux kernels flag that lack of a _PRR method, which is used to reset WiFi and Bluetooth. This patch series adds methods recommended by Intel in document #559910. This patch defines an OpRegion for CNVi, for both integrated and dedicated solutions. Change-Id: Idd2ff93fb65c40f656804d96966e1881202ccb56 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> --- M src/soc/intel/common/block/cnvi/cnvi.c A src/soc/intel/common/block/include/intelblocks/cnvi.h 2 files changed, 95 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/83556/15 -- To view, visit https://review.coreboot.org/c/coreboot/+/83556?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idd2ff93fb65c40f656804d96966e1881202ccb56 Gerrit-Change-Number: 83556 Gerrit-PatchSet: 15 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com>

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[S] Change in coreboot[main]: soc/intel/cnvi: Add AOLX Method
by Sean Rhodes (Code Review) 02 Sep '24

02 Sep '24

Sean Rhodes has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/83716?usp=email ) Change subject: soc/intel/cnvi: Add AOLX Method ...................................................................... Abandoned Not needed -- To view, visit https://review.coreboot.org/c/coreboot/+/83716?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: abandon Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibeafb2b6e8a702430dcf10eb28bfeb9f77aa29b4 Gerrit-Change-Number: 83716 Gerrit-PatchSet: 12 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[L] Change in coreboot[main]: [WIP] mb/hardkernel/odroid-h4: add initial odroid-h4 support
by Angel Pons (Code Review) 02 Sep '24

02 Sep '24

Attention is currently required from: Alicja Michalska, David Milosevic. Angel Pons has posted comments on this change by David Milosevic. ( https://review.coreboot.org/c/coreboot/+/83979?usp=email ) Change subject: [WIP] mb/hardkernel/odroid-h4: add initial odroid-h4 support ...................................................................... Patch Set 3: (1 comment) File src/mainboard/hardkernel/odroid-h4/devicetree.cb: https://review.coreboot.org/c/coreboot/+/83979/comment/f78bf613_3fcad56e?us… : PS2, Line 82: #device ref pcie_rp3 on : # register "pch_pcie_rp[PCH_RP(3)]" = "{ : # .clk_src = 2, : # .clk_req = 2, : # .flags = PCIE_RP_CLK_REQ_DETECT, : # }" : # smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" : # "M.2/M 2280 (M2_SSD1)" "SlotDataBusWidth2X" : #end : #device ref pcie_rp7 on # LAN1 : # register "pch_pcie_rp[PCH_RP(7)]" = "{ : # .clk_src = 3, : # .clk_req = 3, : # .flags = PCIE_RP_CLK_REQ_DETECT, : # }" : #end : #device ref pcie_rp9 on # LAN2 : # register "pch_pcie_rp[PCH_RP(9)]" = "{ : # .clk_src = 0, : # .clk_req = 0, : # .flags = PCIE_RP_CLK_REQ_DETECT, : # }" : #end : #device ref pcie_rp10 on : # register "pch_pcie_rp[PCH_RP(10)]" = "{ : # .clk_src = 1, : # .clk_req = 1, : # .flags = PCIE_RP_CLK_REQ_DETECT, : # }" : # smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" : # "M.2/E 2230 (M2_WIFI1)" "SlotDataBusWidth1X" : #end > Hi and thanks for your help, Angel :) […] The only meaningful difference I see is that you've disabled ASPM, which can help if the CLKREQ stuff is misconfigured. I based my previous comment on the schematics, so it should work as long as the schematics (and my interpretation of them) is correct. -- To view, visit https://review.coreboot.org/c/coreboot/+/83979?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7e0d395ba3d15dfcf6d47a222b90499ca371e4eb Gerrit-Change-Number: 83979 Gerrit-PatchSet: 3 Gerrit-Owner: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Attention: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Comment-Date: Mon, 02 Sep 2024 19:53:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: David Milosevic <David.Milosevic(a)9elements.com>

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[L] Change in coreboot[main]: [WIP] mb/hardkernel/odroid-h4: add initial odroid-h4 support
by David Milosevic (Code Review) 02 Sep '24

02 Sep '24

Attention is currently required from: Alicja Michalska, Angel Pons. David Milosevic has posted comments on this change by David Milosevic. ( https://review.coreboot.org/c/coreboot/+/83979?usp=email ) Change subject: [WIP] mb/hardkernel/odroid-h4: add initial odroid-h4 support ...................................................................... Patch Set 3: (6 comments) File src/mainboard/hardkernel/odroid-h4/devicetree.cb: https://review.coreboot.org/c/coreboot/+/83979/comment/e66059a0_694aa326?us… : PS2, Line 17: register "s0ix_enable" = "1" > It's unlikely that you'll get s0ix working with IT8613E unfortunately. […] Done https://review.coreboot.org/c/coreboot/+/83979/comment/f4f98129_ecd6425f?us… : PS2, Line 84: # .clk_src = 2, > Nice, schematics are also available from the Odroid wiki: https://wiki.odroid. […] Thanks for your help, Alicja :) https://review.coreboot.org/c/coreboot/+/83979/comment/ba25d755_60f3badf?us… : PS2, Line 82: #device ref pcie_rp3 on : # register "pch_pcie_rp[PCH_RP(3)]" = "{ : # .clk_src = 2, : # .clk_req = 2, : # .flags = PCIE_RP_CLK_REQ_DETECT, : # }" : # smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" : # "M.2/M 2280 (M2_SSD1)" "SlotDataBusWidth2X" : #end : #device ref pcie_rp7 on # LAN1 : # register "pch_pcie_rp[PCH_RP(7)]" = "{ : # .clk_src = 3, : # .clk_req = 3, : # .flags = PCIE_RP_CLK_REQ_DETECT, : # }" : #end : #device ref pcie_rp9 on # LAN2 : # register "pch_pcie_rp[PCH_RP(9)]" = "{ : # .clk_src = 0, : # .clk_req = 0, : # .flags = PCIE_RP_CLK_REQ_DETECT, : # }" : #end : #device ref pcie_rp10 on : # register "pch_pcie_rp[PCH_RP(10)]" = "{ : # .clk_src = 1, : # .clk_req = 1, : # .flags = PCIE_RP_CLK_REQ_DETECT, : # }" : # smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" : # "M.2/E 2230 (M2_WIFI1)" "SlotDataBusWidth1X" : #end > I've left it commented out so that the differences are easier to see, but you should obviously uncom […] Hi and thanks for your help, Angel :) We already had something similar for the NVME but did not update this patch yet: ``` device ref pcie_rp9 on register "pch_pcie_rp[PCH_RP(9)]" = "{ .flags = PCIE_RP_LTR | PCIE_RP_AER, .clk_src = 0, .clk_req = 0, .pcie_rp_aspm = ASPM_DISABLE, }" end ``` I am going to give your proposal a try and hopefully it will fix our NVME issue. Thanks again. https://review.coreboot.org/c/coreboot/+/83979/comment/033eb9fc_661bdb7c?us… : PS2, Line 141: device pnp 2e.6 on end # Mouse > From what I can see, this board doesn't have PS/2 ports. […] Done https://review.coreboot.org/c/coreboot/+/83979/comment/cd2038c1_60e7ea61?us… : PS2, Line 148: device pnp 2e.a on end # CIR > CIR seems unused as well Done https://review.coreboot.org/c/coreboot/+/83979/comment/fbcfdd38_3635b293?us… : PS2, Line 156: device ref gspi0 on : register "serial_io_gspi_mode" = "{ : [PchSerialIoIndexGSPI0] = PchSerialIoPci, : }" : end > GSPI0 pins are disconnected in the schematic, this can be disabled. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/83979?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7e0d395ba3d15dfcf6d47a222b90499ca371e4eb Gerrit-Change-Number: 83979 Gerrit-PatchSet: 3 Gerrit-Owner: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Mon, 02 Sep 2024 19:46:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Alicja Michalska <ahplka19(a)gmail.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[L] Change in coreboot[main]: [WIP] mb/hardkernel/odroid-h4: add initial odroid-h4 support
by David Milosevic (Code Review) 02 Sep '24

02 Sep '24

Attention is currently required from: Alicja Michalska, David Milosevic. Hello Angel Pons, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83979?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: [WIP] mb/hardkernel/odroid-h4: add initial odroid-h4 support ...................................................................... [WIP] mb/hardkernel/odroid-h4: add initial odroid-h4 support This patch adds support for the odroid-h4 board. Note, that this is still a work in progress and was not yet properly tested on real hardware. Change-Id: I7e0d395ba3d15dfcf6d47a222b90499ca371e4eb Signed-off-by: David Milosevic <David.Milosevic(a)9elements.com> --- A src/mainboard/hardkernel/Kconfig A src/mainboard/hardkernel/Kconfig.name A src/mainboard/hardkernel/odroid-h4/Kconfig A src/mainboard/hardkernel/odroid-h4/Kconfig.name A src/mainboard/hardkernel/odroid-h4/Makefile.mk A src/mainboard/hardkernel/odroid-h4/board_info.txt A src/mainboard/hardkernel/odroid-h4/bootblock.c A src/mainboard/hardkernel/odroid-h4/data.vbt A src/mainboard/hardkernel/odroid-h4/devicetree.cb A src/mainboard/hardkernel/odroid-h4/dsdt.asl A src/mainboard/hardkernel/odroid-h4/gpio.h A src/mainboard/hardkernel/odroid-h4/ramstage_fsp_params.c A src/mainboard/hardkernel/odroid-h4/romstage_fsp_params.c 13 files changed, 529 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/83979/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/83979?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7e0d395ba3d15dfcf6d47a222b90499ca371e4eb Gerrit-Change-Number: 83979 Gerrit-PatchSet: 3 Gerrit-Owner: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Attention: David Milosevic <David.Milosevic(a)9elements.com>

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[M] Change in coreboot[main]: tree: Use boolean for dptf_enable
by Elyes Haouas (Code Review) 02 Sep '24

02 Sep '24

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Eric Lai, Frans Hendriks, Jakub Czapiga, Jayvik Desai, Jonathon Hall, Kapil Porwal, Lean Sheng Tan, Maxim, Michał Żygowski, Nick Vaccaro, Nico Huber, Piotr Król, Pranava Y N, Rishika Raj, Subrata Banik, Tarun, Werner Zeh. Elyes Haouas has posted comments on this change by Elyes Haouas. ( https://review.coreboot.org/c/coreboot/+/84161?usp=email ) Change subject: tree: Use boolean for dptf_enable ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > I prefer true/false. It reduce ambiguity and potential errors and it prepare for modern C. […] while on it, please see https://review.coreboot.org/c/coreboot/+/83909/6 when you have time -- To view, visit https://review.coreboot.org/c/coreboot/+/84161?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic6e578199e7e4ca3a014eecb1eb7a4d9d24893b8 Gerrit-Change-Number: 84161 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Mon, 02 Sep 2024 18:33:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <ericllai(a)google.com> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Elyes Haouas <ehaouas(a)noos.fr>

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[M] Change in coreboot[main]: tree: Use boolean for dptf_enable
by Elyes Haouas (Code Review) 02 Sep '24

02 Sep '24

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Eric Lai, Frans Hendriks, Jakub Czapiga, Jayvik Desai, Jonathon Hall, Kapil Porwal, Lean Sheng Tan, Maxim, Michał Żygowski, Nick Vaccaro, Nico Huber, Piotr Król, Pranava Y N, Rishika Raj, Subrata Banik, Tarun, Werner Zeh. Elyes Haouas has posted comments on this change by Elyes Haouas. ( https://review.coreboot.org/c/coreboot/+/84161?usp=email ) Change subject: tree: Use boolean for dptf_enable ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > Create ,macro like #define ENABLED true #define DISABLED false, then you can use in device tree? I prefer true/false. It reduce ambiguity and potential errors and it prepare for modern C. (C23 uses true and false instead of 0 and 1) -- To view, visit https://review.coreboot.org/c/coreboot/+/84161?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic6e578199e7e4ca3a014eecb1eb7a4d9d24893b8 Gerrit-Change-Number: 84161 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Mon, 02 Sep 2024 18:31:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <ericllai(a)google.com> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de>

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[XS] Change in coreboot[main]: util/inteltool: pci ids are 16 bit
by Angel Pons (Code Review) 02 Sep '24

02 Sep '24

Attention is currently required from: Alexander Couzens, Felix Held, Paul Menzel, Pratikkumar V Prajapati. Angel Pons has posted comments on this change by Alexander Couzens. ( https://review.coreboot.org/c/coreboot/+/84186?usp=email ) Change subject: util/inteltool: pci ids are 16 bit ...................................................................... Patch Set 1: Code-Review+2 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/84186/comment/1f460be5_977883d6?us… : PS1, Line 7: pci ids are 16 bit > util/inteltool: Fix format for PCI vendor/device IDs https://review.coreboot.org/c/coreboot/+/84186/comment/542aa157_4b6c584b?us… : PS1, Line 8: > Maybe print log before and after? I don't think it's needed -- To view, visit https://review.coreboot.org/c/coreboot/+/84186?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I87804a63f04b7461d348a245531542776575eb7a Gerrit-Change-Number: 84186 Gerrit-PatchSet: 1 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 02 Sep 2024 17:09:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[L] Change in coreboot[main]: inteltool: elkhartlake: keep the same names as coreboot code uses
by Alexander Couzens (Code Review) 02 Sep '24

02 Sep '24

Attention is currently required from: Pratikkumar V Prajapati. Hello Pratikkumar V Prajapati, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84190?usp=email to look at the new patch set (#2). Change subject: inteltool: elkhartlake: keep the same names as coreboot code uses ...................................................................... inteltool: elkhartlake: keep the same names as coreboot code uses coreboot doesn't have a leading zero in gpio < 10. E.g. G00 -> G0 Change-Id: I4558cec444ae2a081fbc0f49464354df222be6c9 --- M util/inteltool/gpio_names/elkhartlake.h 1 file changed, 131 insertions(+), 131 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/84190/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84190?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4558cec444ae2a081fbc0f49464354df222be6c9 Gerrit-Change-Number: 84190 Gerrit-PatchSet: 2 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com>

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[L] Change in coreboot[main]: intelp2m: add support for elkhartlake
by Alexander Couzens (Code Review) 02 Sep '24

02 Sep '24

Attention is currently required from: Maxim. Alexander Couzens has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84191?usp=email ) Change subject: intelp2m: add support for elkhartlake ...................................................................... intelp2m: add support for elkhartlake Change-Id: I0f60d182bc5cc3d0d1d1177fbda0cfe8e2279e46 --- M util/intelp2m/config/config.go M util/intelp2m/main.go M util/intelp2m/parser/parser.go A util/intelp2m/platforms/ehl/macro.go A util/intelp2m/platforms/ehl/template.go 5 files changed, 340 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/84191/1 diff --git a/util/intelp2m/config/config.go b/util/intelp2m/config/config.go index 5578a05..b388b98 100644 --- a/util/intelp2m/config/config.go +++ b/util/intelp2m/config/config.go @@ -33,6 +33,7 @@ JasperType uint8 = 6 MeteorType uint8 = 7 EmmitsburgType uint8 = 8 + ElkhartType uint8 = 9 ) var key uint8 = SunriseType @@ -41,6 +42,7 @@ "snr": SunriseType, "lbg": LewisburgType, "apl": ApolloType, + "ehl": ElkhartType, "cnl": CannonType, "tgl": TigerType, "adl": AlderType, @@ -85,6 +87,9 @@ func IsPlatformEmmitsburg() bool { return IsPlatform(EmmitsburgType) } +func IsPlatformElkhartLake() bool { + return IsPlatform(ElkhartType) +} var InputRegDumpFile *os.File = nil var OutputGenFile *os.File = nil diff --git a/util/intelp2m/main.go b/util/intelp2m/main.go index 38a3b5fc..03adfe4 100644 --- a/util/intelp2m/main.go +++ b/util/intelp2m/main.go @@ -68,6 +68,7 @@ "\tsnr - Sunrise PCH or Skylake/Kaby Lake SoC\n"+ "\tlbg - Lewisburg PCH with Xeon SP\n"+ "\tapl - Apollo Lake SoC\n"+ + "\tehl - Elkhart Lake SoC\n"+ "\tcnl - CannonLake-LP or Whiskeylake/Coffeelake/Cometlake-U SoC\n"+ "\ttgl - TigerLake-H SoC\n"+ "\tadl - AlderLake PCH\n"+ diff --git a/util/intelp2m/parser/parser.go b/util/intelp2m/parser/parser.go index fd3191d..394ebc0 100644 --- a/util/intelp2m/parser/parser.go +++ b/util/intelp2m/parser/parser.go @@ -10,6 +10,7 @@ "review.coreboot.org/coreboot.git/util/intelp2m/platforms/snr" "review.coreboot.org/coreboot.git/util/intelp2m/platforms/lbg" "review.coreboot.org/coreboot.git/util/intelp2m/platforms/apl" + "review.coreboot.org/coreboot.git/util/intelp2m/platforms/ehl" "review.coreboot.org/coreboot.git/util/intelp2m/platforms/cnl" "review.coreboot.org/coreboot.git/util/intelp2m/platforms/tgl" "review.coreboot.org/coreboot.git/util/intelp2m/platforms/adl" @@ -150,6 +151,7 @@ InheritanceTemplate : snr.PlatformSpecific{}, }, config.ApolloType : apl.PlatformSpecific{}, + config.ElkhartType : ehl.PlatformSpecific{}, config.CannonType : cnl.PlatformSpecific{ InheritanceTemplate : snr.PlatformSpecific{}, }, diff --git a/util/intelp2m/platforms/ehl/macro.go b/util/intelp2m/platforms/ehl/macro.go new file mode 100644 index 0000000..7e1d66e --- /dev/null +++ b/util/intelp2m/platforms/ehl/macro.go @@ -0,0 +1,310 @@ +package ehl + +import ( + "fmt" + "strconv" + + "review.coreboot.org/coreboot.git/util/intelp2m/platforms/common" + "review.coreboot.org/coreboot.git/util/intelp2m/config" + "review.coreboot.org/coreboot.git/util/intelp2m/fields" +) + +const ( + PAD_CFG_DW0_RO_FIELDS = (0x1 << 27) | (0xf << 14) | 0xfc + PAD_CFG_DW1_RO_FIELDS = 0xfffc00ff +) + +const ( + PAD_CFG_DW0 = common.PAD_CFG_DW0 + PAD_CFG_DW1 = common.PAD_CFG_DW1 + MAX_DW_NUM = common.MAX_DW_NUM +) + +const ( + PULL_NONE = 0x0 // 0 000: none + PULL_DN_1K = 0x1 // 0 001: 1k wpd + PULL_DN_5K = 0x2 // 0 010: 5k wpd + PULL_DN_20K = 0x4 // 0 100: 20k wpd + PULL_UP_1K_5K_20K = 0x8 // 1 000: 20k & 5k & 1k wpu + PULL_UP_1K = 0x9 // 1 001: 1k wpu + PULL_UP_5K = 0xa // 1 010: 5k wpu + PULL_UP_1K_5K = 0xb // 1 011: 1k & 5k wpu + PULL_UP_20K = 0xc // 1 100: 20k wpu + PULL_UP_1K_20K = 0xd // 1 101: 20k & 1k wpu + PULL_UP_5K_20K = 0xe // 1 110: 20k & 5k wpu + PULL_NATIVE = 0xf // 1 111: (optional) Native controller selected by Pad Mode +) + +type PlatformSpecific struct {} + +// RemmapRstSrc - remmap Pad Reset Source Config +// remmap is not required because it is the same as common. +func (PlatformSpecific) RemmapRstSrc() {} + +// Adds The Pad Termination (TERM) parameter from DW1 to the macro as a new argument +// return: macro +func (PlatformSpecific) Pull() { + macro := common.GetMacro() + dw1 := macro.Register(PAD_CFG_DW1) + var pull = map[uint8]string{ + PULL_NONE: "NONE", + PULL_DN_1K: "DN_1K", + PULL_DN_5K: "DN_5K", + PULL_DN_20K: "DN_20K", + PULL_UP_1K_5K_20K: "UP_1K_5K_20K", + PULL_UP_1K: "UP_1K", + PULL_UP_5K: "UP_5K", + PULL_UP_1K_5K: "UP_1K_5K", + PULL_UP_20K: "UP_20K", + PULL_UP_1K_20K: "UP_1K_20K", + PULL_UP_5K_20K: "UP_5K_20K", + PULL_NATIVE: "NATIVE", + } + terminationFieldValue := dw1.GetTermination() + str, valid := pull[terminationFieldValue] + if !valid { + str = strconv.Itoa(int(terminationFieldValue)) + fmt.Println("Error", macro.PadIdGet(), " invalid TERM value = ", str) + } + macro.Separator().Add(str) +} + +// Generate macro to cause peripheral IRQ when configured in GPIO input mode +func ioApicRoute() bool { + macro := common.GetMacro() + dw0 := macro.Register(PAD_CFG_DW0) + dw1 := macro.Register(PAD_CFG_DW1) + if dw0.GetGPIOInputRouteIOxAPIC() == 0 { + return false + } + macro.Add("_APIC") + if dw1.GetIOStandbyState() != 0 || dw1.GetIOStandbyTermination() != 0 { + // e.g. H1_PCH_INT_ODL + // PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, LEVEL, INVERT, TxDRxE, DISPUPD), + macro.Add("_IOS(").Id().Pull().Rstsrc().Trig().Invert().IOSstate().IOTerm() + } else { + // PAD_CFG_GPI_APIC(pad, pull, rst, trig, inv) + macro.Add("(").Id().Pull().Rstsrc().Trig().Invert().Add("),") + } + macro.Add("),") + return true +} + +// Generate macro to cause NMI when configured in GPIO input mode +func nmiRoute() bool { + macro := common.GetMacro() + if macro.Register(PAD_CFG_DW0).GetGPIOInputRouteNMI() == 0 { + return false + } + // e.g. PAD_CFG_GPI_NMI(GPIO_24, UP_20K, DEEP, LEVEL, INVERT), + macro.Add("_NMI").Add("(").Id().Pull().Rstsrc().Trig().Invert().Add("),") + return true +} + +// Generate macro to cause SCI when configured in GPIO input mode +func sciRoute() bool { + macro := common.GetMacro() + dw0 := macro.Register(PAD_CFG_DW0) + dw1 := macro.Register(PAD_CFG_DW0) + if dw0.GetGPIOInputRouteSCI() == 0 { + return false + } + if dw1.GetIOStandbyState() != 0 || dw1.GetIOStandbyTermination() != 0 { + // PAD_CFG_GPI_SCI_IOS(GPIO_141, NONE, DEEP, EDGE_SINGLE, INVERT, IGNORE, DISPUPD), + macro.Add("_SCI_IOS") + macro.Add("(").Id().Pull().Rstsrc().Trig().Invert().IOSstate().IOTerm() + } else if dw0.GetRXLevelEdgeConfiguration() & 0x1 != 0 { + // e.g. PAD_CFG_GPI_ACPI_SCI(GPP_G2, NONE, DEEP, YES), + macro.Add("_ACPI_SCI").Add("(").Id().Pull().Rstsrc().Invert() + } else { + // e.g. PAD_CFG_GPI_SCI(GPP_B18, UP_20K, PLTRST, LEVEL, INVERT), + macro.Add("_SCI").Add("(").Id().Pull().Rstsrc().Trig().Invert() + } + macro.Add("),") + return true +} + +// Generate macro to cause SMI when configured in GPIO input mode +func smiRoute() bool { + macro := common.GetMacro() + dw0 := macro.Register(PAD_CFG_DW0) + dw1 := macro.Register(PAD_CFG_DW1) + if dw0.GetGPIOInputRouteSMI() == 0 { + return false + } + if dw1.GetIOStandbyState() != 0 || dw1.GetIOStandbyTermination() != 0 { + // PAD_CFG_GPI_SMI_IOS(GPIO_41, UP_20K, DEEP, EDGE_SINGLE, NONE, IGNORE, SAME), + macro.Add("_SMI_IOS") + macro.Add("(").Id().Pull().Rstsrc().Trig().Invert().IOSstate().IOTerm() + } else if dw0.GetRXLevelEdgeConfiguration() & 0x1 != 0 { + // e.g. PAD_CFG_GPI_ACPI_SMI(GPP_I3, NONE, DEEP, YES), + macro.Add("_ACPI_SMI").Add("(").Id().Pull().Rstsrc().Invert() + } else { + // e.g. PAD_CFG_GPI_SMI(GPP_E3, NONE, PLTRST, EDGE_SINGLE, NONE), + macro.Add("_SMI").Add("(").Id().Pull().Rstsrc().Trig().Invert() + } + macro.Add("),") + return true +} + +// Generate macro for GPI port +func (PlatformSpecific) GpiMacroAdd() { + macro := common.GetMacro() + var ids []string + macro.Set("PAD_CFG_GPI") + for routeid, isRoute := range map[string]func() (bool) { + "IOAPIC": ioApicRoute, + "SCI": sciRoute, + "SMI": smiRoute, + "NMI": nmiRoute, + } { + if isRoute() { + ids = append(ids, routeid) + } + } + + switch argc := len(ids); argc { + case 0: + dw1 := macro.Register(PAD_CFG_DW1) + isIOStandbyStateUsed := dw1.GetIOStandbyState() != 0 + isIOStandbyTerminationUsed := dw1.GetIOStandbyTermination() != 0 + if isIOStandbyStateUsed && !isIOStandbyTerminationUsed { + macro.Add("_TRIG_IOSSTATE_OWN(") + // PAD_CFG_GPI_TRIG_IOSSTATE_OWN(pad, pull, rst, trig, iosstate, own) + macro.Id().Pull().Rstsrc().Trig().IOSstate().Own().Add("),") + } else if isIOStandbyTerminationUsed { + macro.Add("_TRIG_IOS_OWN(") + // PAD_CFG_GPI_TRIG_IOS_OWN(pad, pull, rst, trig, iosstate, iosterm, own) + macro.Id().Pull().Rstsrc().Trig().IOSstate().IOTerm().Own().Add("),") + } else { + // PAD_CFG_GPI_TRIG_OWN(pad, pull, rst, trig, own) + macro.Add("_TRIG_OWN(").Id().Pull().Rstsrc().Trig().Own().Add("),") + } + case 1: + // GPI with IRQ route + if config.AreFieldsIgnored() { + macro.SetPadOwnership(common.PAD_OWN_ACPI) + } + case 2: + // PAD_CFG_GPI_DUAL_ROUTE(pad, pull, rst, trig, inv, route1, route2) + macro.Set("PAD_CFG_GPI_DUAL_ROUTE(").Id().Pull().Rstsrc().Trig().Invert() + macro.Add(", " + ids[0] + ", " + ids[1] + "),") + if config.AreFieldsIgnored() { + macro.SetPadOwnership(common.PAD_OWN_ACPI) + } + default: + // Clear the control mask so that the check fails and "Advanced" macro is + // generated + macro.Register(PAD_CFG_DW0).CntrMaskFieldsClear(common.AllFields) + } +} + + +// Adds PAD_CFG_GPO macro with arguments +func (PlatformSpecific) GpoMacroAdd() { + macro := common.GetMacro() + dw0 := macro.Register(PAD_CFG_DW0) + dw1 := macro.Register(PAD_CFG_DW1) + term := dw1.GetTermination() + + macro.Set("PAD_CFG") + if dw1.GetIOStandbyState() != 0 || dw1.GetIOStandbyTermination() != 0 { + // PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_91, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD), + // PAD_CFG_GPO_IOSSTATE_IOSTERM(pad, val, rst, pull, iosstate, ioterm) + macro.Add("_GPO_IOSSTATE_IOSTERM(").Id().Val().Rstsrc().Pull().IOSstate().IOTerm() + } else { + if term != 0 { + // e.g. PAD_CFG_TERM_GPO(GPP_B23, 1, DN_20K, DEEP), + // PAD_CFG_TERM_GPO(pad, val, pull, rst) + macro.Add("_TERM") + } + macro.Add("_GPO(").Id().Val() + if term != 0 { + macro.Pull() + } + macro.Rstsrc() + } + macro.Add("),") + + if dw0.GetRXLevelEdgeConfiguration() != common.TRIG_OFF { + // ignore if trig = OFF is not set + dw0.CntrMaskFieldsClear(common.RxLevelEdgeConfigurationMask) + } +} + +// Adds PAD_CFG_NF macro with arguments +func (PlatformSpecific) NativeFunctionMacroAdd() { + macro := common.GetMacro() + dw1 := macro.Register(PAD_CFG_DW1) + isIOStandbyStateUsed := dw1.GetIOStandbyState() != 0 + isIOStandbyTerminationUsed := dw1.GetIOStandbyTermination() != 0 + + macro.Set("PAD_CFG_NF") + if !isIOStandbyTerminationUsed && isIOStandbyStateUsed { + if dw1.GetIOStandbyState() == common.StandbyIgnore { + // PAD_CFG_NF_IOSTANDBY_IGNORE(PMU_SLP_S0_B, NONE, DEEP, NF1), + macro.Add("_IOSTANDBY_IGNORE(").Id().Pull().Rstsrc().Padfn() + } else { + // PAD_CFG_NF_IOSSTATE(GPIO_22, UP_20K, DEEP, NF2, TxDRxE), + macro.Add("_IOSSTATE(").Id().Pull().Rstsrc().Padfn().IOSstate() + } + } else if isIOStandbyTerminationUsed { + // PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_103, NATIVE, DEEP, NF1, MASK, SAME), + macro.Add("_IOSSTATE_IOSTERM(").Id().Pull().Rstsrc().Padfn().IOSstate().IOTerm() + } else { + // e.g. PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1) + macro.Add("(").Id().Pull().Rstsrc().Padfn() + } + macro.Add("),") + + if dw0 := macro.Register(PAD_CFG_DW0); dw0.GetGPIORxTxDisableStatus() != 0 { + // Since the bufbis parameter will be ignored for NF, we should clear + // the corresponding bits in the control mask. + dw0.CntrMaskFieldsClear(common.RxTxBufDisableMask) + } +} + +// Adds PAD_NC macro +func (PlatformSpecific) NoConnMacroAdd() { + macro := common.GetMacro() + dw1 := macro.Register(PAD_CFG_DW1) + + if dw1.GetIOStandbyState() == common.TxDRxE { + dw0 := macro.Register(PAD_CFG_DW0) + + // See comments in sunrise/macro.go : NoConnMacroAdd() + if dw0.GetRXLevelEdgeConfiguration() != common.TRIG_OFF { + dw0.CntrMaskFieldsClear(common.RxLevelEdgeConfigurationMask) + } + if dw0.GetResetConfig() != 1 { // 1 = RST_DEEP + dw0.CntrMaskFieldsClear(common.PadRstCfgMask) + } + + // PAD_NC(OSC_CLK_OUT_1, DN_20K) + macro.Set("PAD_NC").Add("(").Id().Pull().Add("),") + return + } + // PAD_CFG_GPIO_HI_Z(GPIO_81, UP_20K, DEEP, HIZCRx0, DISPUPD), + macro.Set("PAD_CFG_GPIO_") + if macro.IsOwnershipDriver() { + // PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_55, UP_20K, DEEP, HIZCRx1, ENPU), + macro.Add("DRIVER_") + } + macro.Add("HI_Z(").Id().Pull().Rstsrc().IOSstate().IOTerm().Add("),") +} + +// GenMacro - generate pad macro +// dw0 : DW0 config register value +// dw1 : DW1 config register value +// return: string of macro +// error +func (PlatformSpecific) GenMacro(id string, dw0 uint32, dw1 uint32, ownership uint8) string { + macro := common.GetInstanceMacro(PlatformSpecific{}, fields.InterfaceGet()) + // use platform-specific interface in Macro struct + macro.PadIdSet(id).SetPadOwnership(ownership) + macro.Register(PAD_CFG_DW0).CntrMaskFieldsClear(common.AllFields) + macro.Register(PAD_CFG_DW0).CntrMaskFieldsClear(common.AllFields) + macro.Register(PAD_CFG_DW0).ValueSet(dw0).ReadOnlyFieldsSet(PAD_CFG_DW0_RO_FIELDS) + macro.Register(PAD_CFG_DW1).ValueSet(dw1).ReadOnlyFieldsSet(PAD_CFG_DW1_RO_FIELDS) + return macro.Generate() +} diff --git a/util/intelp2m/platforms/ehl/template.go b/util/intelp2m/platforms/ehl/template.go new file mode 100644 index 0000000..3d4de85 --- /dev/null +++ b/util/intelp2m/platforms/ehl/template.go @@ -0,0 +1,22 @@ +package ehl + +import "review.coreboot.org/coreboot.git/util/intelp2m/platforms/common" + +// GroupNameExtract - This function extracts the group ID, if it exists in a row +// line : string from the configuration file +// return +// bool : true if the string contains a group identifier +// string : group identifier +func (PlatformSpecific) GroupNameExtract(line string) (bool, string) { + // Not supported + return false, "" +} + +// KeywordCheck - This function is used to filter parsed lines of the configuration file and +// returns true if the keyword is contained in the line. +// line : string from the configuration file +func (PlatformSpecific) KeywordCheck(line string) bool { + isIncluded, _ := common.KeywordsCheck(line, + "GPP_", "GPD_", "GPIO_", "VGPIO_") + return isIncluded +} -- To view, visit https://review.coreboot.org/c/coreboot/+/84191?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0f60d182bc5cc3d0d1d1177fbda0cfe8e2279e46 Gerrit-Change-Number: 84191 Gerrit-PatchSet: 1 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Attention: Maxim <max.senia.poliak(a)gmail.com>

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