Attention is currently required from: Julius Werner, Yu-Ping Wu.
Yidi Lin has posted comments on this change by Yu-Ping Wu. ( https://review.coreboot.org/c/coreboot/+/84204?usp=email )
Change subject: util/cbfstool: Print max empty entry size in error message
......................................................................
Patch Set 1: Code-Review+1
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84204/comment/1f9abed4_b0707b55?us… :
PS1, Line 9: print
prints
--
To view, visit https://review.coreboot.org/c/coreboot/+/84204?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: comment
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I00bcc83abe8b0a33dcd7b75521e6cfccd8953661
Gerrit-Change-Number: 84204
Gerrit-PatchSet: 1
Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com>
Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org>
Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com>
Gerrit-Attention: Julius Werner <jwerner(a)chromium.org>
Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>
Gerrit-Comment-Date: Wed, 04 Sep 2024 04:36:41 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: Yes
Attention is currently required from: Ashish Kumar Mishra, Jérémy Compostella, Martin Roth, Pratikkumar V Prajapati, Subrata Banik.
Hello Jérémy Compostella, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/84142?usp=email
to look at the new patch set (#16).
Change subject: src/include: Introduce a new BIT_FLAG_32(x) macro
......................................................................
src/include: Introduce a new BIT_FLAG_32(x) macro
Introduces the BIT_FLAG_32(x) macro to create a 32-bit mask with the
designated bit set. This ensures compatibility with the 32-bit
'GEN_PMCON_A' register on 64-bit systems, where 1ul is 64 bits wide and
could potentially cause an overflow when shifted beyond 31 bits.
Change-Id: I70be1ccba59d25af2ba85a2014232072abf2f87d
Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com>
---
M src/include/types.h
1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/84142/16
--
To view, visit https://review.coreboot.org/c/coreboot/+/84142?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: newpatchset
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I70be1ccba59d25af2ba85a2014232072abf2f87d
Gerrit-Change-Number: 84142
Gerrit-PatchSet: 16
Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com>
Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com>
Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com>
Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com>
Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com>
Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com>
Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com>
Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com>
Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com>
Gerrit-CC: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com>
Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com>
Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com>
Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com>
Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com>
Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com>
Gerrit-Attention: Subrata Banik <subratabanik(a)google.com>
Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com>
Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com>
Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com>
Attention is currently required from: Anand Vaikar, Bao Zheng, Felix Held, Zheng Bao, ritul guru.
Hello Anand Vaikar, Felix Held, Marshall Dawson, Zheng Bao, build bot (Jenkins), ritul guru,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/84194?usp=email
to look at the new patch set (#2).
Change subject: amdfwtool: Set L2 table size as 0x400
......................................................................
amdfwtool: Set L2 table size as 0x400
The Max size of L2 table is 0x400. If we set it to other value, the
the A/B recovery image can not boot on Cezanne/Majolica platform.
The affected boards are Birman, Chausie, Skyrim, Mayan. Other boards
are binary identical. Tested on Skyrim and image can boot.
Change-Id: I2c0af6579dbe2a3a61e1fe9c79d69491fd45a5bb
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
---
M util/amdfwtool/amdfwtool.c
M util/amdfwtool/amdfwtool.h
2 files changed, 4 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/84194/2
--
To view, visit https://review.coreboot.org/c/coreboot/+/84194?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: newpatchset
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I2c0af6579dbe2a3a61e1fe9c79d69491fd45a5bb
Gerrit-Change-Number: 84194
Gerrit-PatchSet: 2
Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com>
Gerrit-Reviewer: Anand Vaikar <a.vaikar2021(a)gmail.com>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Gerrit-Reviewer: Zheng Bao
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com>
Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com>
Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com>
Gerrit-Attention: Zheng Bao
Gerrit-Attention: Anand Vaikar <a.vaikar2021(a)gmail.com>
Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>
Attention is currently required from: Bao Zheng, Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Zheng Bao.
Hello Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Zheng Bao, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/84195?usp=email
to look at the new patch set (#2).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: Cezanne: Add an option to enable A/B recovery scheme
......................................................................
Cezanne: Add an option to enable A/B recovery scheme
The A/B recovery scheme formally separates the SPI flash space into
different partitions; a primary, “A” and secondary, “B”, which hold
the same set of system firmware. Under this scheme, the partitions A
and B can hold identical contents initially, but each partition can be
updated individually.
Normally the system boots from partition A, but if the A partition is
found to be corrupted, the system will switch to partition B and
boot. The OEM BIOS can then choose to continue the boot from partition
B, or repair partition A using contents from partition B.
The Cezanne platform supports both A/B recovery and no recovery
method and need this flag passed to amdfwtool to enable/disable the
A/B recovery layout.
Change-Id: Id1c8028faee9c544628d65fd77be2a378ed7eab6
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
---
M src/soc/amd/cezanne/Kconfig
M src/soc/amd/cezanne/Makefile.mk
2 files changed, 9 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/84195/2
--
To view, visit https://review.coreboot.org/c/coreboot/+/84195?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: newpatchset
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: Id1c8028faee9c544628d65fd77be2a378ed7eab6
Gerrit-Change-Number: 84195
Gerrit-PatchSet: 2
Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com>
Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com>
Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com>
Gerrit-Reviewer: Zheng Bao
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com>
Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com>
Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com>
Gerrit-Attention: Zheng Bao
Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com>
Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>
Attention is currently required from: Jérémy Compostella, Kapil Porwal, Pranava Y N, Subrata Banik.
Hello Kapil Porwal, Pranava Y N, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83798?usp=email
to look at the new patch set (#81).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
......................................................................
soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
List of changes:
1. Add required SoC programming till ramstage.
2. Include only required headers into include/soc.
3. Skeleton code used to call FSP-S API.
BUG=b:348678529
TEST=Verified on Intel® Simics® Pre Silicon Simulation platform
for PTL using google/fatcat mainboard.
Change-Id: Idc6fb11e9e84c28c7567ae2b7abc1ab832a88362
Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com>
---
M src/soc/intel/pantherlake/Kconfig
M src/soc/intel/pantherlake/Makefile.mk
A src/soc/intel/pantherlake/acpi.c
A src/soc/intel/pantherlake/chip.c
M src/soc/intel/pantherlake/chip.h
M src/soc/intel/pantherlake/chipset.cb
A src/soc/intel/pantherlake/cpu.c
A src/soc/intel/pantherlake/crashlog.c
A src/soc/intel/pantherlake/cse_telemetry.c
A src/soc/intel/pantherlake/elog.c
A src/soc/intel/pantherlake/finalize.c
A src/soc/intel/pantherlake/fsp_params.c
A src/soc/intel/pantherlake/gspi.c
A src/soc/intel/pantherlake/i2c.c
A src/soc/intel/pantherlake/include/soc/cpu.h
A src/soc/intel/pantherlake/include/soc/crashlog.h
A src/soc/intel/pantherlake/include/soc/dptf.h
M src/soc/intel/pantherlake/include/soc/iomap.h
A src/soc/intel/pantherlake/include/soc/irq.h
A src/soc/intel/pantherlake/include/soc/itss.h
A src/soc/intel/pantherlake/include/soc/nvs.h
M src/soc/intel/pantherlake/include/soc/p2sb.h
A src/soc/intel/pantherlake/include/soc/pcie.h
M src/soc/intel/pantherlake/include/soc/pmc.h
A src/soc/intel/pantherlake/include/soc/ramstage.h
A src/soc/intel/pantherlake/include/soc/serialio.h
M src/soc/intel/pantherlake/include/soc/systemagent.h
A src/soc/intel/pantherlake/include/soc/tcss.h
A src/soc/intel/pantherlake/include/soc/usb.h
A src/soc/intel/pantherlake/lockdown.c
A src/soc/intel/pantherlake/p2sb.c
A src/soc/intel/pantherlake/pcie_rp.c
A src/soc/intel/pantherlake/pmc.c
A src/soc/intel/pantherlake/pmutil.c
A src/soc/intel/pantherlake/retimer.c
A src/soc/intel/pantherlake/smihandler.c
A src/soc/intel/pantherlake/soundwire.c
A src/soc/intel/pantherlake/spi.c
A src/soc/intel/pantherlake/systemagent.c
A src/soc/intel/pantherlake/tcss.c
A src/soc/intel/pantherlake/uart.c
A src/soc/intel/pantherlake/xhci.c
42 files changed, 3,743 insertions(+), 106 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/83798/81
--
To view, visit https://review.coreboot.org/c/coreboot/+/83798?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: newpatchset
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: Idc6fb11e9e84c28c7567ae2b7abc1ab832a88362
Gerrit-Change-Number: 83798
Gerrit-PatchSet: 81
Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com>
Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com>
Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com>
Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com>
Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com>
Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com>
Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com>
Gerrit-CC: Cliff Huang <cliff.huang(a)intel.com>
Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com>
Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com>
Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com>
Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com>
Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com>
Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com>
Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com>
Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com>
Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com>
Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com>
Gerrit-Attention: Subrata Banik <subratabanik(a)google.com>
Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com>
Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com>
Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>
Attention is currently required from: Ashish Kumar Mishra, Jérémy Compostella, Martin Roth, Pratikkumar V Prajapati, Subrata Banik.
Saurabh Mishra has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/84142?usp=email )
Change subject: src/include: Introduce a new BIT_FLAG_32(x) macro
......................................................................
Patch Set 14:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84142/comment/29d0bc1a_0058df3e?us… :
PS14, Line 7: src/include: Introducing a new SET_32_BIT_FLAG(x) macro.
> Remove the . at the end of line.
Acknowledged
https://review.coreboot.org/c/coreboot/+/84142/comment/d61efe96_961fc49d?us… :
PS14, Line 9: This new macro addition ensures the shift operation does not
> This is a generic macro. Please describe the macro here. […]
Acknowledged
https://review.coreboot.org/c/coreboot/+/84142/comment/21046f58_a8f90382?us… :
PS14, Line 12: On a 64-bit system, 1ul will typically be 64 bits wide.
: The left shift can accommodate values of x up to 63 without overflowing.
: But `GEN_PMCON_A` register width is 32-bit hence, adding new SET_32_BIT_FLAG(x)
: to limit the register to max 32-bit width.
> yes
Done
--
To view, visit https://review.coreboot.org/c/coreboot/+/84142?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: comment
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I70be1ccba59d25af2ba85a2014232072abf2f87d
Gerrit-Change-Number: 84142
Gerrit-PatchSet: 14
Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com>
Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com>
Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com>
Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com>
Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com>
Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com>
Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com>
Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com>
Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com>
Gerrit-CC: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com>
Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com>
Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com>
Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com>
Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com>
Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com>
Gerrit-Attention: Subrata Banik <subratabanik(a)google.com>
Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com>
Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com>
Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com>
Gerrit-Comment-Date: Wed, 04 Sep 2024 03:34:58 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Comment-In-Reply-To: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com>
Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>