coreboot-gerrit September 2024

coreboot-gerrit@coreboot.org

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2094 discussions

[XS] Change in coreboot[main]: FIXME remove asserts for mt8186 code
by Yu-Ping Wu (Code Review) 04 Sep '24

04 Sep '24

Attention is currently required from: Arthur Heymans, Hung-Te Lin, Yidi Lin. Yu-Ping Wu has posted comments on this change by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/84208?usp=email ) Change subject: FIXME remove asserts for mt8186 code ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84208?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6185e87a374f8722dba545d6bbce1c3a8de53e7e Gerrit-Change-Number: 84208 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Wed, 04 Sep 2024 06:19:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/dedede/var/beadrix: Add LTE only daughterboard support
by Kevin Yang (Code Review) 04 Sep '24

04 Sep '24

Kevin Yang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84209?usp=email ) Change subject: mb/google/dedede/var/beadrix: Add LTE only daughterboard support ...................................................................... mb/google/dedede/var/beadrix: Add LTE only daughterboard support Add FW_CONFIG for no port LTE skus, and probe 1A port in devicetree to match program.star config BUG=b:364431483 BRANCH=firmware-dedede-13606.B TEST=emerge-dedede coreboot chromeos-bootimage flash and check boot log on DUT. Change-Id: Ica5a2d6e19421b132a0bdbad77806a17e2c1ce69 Signed-off-by: Kevin Yang <kevin.yang(a)ecs.corp-partner.google.com> --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/mainboard/google/dedede/variants/beadrix/gpio.c M src/mainboard/google/dedede/variants/beadrix/overridetree.cb 3 files changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/84209/1 diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index cc2b66d..d0ed6f1 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -10,6 +10,7 @@ option DB_PORTS_1C 7 option DB_PORTS_1A_HDMI_LTE 8 option DB_PORTS_LTE 9 + option DB_PORTS_1A 10 end field STYLUS 4 option STYLUS_ABSENT 0 diff --git a/src/mainboard/google/dedede/variants/beadrix/gpio.c b/src/mainboard/google/dedede/variants/beadrix/gpio.c index 131cb96..70ba6d5 100644 --- a/src/mainboard/google/dedede/variants/beadrix/gpio.c +++ b/src/mainboard/google/dedede/variants/beadrix/gpio.c @@ -122,7 +122,8 @@ static void fw_config_handle(void *unused) { - if (!fw_config_probe(FW_CONFIG(DB_PORTS, DB_PORTS_1C_LTE))) + if (!fw_config_probe(FW_CONFIG(DB_PORTS, DB_PORTS_1C_LTE)) && + !fw_config_probe(FW_CONFIG(DB_PORTS, DB_PORTS_LTE))) gpio_configure_pads(lte_disable_pads, ARRAY_SIZE(lte_disable_pads)); } BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL); diff --git a/src/mainboard/google/dedede/variants/beadrix/overridetree.cb b/src/mainboard/google/dedede/variants/beadrix/overridetree.cb index 0554baf..0c911e0 100644 --- a/src/mainboard/google/dedede/variants/beadrix/overridetree.cb +++ b/src/mainboard/google/dedede/variants/beadrix/overridetree.cb @@ -141,6 +141,7 @@ register "enable_delay_ms" = "20" device usb 3.3 on probe DB_PORTS DB_PORTS_1C_LTE + probe DB_PORTS DB_PORTS_LTE end end end @@ -239,6 +240,7 @@ register "reg_irq_cfg2" = "0x00" device i2c 28 on probe DB_PORTS DB_PORTS_1C_LTE + probe DB_PORTS DB_PORTS_LTE end end end # I2C 5 -- To view, visit https://review.coreboot.org/c/coreboot/+/84209?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ica5a2d6e19421b132a0bdbad77806a17e2c1ce69 Gerrit-Change-Number: 84209 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Yang <kevin.yang(a)ecs.corp-partner.google.com>

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[L] Change in coreboot[main]: soc/intel/common/block/imc: Add Integrated Memory Controller driver
by Shuo Liu (Code Review) 04 Sep '24

04 Sep '24

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[S] Change in coreboot[main]: soc/intel/{adl,mtl}: Don't set up SPD on LPDDRx
by Subrata Banik (Code Review) 04 Sep '24

04 Sep '24

Attention is currently required from: Arthur Heymans, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Rishika Raj, Tarun. Subrata Banik has posted comments on this change by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/84205?usp=email ) Change subject: soc/intel/{adl,mtl}: Don't set up SPD on LPDDRx ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/meteorlake/meminit.c: https://review.coreboot.org/c/coreboot/+/84205/comment/1e519def_bb45be4f?us… : PS2, Line 209: has_spd = true; Can you help me understand the purpose of `has_spd`? Does it mean the mainboard has an SPD chip and we'll read the hex file using SMBUS? -- To view, visit https://review.coreboot.org/c/coreboot/+/84205?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib3d4ed8032bb06b6d08fbc2dc4b697df88745243 Gerrit-Change-Number: 84205 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Wed, 04 Sep 2024 05:48:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[L] Change in coreboot[main]: soc/intel/common/block/imc: Add Integrated Memory Controller driver
by Shuo Liu (Code Review) 04 Sep '24

04 Sep '24

Attention is currently required from: Felix Singer, Jérémy Compostella, yuchi.chen(a)intel.com. Shuo Liu has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/83320?usp=email ) Change subject: soc/intel/common/block/imc: Add Integrated Memory Controller driver ...................................................................... Patch Set 17: (3 comments) File src/soc/intel/common/block/include/intelblocks/imc.h: https://review.coreboot.org/c/coreboot/+/83320/comment/cf22705f_29736879?us… : PS15, Line 10: > I moved it to an internal header imclib.h. Done File src/soc/intel/common/block/smbus/smbuslib.c: https://review.coreboot.org/c/coreboot/+/83320/comment/f4c0d837_a3eb18c4?us… : PS7, Line 38: static void spd_read(u8 *spd, u8 addr) > This function is not the actual SPD IO function, it calls spd_read_byte(), spd_read_word() and spd_w […] Done File src/soc/intel/common/block/smbus/smbuslib.c: https://review.coreboot.org/c/coreboot/+/83320/comment/55b6641c_3e7fc342?us… : PS15, Line 1: /* SPDX-License-Identifier: GPL-2.0-only */ > Please review https://review.coreboot.org/c/coreboot/+/84201. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/83320?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3f47ddeda94d3882852d64c0052f8fb42b6b7ad2 Gerrit-Change-Number: 83320 Gerrit-PatchSet: 17 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Wed, 04 Sep 2024 05:46:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: yuchi.chen(a)intel.com Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com>

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[M] Change in coreboot[main]: soc/intel: Refactor ITSS macros
by Dinesh Gehlot (Code Review) 04 Sep '24

04 Sep '24

Attention is currently required from: Arthur Heymans, Christian Walter, Eran Mitrani, Jakub Czapiga, Jayvik Desai, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Nick Vaccaro, Patrick Rudolph, Rishika Raj, Subrata Banik, Tarun, Tim Chu, Werner Zeh. Dinesh Gehlot has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/84183?usp=email ) Change subject: soc/intel: Refactor ITSS macros ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84183?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6461dc93b0d21bec5429075bc26435bae3754d74 Gerrit-Change-Number: 84183 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 04 Sep 2024 05:44:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: FIXME remove asserts for mt8186 code
by Arthur Heymans (Code Review) 04 Sep '24

04 Sep '24

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Arthur Heymans has posted comments on this change by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/84208?usp=email ) Change subject: FIXME remove asserts for mt8186 code ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: I don't know the SOC and mainboards to know if the asserts are wrong or if the input is wrong. -- To view, visit https://review.coreboot.org/c/coreboot/+/84208?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6185e87a374f8722dba545d6bbce1c3a8de53e7e Gerrit-Change-Number: 84208 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 04 Sep 2024 05:44:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: soc/intel/{adl,mtl}: Don't set up SPD on LPDDRx
by Arthur Heymans (Code Review) 04 Sep '24

04 Sep '24

Attention is currently required from: Dinesh Gehlot, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Rishika Raj, Subrata Banik. Hello Dinesh Gehlot, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Rishika Raj, Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84205?usp=email to look at the new patch set (#2). Change subject: soc/intel/{adl,mtl}: Don't set up SPD on LPDDRx ...................................................................... soc/intel/{adl,mtl}: Don't set up SPD on LPDDRx The common code for SPD is invalid for LPDDRx, so don't call it as it is not needed. Change-Id: Ib3d4ed8032bb06b6d08fbc2dc4b697df88745243 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/alderlake/meminit.c M src/soc/intel/meteorlake/meminit.c 2 files changed, 20 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/84205/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84205?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib3d4ed8032bb06b6d08fbc2dc4b697df88745243 Gerrit-Change-Number: 84205 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>

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[XS] Change in coreboot[main]: FIXME remove asserts for mt8186 code
by Arthur Heymans (Code Review) 04 Sep '24

04 Sep '24

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84208?usp=email ) Change subject: FIXME remove asserts for mt8186 code ...................................................................... FIXME remove asserts for mt8186 code With LTO GCC is able to assert this statically and found that voltages are incorrectly set. Change-Id: I6185e87a374f8722dba545d6bbce1c3a8de53e7e Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/mediatek/mt8186/mt6366.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/84208/1 diff --git a/src/soc/mediatek/mt8186/mt6366.c b/src/soc/mediatek/mt8186/mt6366.c index 9dbf483..0f29cf1 100644 --- a/src/soc/mediatek/mt8186/mt6366.c +++ b/src/soc/mediatek/mt8186/mt6366.c @@ -591,7 +591,7 @@ u16 cali_trim; assert(vddq_uv >= 530000); - assert(vddq_uv <= 680000); + //assert(vddq_uv <= 680000); /* Round down to multiple of 10 */ target_mv = (vddq_uv / 1000) / 10 * 10; @@ -735,7 +735,7 @@ static void pmic_set_vrf12_vol(u32 vrf12_uv) { - assert(vrf12_uv == VRF12_VOLTAGE_UV); + //assert(vrf12_uv == VRF12_VOLTAGE_UV); pwrap_write_field(PMIC_LDO_VRF12_CON0, 1, 0x3, 0); pwrap_write_field(PMIC_LDO_VRF12_OP_EN, 1, 0x3, 0); } @@ -799,7 +799,7 @@ static void pmic_set_vio18_vol(u32 vio18_uv) { - assert(vio18_uv == VIO18_VOLTAGE_UV); + //assert(vio18_uv == VIO18_VOLTAGE_UV); pwrap_write_field(PMIC_LDO_VIO18_CON0, 1, 0x1, 0); } -- To view, visit https://review.coreboot.org/c/coreboot/+/84208?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6185e87a374f8722dba545d6bbce1c3a8de53e7e Gerrit-Change-Number: 84208 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>

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[XS] Change in coreboot[main]: mb/cwwk/ald: Remove DIMM_MAX
by Arthur Heymans (Code Review) 04 Sep '24

04 Sep '24

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84207?usp=email ) Change subject: mb/cwwk/ald: Remove DIMM_MAX ...................................................................... mb/cwwk/ald: Remove DIMM_MAX For ADL DIMM_MAX is a soc property and not a mainboard property. Change-Id: I834b631ffb9b7b2272ec631122de61136e55651a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/cwwk/adl/Kconfig 1 file changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/84207/1 diff --git a/src/mainboard/cwwk/adl/Kconfig b/src/mainboard/cwwk/adl/Kconfig index c6c0aa3..7f6c33a 100644 --- a/src/mainboard/cwwk/adl/Kconfig +++ b/src/mainboard/cwwk/adl/Kconfig @@ -19,9 +19,6 @@ config MAINBOARD_PART_NUMBER default "CW-AL-4L-V1.0" -config DIMM_MAX - default 2 - config NO_POST default y -- To view, visit https://review.coreboot.org/c/coreboot/+/84207?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I834b631ffb9b7b2272ec631122de61136e55651a Gerrit-Change-Number: 84207 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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coreboot-gerrit September 2024