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Change subject: Revert "Makefile.mk: Use Walloc-size GCC option"
......................................................................
Patch Set 2: Code-Review+2
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Change subject: src/mainboard/intel/frost_creek: add a new CRB Frost Creek for SNR
......................................................................
src/mainboard/intel/frost_creek: add a new CRB Frost Creek for SNR
Change-Id: If3b387a6a4a567415aef21e520056c23b8cfa013
Signed-off-by: Yuchi Chen <yuchi.chen(a)intel.com>
---
A src/mainboard/intel/frost_creek/COPYING-NOTICE
A src/mainboard/intel/frost_creek/Kconfig
A src/mainboard/intel/frost_creek/Kconfig.name
A src/mainboard/intel/frost_creek/Makefile.mk
A src/mainboard/intel/frost_creek/acpi/mainboard.asl
A src/mainboard/intel/frost_creek/acpi/platform.asl
A src/mainboard/intel/frost_creek/acpi_tables.c
A src/mainboard/intel/frost_creek/board.fmd
A src/mainboard/intel/frost_creek/board_id.c
A src/mainboard/intel/frost_creek/board_id.h
A src/mainboard/intel/frost_creek/board_info.txt
A src/mainboard/intel/frost_creek/devicetree.cb
A src/mainboard/intel/frost_creek/dsdt.asl
A src/mainboard/intel/frost_creek/gpio.inc
A src/mainboard/intel/frost_creek/ramstage.c
A src/mainboard/intel/frost_creek/ramstage.h
A src/mainboard/intel/frost_creek/romstage.c
A src/mainboard/intel/frost_creek/romstage.h
18 files changed, 676 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/83322/2
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Change subject: src/soc/intel/snowridge: add support for Intel Atom Snow Ridge SoC
......................................................................
src/soc/intel/snowridge: add support for Intel Atom Snow Ridge SoC
Change-Id: I32ad836dfaaff0d1816eac41e5a7d19ece11080f
Signed-off-by: Yuchi Chen <yuchi.chen(a)intel.com>
---
A src/soc/intel/snowridge/COPYING-NOTICE
A src/soc/intel/snowridge/Kconfig
A src/soc/intel/snowridge/Makefile.mk
A src/soc/intel/snowridge/acpi.c
A src/soc/intel/snowridge/acpi/hostbridges.asl
A src/soc/intel/snowridge/acpi/ith.asl
A src/soc/intel/snowridge/acpi/lpc.asl
A src/soc/intel/snowridge/acpi/pch_irqs.asl
A src/soc/intel/snowridge/acpi/pci_irqs.asl
A src/soc/intel/snowridge/acpi/pcie.asl
A src/soc/intel/snowridge/acpi/pcie_port.asl
A src/soc/intel/snowridge/acpi/pmc.asl
A src/soc/intel/snowridge/acpi/sata0.asl
A src/soc/intel/snowridge/acpi/sata2.asl
A src/soc/intel/snowridge/acpi/sleepstates.asl
A src/soc/intel/snowridge/acpi/smbus.asl
A src/soc/intel/snowridge/acpi/southcluster.asl
A src/soc/intel/snowridge/acpi/uncore.asl
A src/soc/intel/snowridge/bootblock/bootblock.c
A src/soc/intel/snowridge/bootblock/bootblock.h
A src/soc/intel/snowridge/bootblock/early_uart_init.c
A src/soc/intel/snowridge/chip.c
A src/soc/intel/snowridge/chip.h
A src/soc/intel/snowridge/common/fsp_hob.c
A src/soc/intel/snowridge/common/fsp_hob.h
A src/soc/intel/snowridge/common/gpio.c
A src/soc/intel/snowridge/common/hob_display.c
A src/soc/intel/snowridge/common/kti_cache.c
A src/soc/intel/snowridge/common/kti_cache.h
A src/soc/intel/snowridge/common/pmclib.c
A src/soc/intel/snowridge/common/reset.c
A src/soc/intel/snowridge/common/spi.c
A src/soc/intel/snowridge/common/uart8250mem.c
A src/soc/intel/snowridge/common/uart8250mem.h
A src/soc/intel/snowridge/common/upd_display.c
A src/soc/intel/snowridge/cpu.c
A src/soc/intel/snowridge/finalize.c
A src/soc/intel/snowridge/heci.c
A src/soc/intel/snowridge/hob_iiouds.h
A src/soc/intel/snowridge/hqm.c
A src/soc/intel/snowridge/include/soc/acpi.h
A src/soc/intel/snowridge/include/soc/cpu.h
A src/soc/intel/snowridge/include/soc/gpio.h
A src/soc/intel/snowridge/include/soc/gpio_defs.h
A src/soc/intel/snowridge/include/soc/gpio_snr.h
A src/soc/intel/snowridge/include/soc/gpmr.h
A src/soc/intel/snowridge/include/soc/iomap.h
A src/soc/intel/snowridge/include/soc/irq.h
A src/soc/intel/snowridge/include/soc/itss.h
A src/soc/intel/snowridge/include/soc/lpc.h
A src/soc/intel/snowridge/include/soc/msr.h
A src/soc/intel/snowridge/include/soc/nvs.h
A src/soc/intel/snowridge/include/soc/p2sb.h
A src/soc/intel/snowridge/include/soc/pci_devs.h
A src/soc/intel/snowridge/include/soc/pci_ids.h
A src/soc/intel/snowridge/include/soc/pcr_ids.h
A src/soc/intel/snowridge/include/soc/pm.h
A src/soc/intel/snowridge/include/soc/pmc.h
A src/soc/intel/snowridge/include/soc/sata.h
A src/soc/intel/snowridge/include/soc/smbus.h
A src/soc/intel/snowridge/include/soc/soc_chip.h
A src/soc/intel/snowridge/include/soc/systemagent.h
A src/soc/intel/snowridge/lockdown.c
A src/soc/intel/snowridge/lpc.c
A src/soc/intel/snowridge/memmap.c
A src/soc/intel/snowridge/nis.c
A src/soc/intel/snowridge/qat.c
A src/soc/intel/snowridge/ramstage.h
A src/soc/intel/snowridge/romstage/gpio_snr.c
A src/soc/intel/snowridge/romstage/romstage.c
A src/soc/intel/snowridge/sata.c
A src/soc/intel/snowridge/smihandler.c
A src/soc/intel/snowridge/sriov.c
A src/soc/intel/snowridge/systemagent.c
74 files changed, 5,897 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/83321/2
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Change subject: src/soc/intel/common/block/imc: add Integrated Memory Controller driver
......................................................................
src/soc/intel/common/block/imc: add Integrated Memory Controller driver
This patch wraps the smbus IO calls with weak spd IO functions so that
firmware could use IMC to get SPD data.
Change-Id: I3f47ddeda94d3882852d64c0052f8fb42b6b7ad2
Signed-off-by: Yuchi Chen <yuchi.chen(a)intel.com>
---
M src/include/spd_bin.h
A src/soc/intel/common/block/imc/Kconfig
A src/soc/intel/common/block/imc/Makefile.mk
A src/soc/intel/common/block/imc/imc.c
A src/soc/intel/common/block/imc/spd.c
M src/soc/intel/common/block/include/intelblocks/imc.h
M src/soc/intel/common/block/smbus/smbuslib.c
M src/southbridge/intel/common/smbus.c
8 files changed, 293 insertions(+), 18 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/83320/2
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Change subject: src/soc/intel/common/systemagent: improve systemagent
......................................................................
src/soc/intel/common/systemagent: improve systemagent
1. The TOLUD and TOUUD register in systemagent indicate address limit or
address limit plus 1 on different SoCs. This patch add supports for it.
2. Make BDSM, BGSM and CAPID_A registers invisible for some SoC.
Change-Id: If32c2a6524c9d55ce7f9c3dd203bcf85cab76c2c
Signed-off-by: Yuchi Chen <yuchi.chen(a)intel.com>
---
M src/soc/intel/common/block/systemagent/Kconfig
M src/soc/intel/common/block/systemagent/systemagent.c
M src/soc/intel/common/block/systemagent/systemagent_def.h
M src/soc/intel/common/block/systemagent/systemagent_early.c
4 files changed, 116 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/83318/2
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Change subject: src/soc/intel/common/block/include/intelblocks/gpio.h: add new field
......................................................................
src/soc/intel/common/block/include/intelblocks/gpio.h: add new field
Add pad_own_reg_0 to `struct pad_community`.
Change-Id: I30a934fd00a7a42cb156341da1954e4e4b1231d8
Signed-off-by: Yuchi Chen <yuchi.chen(a)intel.com>
---
M src/soc/intel/common/block/include/intelblocks/gpio.h
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/83315/2
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Jian Tong has posted comments on this change by Wentao Qin. ( https://review.coreboot.org/c/coreboot/+/83323?usp=email )
Change subject: mb/google/lotso: Select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS
......................................................................
Patch Set 1: Code-Review+1
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