Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83229?usp=email )
Change subject: soc/intel/cmn/cse: Modify dependency on CSE EOP configs
......................................................................
soc/intel/cmn/cse: Modify dependency on CSE EOP configs
Refactor CSE lite End-of-Post (EOP) configs to support
the alternative of sending CSE communication from the payload.
When the SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD config is selected, coreboot
will skip initiating CSE EOP operations and rely on the payload CSE
driver implementation.
The following configs are modified to ensure coreboot skips CSE
communication when SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD is enabled:
- SOC_INTEL_CSE_SEND_EOP_EARLY
- SOC_INTEL_CSE_SEND_EOP_LATE
- SOC_INTEL_CSE_SEND_EOP_ASYNC
- SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD
BUG=b:305898363
TEST=Able to build google/rex.
Change-Id: Ia6b616163d02be8d637b134fd3728c391fc63c90
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83229
Reviewed-by: Dinesh Gehlot <digehlot(a)google.com>
Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com>
Reviewed-by: Eric Lai <ericllai(a)google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/soc/intel/common/block/cse/Kconfig
1 file changed, 3 insertions(+), 7 deletions(-)
Approvals:
Dinesh Gehlot: Looks good to me, approved
build bot (Jenkins): Verified
Nick Vaccaro: Looks good to me, approved
Eric Lai: Looks good to me, but someone else must approve
diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig
index 966726e..d8d2456 100644
--- a/src/soc/intel/common/block/cse/Kconfig
+++ b/src/soc/intel/common/block/cse/Kconfig
@@ -97,7 +97,7 @@
config SOC_INTEL_CSE_SEND_EOP_EARLY
bool "CSE send EOP early"
- depends on SOC_INTEL_COMMON_BLOCK_CSE
+ depends on SOC_INTEL_COMMON_BLOCK_CSE && !SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD
help
Use this config to send End Of Post (EOP) earlier through SoC code in order to
reduce time required to send EOP and getting CSE response.
@@ -106,7 +106,7 @@
config SOC_INTEL_CSE_SEND_EOP_LATE
bool
- depends on SOC_INTEL_COMMON_BLOCK_CSE
+ depends on SOC_INTEL_COMMON_BLOCK_CSE && !SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD
help
Use this config to send End Of Post (EOP) late (even after CSE `final` operation)
using boot state either `BS_PAYLOAD_BOOT` or `BS_PAYLOAD_LOAD` from common code
@@ -119,7 +119,7 @@
config SOC_INTEL_CSE_SEND_EOP_ASYNC
bool
- depends on SOC_INTEL_COMMON_BLOCK_CSE
+ depends on SOC_INTEL_COMMON_BLOCK_CSE && !SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD
depends on !SOC_INTEL_CSE_SEND_EOP_LATE
depends on !SOC_INTEL_CSE_SEND_EOP_EARLY
help
@@ -139,10 +139,6 @@
config SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD
bool
depends on SOC_INTEL_COMMON_BLOCK_CSE
- depends on !SOC_INTEL_CSE_SEND_EOP_LATE
- depends on !SOC_INTEL_CSE_SEND_EOP_EARLY
- depends on !SOC_INTEL_CSE_SEND_EOP_ASYNC
- depends on !DISABLE_HECI1_AT_PRE_BOOT
help
Use this config to specify that the payload will send the End Of Post (EOP) instead
of coreboot.
--
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Gerrit-MessageType: merged
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Gerrit-Change-Id: Ia6b616163d02be8d637b134fd3728c391fc63c90
Gerrit-Change-Number: 83229
Gerrit-PatchSet: 3
Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>
Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com>
Gerrit-Reviewer: Eric Lai <ericllai(a)google.com>
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Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83228?usp=email )
Change subject: soc/intel/cmn/cse: Modify dependency on CSE lite configs
......................................................................
soc/intel/cmn/cse: Modify dependency on CSE lite configs
Refactor CSE lite configs (specifically CSE sync related) to support
the alternative of sending CSE communication from the payload.
When the SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD config is selected, coreboot
will skip initiating CSE sync operations and rely on the payload CSE
driver implementation.
The following configs are modified to ensure coreboot skips CSE
communication when SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD is enabled:
- SOC_INTEL_CSE_LITE_PSR
- SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY
- SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE
- SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE
BUG=b:305898363
TEST=Able to build google/rex.
Change-Id: I5ddaf6e29949231db84b14bf7ea2d34866bb8e6c
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83228
Reviewed-by: Eric Lai <ericllai(a)google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot(a)google.com>
Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com>
---
M src/soc/intel/common/block/cse/Kconfig
1 file changed, 4 insertions(+), 3 deletions(-)
Approvals:
Nick Vaccaro: Looks good to me, approved
Dinesh Gehlot: Looks good to me, approved
build bot (Jenkins): Verified
Eric Lai: Looks good to me, but someone else must approve
diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig
index edc7e23..966726e 100644
--- a/src/soc/intel/common/block/cse/Kconfig
+++ b/src/soc/intel/common/block/cse/Kconfig
@@ -169,7 +169,7 @@
config SOC_INTEL_CSE_LITE_PSR
bool
default n
- depends on SOC_INTEL_CSE_LITE_SKU
+ depends on SOC_INTEL_CSE_LITE_SKU && !SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD
select SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE
help
Select this config if Platform Service Record(PSR) is supported by the platform. This
@@ -298,7 +298,7 @@
config SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY
def_bool n
- depends on SOC_INTEL_CSE_LITE_SKU
+ depends on SOC_INTEL_CSE_LITE_SKU && !SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD
help
Mainboard user to select this Kconfig in order to capture pre-cpu
reset boot performance telemetry data.
@@ -320,13 +320,14 @@
config SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE
bool
default !SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE
- depends on SOC_INTEL_CSE_LITE_SKU && !SOC_INTEL_CSE_LITE_COMPRESS_ME_RW
+ depends on SOC_INTEL_CSE_LITE_SKU && !SOC_INTEL_CSE_LITE_COMPRESS_ME_RW && !SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD
help
Use default flow of CSE FW Update in romstage when uncompressed ME_RW blobs are used.
config SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE
bool
default n
+ depends on !SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD
help
Use this option if CSE RW update needs to be triggered during RAMSTAGE.
--
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Elyes Haouas has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/83322?usp=email )
Change subject: src/mainboard/intel/frost_creek: add a new CRB Frost Creek for SNR
......................................................................
Patch Set 3:
(1 comment)
File src/mainboard/intel/frost_creek/acpi/platform.asl:
https://review.coreboot.org/c/coreboot/+/83322/comment/8d9e150d_d74b8f3e?us… :
PS3, Line 22: Store (Arg0, SMIF) // SMI Function
: Store (0,
Please use ASL2 syntax
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Change subject: src/mainboard/intel/frost_creek: add a new CRB Frost Creek for SNR
......................................................................
src/mainboard/intel/frost_creek: add a new CRB Frost Creek for SNR
Change-Id: If3b387a6a4a567415aef21e520056c23b8cfa013
Signed-off-by: Yuchi Chen <yuchi.chen(a)intel.com>
---
A src/mainboard/intel/frost_creek/COPYING-NOTICE
A src/mainboard/intel/frost_creek/Kconfig
A src/mainboard/intel/frost_creek/Kconfig.name
A src/mainboard/intel/frost_creek/Makefile.mk
A src/mainboard/intel/frost_creek/acpi/mainboard.asl
A src/mainboard/intel/frost_creek/acpi/platform.asl
A src/mainboard/intel/frost_creek/acpi_tables.c
A src/mainboard/intel/frost_creek/board.fmd
A src/mainboard/intel/frost_creek/board_id.c
A src/mainboard/intel/frost_creek/board_id.h
A src/mainboard/intel/frost_creek/board_info.txt
A src/mainboard/intel/frost_creek/devicetree.cb
A src/mainboard/intel/frost_creek/dsdt.asl
A src/mainboard/intel/frost_creek/gpio.inc
A src/mainboard/intel/frost_creek/ramstage.c
A src/mainboard/intel/frost_creek/ramstage.h
A src/mainboard/intel/frost_creek/romstage.c
A src/mainboard/intel/frost_creek/romstage.h
18 files changed, 676 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/83322/3
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Change subject: src/soc/intel/snowridge: add support for Intel Atom Snow Ridge SoC
......................................................................
src/soc/intel/snowridge: add support for Intel Atom Snow Ridge SoC
Change-Id: I32ad836dfaaff0d1816eac41e5a7d19ece11080f
Signed-off-by: Yuchi Chen <yuchi.chen(a)intel.com>
---
A src/soc/intel/snowridge/COPYING-NOTICE
A src/soc/intel/snowridge/Kconfig
A src/soc/intel/snowridge/Makefile.mk
A src/soc/intel/snowridge/acpi.c
A src/soc/intel/snowridge/acpi/hostbridges.asl
A src/soc/intel/snowridge/acpi/ith.asl
A src/soc/intel/snowridge/acpi/lpc.asl
A src/soc/intel/snowridge/acpi/pch_irqs.asl
A src/soc/intel/snowridge/acpi/pci_irqs.asl
A src/soc/intel/snowridge/acpi/pcie.asl
A src/soc/intel/snowridge/acpi/pcie_port.asl
A src/soc/intel/snowridge/acpi/pmc.asl
A src/soc/intel/snowridge/acpi/sata0.asl
A src/soc/intel/snowridge/acpi/sata2.asl
A src/soc/intel/snowridge/acpi/sleepstates.asl
A src/soc/intel/snowridge/acpi/smbus.asl
A src/soc/intel/snowridge/acpi/southcluster.asl
A src/soc/intel/snowridge/acpi/uncore.asl
A src/soc/intel/snowridge/bootblock/bootblock.c
A src/soc/intel/snowridge/bootblock/bootblock.h
A src/soc/intel/snowridge/bootblock/early_uart_init.c
A src/soc/intel/snowridge/chip.c
A src/soc/intel/snowridge/chip.h
A src/soc/intel/snowridge/common/fsp_hob.c
A src/soc/intel/snowridge/common/fsp_hob.h
A src/soc/intel/snowridge/common/gpio.c
A src/soc/intel/snowridge/common/hob_display.c
A src/soc/intel/snowridge/common/kti_cache.c
A src/soc/intel/snowridge/common/kti_cache.h
A src/soc/intel/snowridge/common/pmclib.c
A src/soc/intel/snowridge/common/reset.c
A src/soc/intel/snowridge/common/spi.c
A src/soc/intel/snowridge/common/uart8250mem.c
A src/soc/intel/snowridge/common/uart8250mem.h
A src/soc/intel/snowridge/common/upd_display.c
A src/soc/intel/snowridge/cpu.c
A src/soc/intel/snowridge/finalize.c
A src/soc/intel/snowridge/heci.c
A src/soc/intel/snowridge/hob_iiouds.h
A src/soc/intel/snowridge/hqm.c
A src/soc/intel/snowridge/include/soc/acpi.h
A src/soc/intel/snowridge/include/soc/cpu.h
A src/soc/intel/snowridge/include/soc/gpio.h
A src/soc/intel/snowridge/include/soc/gpio_defs.h
A src/soc/intel/snowridge/include/soc/gpio_snr.h
A src/soc/intel/snowridge/include/soc/gpmr.h
A src/soc/intel/snowridge/include/soc/iomap.h
A src/soc/intel/snowridge/include/soc/irq.h
A src/soc/intel/snowridge/include/soc/itss.h
A src/soc/intel/snowridge/include/soc/lpc.h
A src/soc/intel/snowridge/include/soc/msr.h
A src/soc/intel/snowridge/include/soc/nvs.h
A src/soc/intel/snowridge/include/soc/p2sb.h
A src/soc/intel/snowridge/include/soc/pci_devs.h
A src/soc/intel/snowridge/include/soc/pci_ids.h
A src/soc/intel/snowridge/include/soc/pcr_ids.h
A src/soc/intel/snowridge/include/soc/pm.h
A src/soc/intel/snowridge/include/soc/pmc.h
A src/soc/intel/snowridge/include/soc/sata.h
A src/soc/intel/snowridge/include/soc/smbus.h
A src/soc/intel/snowridge/include/soc/soc_chip.h
A src/soc/intel/snowridge/include/soc/systemagent.h
A src/soc/intel/snowridge/lockdown.c
A src/soc/intel/snowridge/lpc.c
A src/soc/intel/snowridge/memmap.c
A src/soc/intel/snowridge/nis.c
A src/soc/intel/snowridge/qat.c
A src/soc/intel/snowridge/ramstage.h
A src/soc/intel/snowridge/romstage/gpio_snr.c
A src/soc/intel/snowridge/romstage/romstage.c
A src/soc/intel/snowridge/sata.c
A src/soc/intel/snowridge/smihandler.c
A src/soc/intel/snowridge/sriov.c
A src/soc/intel/snowridge/systemagent.c
74 files changed, 5,897 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/83321/3
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Change subject: mb/google/lotso: Add hid report address for gt7986u
......................................................................
Patch Set 4: Code-Review+2
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