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Change subject: device/pci_ids: Add new Intel PTL device IDs for Fast-SPI and GSPIx
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Patch Set 1: Code-Review+1
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Change subject: device/pci_ids: Add new Intel PTL device IDs for eSPI/LPC
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Patch Set 1: Code-Review+1
(1 comment)
File src/soc/intel/common/block/lpc/lpc.c:
https://review.coreboot.org/c/coreboot/+/83506/comment/ef041abf_b118bd01?us… :
PS1, Line 143: static const unsigned short pci_device_ids[] = {
For another patch: bind the LPC/eSPI ops through the chipset devicetree instead of having such a long list of IDs. See CB:79167 for an example. Yes, this can also be done for other devices.
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Change subject: device/pci_ids: Add new Intel PTL device IDs for ISH
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Patch Set 1: Code-Review+1
(1 comment)
File src/include/device/pci_ids.h:
https://review.coreboot.org/c/coreboot/+/83505/comment/949f9598_ef3549b2?us… :
PS1, Line 2189: PCI_DID_INTEL_PTL_U_H_ISHB
If I understand this correctly, there's two versions of PTL-H with different ISHB device IDs? I guess details are NDA-only, though.
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Change subject: soc/intel/common/intelblocks/gpio.h: Allow specifying the pad ownership
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soc/intel/common/intelblocks/gpio.h: Allow specifying the pad ownership
Add pad_own_reg_0 to `struct pad_community`.
Change-Id: I30a934fd00a7a42cb156341da1954e4e4b1231d8
Signed-off-by: Yuchi Chen <yuchi.chen(a)intel.com>
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M src/soc/intel/common/block/include/intelblocks/gpio.h
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/83315/7
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Change subject: soc/intel/common/block/gpmr: Allow soc to have specific gpmr definition
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soc/intel/common/block/gpmr: Allow soc to have specific gpmr definition
This patch add a new Kconfig HAVE_SPECIFIC_GPMR and use it to include
soc/gpmr.h if necessary.
Change-Id: I94797a72af75fc96ab2cacb1d46b581605a15387
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---
M src/soc/intel/common/block/gpmr/Kconfig
M src/soc/intel/common/block/include/intelblocks/gpmr.h
2 files changed, 12 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/83317/7
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