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Change subject: lotso: Update board type to BOARD_TYPE_ULT_ULX
......................................................................
Patch Set 2: Code-Review+1
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Change subject: lotso: Add hid report address for gt7986u
......................................................................
Patch Set 3:
(1 comment)
File src/drivers/spi/acpi/acpi.c:
https://review.coreboot.org/c/coreboot/+/83139/comment/769a80d9_4432f398?us… :
PS2, Line 151: if (config->hid_report_addr)
: acpi_dp_add_integer(dsd, "goodix,hid-report-addr",
: config->hid_report_addr);
> Since you are adding a vendor specific property, add it as follows: […]
Done
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Hello Jian Tong, Karthik Ramasubramanian, Shelley Chen, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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The following approvals got outdated and were removed:
Code-Review+1 by Jian Tong, Verified+1 by build bot (Jenkins)
Change subject: lotso: Add hid report address for gt7986u
......................................................................
lotso: Add hid report address for gt7986u
Add hid report address for gt7986u
BUG=b:342932183
BRANCH=None
TEST=Verify touchscreen work normal
Change-Id: I8b18e0a2925e6fd36e3a470bde9910661b7558b8
Signed-off-by: Kun Liu <liukun11(a)huaqin.corp-partner.google.com>
---
M src/drivers/spi/acpi/acpi.c
M src/drivers/spi/acpi/chip.h
M src/mainboard/google/brox/variants/lotso/overridetree.cb
3 files changed, 13 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/83139/3
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Kun Liu has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/83191?usp=email )
Change subject: lotso: Update board type to BOARD_TYPE_ULT_ULX
......................................................................
lotso: Update board type to BOARD_TYPE_ULT_ULX
Update board type to BOARD_TYPE_ULT_ULX
BUG=b:348147663
BRANCH=none
TEST=Built and compare the results of
command 'dmidecode --type 17 | grep Speed'
[Before]
Speed: 8400 MT/s
Configured Memory Speed: 6400 MT/s
[After]
Speed: 8400 MT/s
Configured Memory Speed: 5200 MT/s
Change-Id: I049d7c19424f41e83480f4b80bafd6ef8b9e30f6
Signed-off-by: Kun Liu <liukun11(a)huaqin.corp-partner.google.com>
---
M src/mainboard/google/brox/variants/lotso/memory.c
1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/83191/2
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Change subject: mb/google/trulo/var/orisa: Fill in gpio.h
......................................................................
Patch Set 8:
(1 comment)
Patchset:
PS7:
> Please also add device tree change in comment or separate another CL
Done
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Change subject: mb/google/trulo/var/orisa: Fill in gpio.h
......................................................................
mb/google/trulo/var/orisa: Fill in gpio.h
Fill ec pins in gpio.h and configure GPE0 DW2 in overridetree according to schematic_20240614.
BUG=b:333486830
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: I9de842a8a66632314d5fdf6444005d34338a1100
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---
M src/mainboard/google/brya/variants/orisa/include/variant/gpio.h
M src/mainboard/google/brya/variants/orisa/overridetree.cb
2 files changed, 13 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/83155/8
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Change subject: skl mainboards/dt: Move serirq setting into LPC device scope
......................................................................
Patch Set 2: Code-Review+1
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Change subject: skl mainboards/dt: Move SATA related settings into SATA device scope
......................................................................
Patch Set 2: Code-Review+1
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Change subject: skl mainboards/dt: Drop SataPortsEnable[x] setting if disabled
......................................................................
Patch Set 1: Code-Review+1
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