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Change subject: arch/arm64: Support calling a trusted monitor
......................................................................
Patch Set 15:
(2 comments)
File src/arch/arm64/smc.c:
https://review.coreboot.org/c/coreboot/+/78284/comment/9d83e760_651a11c4 :
PS15, Line 6: extern
The extern keyword is meaningless for functions.
https://review.coreboot.org/c/coreboot/+/78284/comment/57112df0_7ea8cda9 :
PS15, Line 9: inline
I don't think inline works without static: You want it to be exported at the compilation module level which makes inlining impossible (LTO might inline it after all).
Do you see a difference at binary level?
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Change subject: drivers/intel/fsp2_0: Add dedicated caller function for ap procedure calls
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Patch Set 11: Code-Review+2
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Change subject: libpayload: Add x86_64 (64-bit) support
......................................................................
Patch Set 20:
(9 comments)
Patchset:
PS1:
> > Why duplicate the x86 code into x64? Why not capture the differences with preprocessor as done in coreboot?
>
> I just submit something for your view and i felt we are back/forth talking about we need to implement ABI first.
>
> I really wish to submit the clean code but i pull something from my downstream repo that I'm working to enable this support.
Alright. No worries. I suppose review can happen later.
File payloads/libpayload/Kconfig:
https://review.coreboot.org/c/coreboot/+/81968/comment/97207d79_c2010fad :
PS20, Line 168: default 0x80100000 if ARCH_X86_64
why use a different address than 32bit code?
File payloads/libpayload/arch/x86/exec_64.S:
https://review.coreboot.org/c/coreboot/+/81968/comment/33499bdd_bad3ae79 :
PS20, Line 41: i386_do_exec
I would expect 32bit code with this name.
File payloads/libpayload/arch/x86/gdb.c:
https://review.coreboot.org/c/coreboot/+/81968/comment/d0eea913_24a94054 :
PS20, Line 59: esp
should be larger size if you do movq. Maybe use uintptr_t for it?
File payloads/libpayload/arch/x86/head_64.S:
https://review.coreboot.org/c/coreboot/+/81968/comment/654eebf6_0ba0443f :
PS20, Line 81: /* Enable special x86 functions if present. */
: push %rdi
: push %rsi
: push %rdx
: push %rcx
: push %r8
: push %r9
Why save/restore registers that you don't use but not the ones you actually use like rax, rbx, rcx, rdx?
File payloads/libpayload/arch/x86/libpayload_64.ldscript:
https://review.coreboot.org/c/coreboot/+/81968/comment/718d4c06_7cdcee5f :
PS20, Line 29: OUTPUT_FORMAT(elf64-x86-64)
: OUTPUT_ARCH(x86_64)
Any reason for a separate linker script with the same content? You can add multiple OUTPUT_FORMAT and ARCH in here afaik?
File payloads/libpayload/arch/x86/multiboot.c:
https://review.coreboot.org/c/coreboot/+/81968/comment/9ec1549f_6d1a9277 :
PS20, Line 1: *
: *
: * Copyright (C) 2008 Advanced Micro Devices, Inc.
: *
Multiboot2 predates long mode. I don't think this compilation unit should be added with long mode.
https://review.coreboot.org/c/coreboot/+/81968/comment/c8ac50ec_f39a5e80 :
PS20, Line 117: if (loader_rdi != MULTIBOOT_MAGIC)
Looking at how you intend to boot with will simply never be the case as RDI contains a pointer to the coreboot tables.
File payloads/libpayload/arch/x86/string.c:
https://review.coreboot.org/c/coreboot/+/81968/comment/5ff6d8c7_af89f93a :
PS20, Line 84: asm volatile(
: "rep ; movsl\n\t"
: #if CONFIG(LP_ARCH_X86_64)
: "movq %4,%%rcx\n\t"
: #else
: "movl %4,%%ecx\n\t"
: #endif
: "rep ; movsb\n\t"
: : "=&c" (d0), "=&D" (d1), "=&S" (d2)
: : "0" (n >> 2), "g" (n & 3), "1" (dest), "2" (src)
: : "memory"
: );
Increment by 8 bytes instead of 4.
#if CONFIG(LP_ARCH_X86_64)
asm volatile(
"rep ; movsq\n\t"
"mov %4,%%rcx\n\t"
"rep ; movsb\n\t"
: "=&c" (d0), "=&D" (d1), "=&S" (d2)
: "0" (n >> 3), "g" (n & 7), "1" (dest), "2" (src)
: "memory"
);
#else
asm volatile(
"rep ; movsl\n\t"
"movl %4,%%ecx\n\t"
"rep ; movsb\n\t"
: "=&c" (d0), "=&D" (d1), "=&S" (d2)
: "0" (n >> 2), "g" (n & 3), "1" (dest), "2" (src)
: "memory"
);
#endif
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Change subject: arch/arm64: Add EL1/EL2/EL3 support for arm64
......................................................................
Patch Set 18:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/74798/comment/bbfd03d4_34d3e020 :
PS5, Line 11: one boots into TF-A first and drops into EL2 for coreboot afterwards.
> > ARM did what they have promissed: https://developer.arm.com/documentation/den0044/latest. […]
We have agreed that if ARM introduces the requested changes into their spec we are willing to merge this patch. Since ARM did it's up to us now.
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Change subject: mb/google/brya/var/bujia: Add VBT data file
......................................................................
Patch Set 7: Code-Review+2
(1 comment)
Patchset:
PS7:
please rebase
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Change subject: mb/google/brya/var/bujia: Add VBT data file
......................................................................
Patch Set 7:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/81553/comment/b58cccb9_34e15e90 :
PS6, Line 7: files
> file
Done
https://review.coreboot.org/c/coreboot/+/81553/comment/066cd5f0_5f6b79fe :
PS6, Line 13: "integrated DisplayPort with HDMI/DVI compatible" -> "Integrated HDMI/DVI".
: turn the AUX off.
> Format it as a list.
Done
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I'd like you to reexamine a change. Please visit
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Change subject: mb/google/brya/var/bujia: Add VBT data file
......................................................................
mb/google/brya/var/bujia: Add VBT data file
Add data.vbt files for bujia supported by brask recovery images.
Select INTEL_GMA_HAVE_VBT for bujia which currently have a VBT file.
changes:
1. "integrated DisplayPort with HDMI/DVI compatible"
-> "Integrated HDMI/DVI".
2. turn the AUX off.
BUG=b:327549688
TEST=build/boot various brya variants
Change-Id: Id56461708250eaedd288ddbf788d686153df0b96
Signed-off-by: Shon Wang <shon.wang(a)quanta.corp-partner.google.com>
---
M src/mainboard/google/brya/Kconfig
A src/mainboard/google/brya/variants/bujia/data.vbt
2 files changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/81553/7
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Hello Angel Pons, Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, TangYiwei, Tim Chu, build bot (Jenkins),
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Change subject: soc/intel/xeon_sp: Add Granite Rapids initial codes
......................................................................
soc/intel/xeon_sp: Add Granite Rapids initial codes
coreboot GNR (Granite Rapids) is a FSP 2.4 based, no-PCH, single
IO-APIC Xeon-SP platform. The same set of codes is also used
for SRF (Sierra Forest) SoC.
This patch initially sets the code set up.
1. All register definitions are forked from SPR (Sapphire Rapids)
and EBG (Emmisburg PCH)'s codes are reused.
2. src/soc/intel/xeon_sp/chip_gen6.c is newly added as chip
common codes for 6th Gen Xeon-SP SoC (Granite Rapids) and later.
TEST=Build and boot on intel/archercity CRB
Change-Id: I3084e1b5abf25d8d9504bebeaed2a15b916ed56b
Signed-off-by: Shuo Liu <shuo.liu(a)intel.com>
Signed-off-by: Gang Chen <gang.c.chen(a)intel.com>
Signed-off-by: Jincheng Li <jincheng.li(a)intel.com>
---
M MAINTAINERS
M src/soc/intel/xeon_sp/Makefile.mk
A src/soc/intel/xeon_sp/chip_gen6.c
A src/soc/intel/xeon_sp/gnr/Kconfig
A src/soc/intel/xeon_sp/gnr/Makefile.inc
A src/soc/intel/xeon_sp/gnr/acpi/gpe.asl
A src/soc/intel/xeon_sp/gnr/chip.c
A src/soc/intel/xeon_sp/gnr/chip.h
A src/soc/intel/xeon_sp/gnr/chipset.cb
A src/soc/intel/xeon_sp/gnr/cpu.c
A src/soc/intel/xeon_sp/gnr/include/soc/cpu.h
A src/soc/intel/xeon_sp/gnr/include/soc/pci_devs.h
A src/soc/intel/xeon_sp/gnr/include/soc/soc_msr.h
A src/soc/intel/xeon_sp/gnr/include/soc/soc_util.h
A src/soc/intel/xeon_sp/gnr/include/soc/vpd.h
A src/soc/intel/xeon_sp/gnr/ramstage.c
A src/soc/intel/xeon_sp/gnr/romstage.c
A src/soc/intel/xeon_sp/gnr/soc_acpi.c
A src/soc/intel/xeon_sp/gnr/soc_util.c
M src/soc/intel/xeon_sp/include/soc/acpi.h
M src/soc/intel/xeon_sp/include/soc/fsp_upd.h
M src/soc/intel/xeon_sp/lockdown.c
M src/soc/intel/xeon_sp/spr/soc_acpi.c
23 files changed, 1,173 insertions(+), 20 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/81316/50
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Attention is currently required from: Federico Amedeo Izzo.
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/82010?usp=email
to look at the new patch set (#4).
Change subject: mb/aoostar: Add AOOSTAR R1 (WTR_R1)
......................................................................
mb/aoostar: Add AOOSTAR R1 (WTR_R1)
AOOSTAR R1 is a Chinese NAS based on Intel N100 (Alder Lake N), with
two 3.5" HDD slots, an M.2 NVMe 2280 SSD slot and a single DDR4 SODIMM
slot. It also comes with 2x 2.5Gb Intel NICs, Intel AX200 WiFi + BT
and USB-C Alt-DP Power Delivery.
Working:
- Automatic FAN control (IT8613E SuperIO)
- M.2 NVME slot
- 2x SATA ports
- 2.0 USB ports
- USB-C port with Alt-DP and PD
- HDMI / DisplayPort ports
- 2x 2.5Gb NICs
- WiFi + BT
- ASPM (Unavailable on stock)
- Linux/Windows UEFI booting with EDK2
Broken:
- Power button (OFF->ON broken, ON->OFF works)
- USB 3.0 ports
Untested:
- Internal audio
- MicroSD card reader
- S3
My motivation for doing this port is enabling ASPM, as it makes a
great difference on idle power consumption (from 8.4W to 5W measured
from the wall).
The last remaining annoyance of this port is the power button not
working. I spent a few hours double checking the SuperIO registers but
then I gave up. A workaround for this is to use the "ON after power
loss" feature and reconnect the power cord to turn on the board.
It's not a big problem for a NAS that will stay ON 24/7.
VDT extracted from vendor BIOS.
Compiled with IFD descriptor, ME blob and vgabios blob (ID 8086,0406)
extracted from vendor BIOS.
The board can be flashed externally using a 1.8V adapter, I used a
CH341a modded for 3.3V I/O. Internal flashing could work too as SPI
flash is not read/write protected, but I haven't tried.
Change-Id: I9414eb742b6b90459e010b038c1994537e9801a5
Signed-off-by: Federico Amedeo Izzo <federico(a)izzo.pro>
---
A src/mainboard/aoostar/Kconfig
A src/mainboard/aoostar/Kconfig.name
A src/mainboard/aoostar/wtr_r1/Kconfig
A src/mainboard/aoostar/wtr_r1/Kconfig.name
A src/mainboard/aoostar/wtr_r1/Makefile.mk
A src/mainboard/aoostar/wtr_r1/board_info.txt
A src/mainboard/aoostar/wtr_r1/bootblock.c
A src/mainboard/aoostar/wtr_r1/data.vbt
A src/mainboard/aoostar/wtr_r1/devicetree.cb
A src/mainboard/aoostar/wtr_r1/dsdt.asl
A src/mainboard/aoostar/wtr_r1/gpio.h
A src/mainboard/aoostar/wtr_r1/romstage_fsp_params.c
12 files changed, 744 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/82010/4
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Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I9414eb742b6b90459e010b038c1994537e9801a5
Gerrit-Change-Number: 82010
Gerrit-PatchSet: 4
Gerrit-Owner: Federico Amedeo Izzo <federico(a)izzo.pro>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>
Gerrit-Attention: Federico Amedeo Izzo <federico(a)izzo.pro>
Gerrit-MessageType: newpatchset