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Change subject: mb/intel/avenuecity_crb: Add GNR/SRF-AP 2S server board Avenue City
......................................................................
mb/intel/avenuecity_crb: Add GNR/SRF-AP 2S server board Avenue City
Avenue City CRB is the 2 socket reference board for 6th Gen Xeon-SP
AP SoCs (Granite Rapids AP and Sierra Forest AP).
This patch initially sets the code set up as a compilation target
with GNR N-1 FSP, and with basic feature supports (Integrated IO
Controller (IIO) configuration, BMC, UART, HPET).
TEST=Build on intel/avenuecity CRB
Change-Id: I64fdd5388aadf7732f6d3daa600c1455d3672a46
Signed-off-by: Gang Chen <gang.c.chen(a)intel.com>
Co-authored-by: Shuo Liu <shuo.liu(a)intel.com>
Co-authored-by: Jincheng Li <jincheng.li(a)intel.com>
---
A configs/builder/config.intel.crb.avc
A src/mainboard/intel/avenuecity_crb/Kconfig
A src/mainboard/intel/avenuecity_crb/Kconfig.name
A src/mainboard/intel/avenuecity_crb/Makefile.mk
A src/mainboard/intel/avenuecity_crb/board.fmd
A src/mainboard/intel/avenuecity_crb/board_info.txt
A src/mainboard/intel/avenuecity_crb/bootblock.c
A src/mainboard/intel/avenuecity_crb/config/iio.c
A src/mainboard/intel/avenuecity_crb/devicetree.cb
A src/mainboard/intel/avenuecity_crb/dsdt.asl
A src/mainboard/intel/avenuecity_crb/ramstage.c
A src/mainboard/intel/avenuecity_crb/romstage.c
12 files changed, 269 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/81319/45
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Change subject: soc/intel/xeon_sp/gnr: Add IIO config utils
......................................................................
soc/intel/xeon_sp/gnr: Add IIO config utils
Add IIO configuration utils shared in GNR boards to handle the
complex IIO configuration settings.
TEST=Build and boot on intel/archercity CRB
Change-Id: If7146761db6f73a0c4b0d31b010c0d30a42bf690
Signed-off-by: Gang Chen <gang.c.chen(a)intel.com>
Co-authored-by: Shuo Liu <shuo.liu(a)intel.com>
---
M src/soc/intel/xeon_sp/gnr/Makefile.inc
A src/soc/intel/xeon_sp/gnr/include/soc/iio.h
A src/soc/intel/xeon_sp/gnr/soc_iio.c
3 files changed, 200 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/81318/42
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Change subject: soc/intel/xeon_sp: Add Granite Rapids initial codes
......................................................................
soc/intel/xeon_sp: Add Granite Rapids initial codes
coreboot GNR (Granite Rapids) is a FSP 2.4 based, no-PCH, single
IO-APIC Xeon-SP platform. The same set of codes is also used
for SRF (Sierra Forest) SoC.
This patch initially sets the code set up.
1. All register definitions are forked from SPR (Sapphire Rapids)
and EBG (Emmisburg PCH)'s codes are reused.
2. src/soc/intel/xeon_sp/chip_gen6.c is newly added as chip
common codes for 6th Gen Xeon-SP SoC (Granite Rapids) and later.
TEST=Build and boot on intel/archercity CRB
Change-Id: I3084e1b5abf25d8d9504bebeaed2a15b916ed56b
Signed-off-by: Shuo Liu <shuo.liu(a)intel.com>
Co-authored-by: Gang Chen <gang.c.chen(a)intel.com>
Co-authored-by: Jincheng Li <jincheng.li(a)intel.com>
---
M MAINTAINERS
M src/soc/intel/xeon_sp/Makefile.mk
A src/soc/intel/xeon_sp/chip_gen6.c
A src/soc/intel/xeon_sp/gnr/Kconfig
A src/soc/intel/xeon_sp/gnr/Makefile.inc
A src/soc/intel/xeon_sp/gnr/acpi/gpe.asl
A src/soc/intel/xeon_sp/gnr/chip.c
A src/soc/intel/xeon_sp/gnr/chip.h
A src/soc/intel/xeon_sp/gnr/chipset.cb
A src/soc/intel/xeon_sp/gnr/cpu.c
A src/soc/intel/xeon_sp/gnr/include/soc/cpu.h
A src/soc/intel/xeon_sp/gnr/include/soc/pci_devs.h
A src/soc/intel/xeon_sp/gnr/include/soc/soc_msr.h
A src/soc/intel/xeon_sp/gnr/include/soc/soc_util.h
A src/soc/intel/xeon_sp/gnr/include/soc/vpd.h
A src/soc/intel/xeon_sp/gnr/ramstage.c
A src/soc/intel/xeon_sp/gnr/romstage.c
A src/soc/intel/xeon_sp/gnr/soc_acpi.c
A src/soc/intel/xeon_sp/gnr/soc_util.c
M src/soc/intel/xeon_sp/include/soc/acpi.h
M src/soc/intel/xeon_sp/include/soc/fsp_upd.h
M src/soc/intel/xeon_sp/lockdown.c
M src/soc/intel/xeon_sp/spr/soc_acpi.c
23 files changed, 1,173 insertions(+), 20 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/81316/51
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Michał Kopeć has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80853?usp=email )
Change subject: mb/erying: Add Erying Polestar G613 Pro (TGL-H)
......................................................................
Patch Set 7:
(1 comment)
File src/mainboard/erying/tgl/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/80853/comment/d24fa75e_f9afdb43 :
PS7, Line 144: register "TMPIN1.mode" = "THERMAL_DIODE"
> Sorry, I didn't notice the tmpin […]
I had a similar problem with IT8625E (for which I submitted a CL but never finished it), maybe this could help you: https://review.coreboot.org/c/coreboot/+/63672
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Change subject: gma display_probing: Make new TGL ports available
......................................................................
Patch Set 4: Code-Review+2
(2 comments)
Commit Message:
https://review.coreboot.org/c/libgfxinit/+/81522/comment/4fd05800_5e529291 :
PS1, Line 8:
> Maybe list these new ports, or document the chapter, where they are documented.
`intel-gfx-prm-osrc-tgl-vol-12-display-engine.pdf` mentions these ports.
File common/hw-gfx-gma-display_probing.ads:
https://review.coreboot.org/c/libgfxinit/+/81522/comment/7ccd5d8e_43f09a7f :
PS4, Line 26: USBC1_HDMI, USBC2_HDMI, USBC3_HDMI, USBC4_HDMI, USBC5_HDMI, USBC6_HDMI,
I see DP ports get mapped above, should the same be done for these?
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Change subject: Makefile: Always disable warnings for out-of-order record fields
......................................................................
Patch Set 1: Code-Review+2
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Attention is currently required from: Angel Pons.
Hello Angel Pons,
I'd like you to do a code review.
Please visit
https://review.coreboot.org/c/libhwbase/+/82052?usp=email
to review the following change.
Change subject: Makefile: Always disable warnings for out-of-order record fields
......................................................................
Makefile: Always disable warnings for out-of-order record fields
We added this as a GCC 10 quirk, but of course by now there are many
more versions with this flag. Stable GCC 10.1 was released almost 4
years ago and libhwbase is mostly used with coreboot's toolchain and
newer ones. So we don't have to keep compatibility with older GCC
releases.
Change-Id: I1131ebbdde71cd6223a9ea650512eec601401cc3
Signed-off-by: Nico Huber <nico.h(a)gmx.de>
---
M Makefile
1 file changed, 1 insertion(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/libhwbase refs/changes/52/82052/1
diff --git a/Makefile b/Makefile
index fb4c43c..e8d864e 100644
--- a/Makefile
+++ b/Makefile
@@ -43,8 +43,6 @@
CC = $(CROSS_COMPILE)gcc
GNATBIND = $(CROSS_COMPILE)gnatbind
-GCC_MAJOR = $(shell echo __GNUC__ | $(CC) -E - 2>/dev/null | tail -1)
-
CFLAGS += -Wuninitialized -Wall -Werror
CFLAGS += -pipe -g
CFLAGS += -Wstrict-aliasing -Wshadow
@@ -89,8 +87,7 @@
# .Y Disable information messages for why package spec needs body:
# Those messages are annoying. But don't forget to enable those,
# if you need the information.
-ADAFLAGS += -gnatwa.eeD.HHTU.U.W.Y
-ADAFLAGS += $(if $(filter 10,$(GCC_MAJOR)),-gnatw_R)
+ADAFLAGS += -gnatwa.eeD.HHTU.U.W.Y_R
# Disable style checks for now
ADAFLAGS += -gnatyN
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/82010?usp=email
to look at the new patch set (#5).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: mb/aoostar: Add AOOSTAR R1 (WTR_R1)
......................................................................
mb/aoostar: Add AOOSTAR R1 (WTR_R1)
AOOSTAR R1 is a Chinese NAS based on Intel N100 (Alder Lake N), with
two 3.5" HDD slots, an M.2 NVMe 2280 SSD slot and a single DDR4 SODIMM
slot. It also comes with 2x 2.5Gb Intel NICs, Intel AX200 WiFi + BT
and USB-C Alt-DP Power Delivery.
Working:
- Automatic FAN control (IT8613E SuperIO)
- M.2 NVME slot
- 2x SATA ports
- 2.0 USB ports
- USB-C port with Alt-DP and PD
- HDMI / DisplayPort ports
- 2x 2.5Gb NICs
- WiFi + BT
- ASPM (Unavailable on stock)
- Linux/Windows UEFI booting with EDK2
Broken:
- Power button (OFF->ON broken, ON->OFF works)
- USB 3.0 ports
Untested:
- Internal audio
- MicroSD card reader
- S3
My motivation for doing this port is enabling ASPM, as it makes a
great difference on idle power consumption (from 8.4W to 5W measured
from the wall).
The last remaining annoyance of this port is the power button not
working. I spent a few hours double checking the SuperIO registers but
then I gave up. A workaround for this is to use the "ON after power
loss" feature and reconnect the power cord to turn on the board.
It's not a big problem for a NAS that will stay ON 24/7.
VDT extracted from vendor BIOS.
Compiled with FSP GOP video initialization, using IFD descriptor,
ME blob and vgabios blob (ID 8086,0406) extracted from vendor BIOS.
The board can be flashed externally using a 1.8V adapter, I used a
CH341a modded for 3.3V I/O. Internal flashing could work too as SPI
flash is not read/write protected, but I haven't tried.
Patchset 5: Re-enabled dptf, added default options to Kconfig.
Change-Id: I9414eb742b6b90459e010b038c1994537e9801a5
Signed-off-by: Federico Amedeo Izzo <federico(a)izzo.pro>
---
A src/mainboard/aoostar/Kconfig
A src/mainboard/aoostar/Kconfig.name
A src/mainboard/aoostar/wtr_r1/Kconfig
A src/mainboard/aoostar/wtr_r1/Kconfig.name
A src/mainboard/aoostar/wtr_r1/Makefile.mk
A src/mainboard/aoostar/wtr_r1/board_info.txt
A src/mainboard/aoostar/wtr_r1/bootblock.c
A src/mainboard/aoostar/wtr_r1/data.vbt
A src/mainboard/aoostar/wtr_r1/devicetree.cb
A src/mainboard/aoostar/wtr_r1/dsdt.asl
A src/mainboard/aoostar/wtr_r1/gpio.h
A src/mainboard/aoostar/wtr_r1/romstage_fsp_params.c
12 files changed, 752 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/82010/5
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Change subject: drivers/intel/fsp2_0: Default to 64-bits for FSP 2.4
......................................................................
Patch Set 33: Code-Review+2
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Change subject: arch/arm64: Implement initial set of SMBIOS tables
......................................................................
Patch Set 15:
(3 comments)
File src/arch/arm64/smbios.c:
https://review.coreboot.org/c/coreboot/+/78285/comment/dbd6b423_f3687a63 :
PS15, Line 74: t->core_count = MAX_CPUS_ENABLED(t->core_count2);
: t->thread_count = MAX_CPUS_ENABLED(t->thread_count2);
SMP is now a thing in ARM right? Maybe the SOC should provide this info? Maybe add a TODO comment?
File src/arch/arm64/tables.c:
https://review.coreboot.org/c/coreboot/+/78285/comment/af98ded6_88f0d09b :
PS15, Line 26: high_table_pointer, new_high_table_pointer;
'high' is x86 terminology where 'low' means 0 - 1*MiB. I don't that terminology should be reused on arm64. maybe smbios_begin and smbios_end?
https://review.coreboot.org/c/coreboot/+/78285/comment/b5957899_0e90da04 :
PS15, Line 32: if (!high_table_pointer)
: return;
You want assert or error message.
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