coreboot-gerrit April 2024

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[M] Change in coreboot[main]: drivers/i2c/rt5645: Add RT5645 amp driver
by Jianeng Ceng (Code Review) 23 Apr '24

23 Apr '24

Attention is currently required from: Dolan Liu, Elyes Haouas, Eric Lai, Kapil Porwal, Matt DeVillier, Paul Menzel, Subrata Banik. Jianeng Ceng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81773?usp=email ) Change subject: drivers/i2c/rt5645: Add RT5645 amp driver ...................................................................... Patch Set 25: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/81773/comment/56a7e830_02383368 : PS24, Line 9: In order to be different from rt5663, the driver of RT5645 is : specially declared. > while the wording here is slightly awkward, I don't see enumerating the differences between the two […] Done https://review.coreboot.org/c/coreboot/+/81773/comment/200dca0a_42bd74f3 : PS24, Line 17: > or stated another way, the ACPI device is being created specifically for Linux Done File src/drivers/i2c/rt5645/rt5645.c: https://review.coreboot.org/c/coreboot/+/81773/comment/660e91a0_c684ba82 : PS24, Line 48: acpigen_write_STA(ACPI_STATUS_DEVICE_HIDDEN_ON); > Maybe add a comment here, that it is for Microsoft Windows. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/81773?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I602fcc4dd8576043943f6e20884edc4703350320 Gerrit-Change-Number: 81773 Gerrit-PatchSet: 25 Gerrit-Owner: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Tue, 23 Apr 2024 01:16:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: drivers/i2c/rt5645: Add RT5645 amp driver
by Jianeng Ceng (Code Review) 23 Apr '24

23 Apr '24

Attention is currently required from: Dolan Liu, Elyes Haouas, Eric Lai, Jianeng Ceng, Kapil Porwal, Matt DeVillier, Paul Menzel, Subrata Banik. Hello Dolan Liu, Eric Lai, Kapil Porwal, Matt DeVillier, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81773?usp=email to look at the new patch set (#25). The following approvals got outdated and were removed: Code-Review+1 by Eric Lai, Code-Review+1 by Matt DeVillier, Code-Review+1 by Subrata Banik, Code-Review+2 by Kapil Porwal, Verified+1 by build bot (Jenkins) Change subject: drivers/i2c/rt5645: Add RT5645 amp driver ...................................................................... drivers/i2c/rt5645: Add RT5645 amp driver RT5663 is very old and it was used the hard code like RT53 or 10EC5663, which is the different series from RT5645/5650, it may caused some ambiguity. Because I2C generic driver dose not support dsd gpio setting, we declared the new rt5645 series driver for expansion. Add RT5645 AMP support. The kernel driver of 5650 is written in rt5645.c. Add acpi name cbj-sleeve-gpios for power gate GPIO. ALC5650 DataSheet Rev 0.93 Realtek upstream link: https://lore.kernel.org/all/20240404035747.118064-1-derek.fang@realtek.com/ Hide the device because of Microsoft Windows. BUG=None TEST=verified in anraggar and probe device rt5650 succeed ``` \_SB.PCI0.I2C3.RT58: Realtek RT5650 ``` Change-Id: I602fcc4dd8576043943f6e20884edc4703350320 Signed-off-by: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> --- A src/drivers/i2c/rt5645/Kconfig A src/drivers/i2c/rt5645/Makefile.mk A src/drivers/i2c/rt5645/chip.h A src/drivers/i2c/rt5645/rt5645.c 4 files changed, 144 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/81773/25 -- To view, visit https://review.coreboot.org/c/coreboot/+/81773?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I602fcc4dd8576043943f6e20884edc4703350320 Gerrit-Change-Number: 81773 Gerrit-PatchSet: 25 Gerrit-Owner: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: vendorcode/ramoops: Move RAMOOPS region creation to chip init stage
by Anil Kumar K (Code Review) 23 Apr '24

23 Apr '24

Anil Kumar K has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82042?usp=email ) Change subject: vendorcode/ramoops: Move RAMOOPS region creation to chip init stage ...................................................................... vendorcode/ramoops: Move RAMOOPS region creation to chip init stage BUG=b:332910298 TEST=build and boot coreboot image on google/rex HW. Check RAMOOPS CBMEM region creation using cbmem -l command Signed-off-by: Anil Kumar <anil.kumar.k(a)intel.com> Change-Id: Ibae06362cd80eacb16f6cf0eed8c9aa1fbfb2535 --- M src/vendorcode/google/chromeos/ramoops.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/82042/1 diff --git a/src/vendorcode/google/chromeos/ramoops.c b/src/vendorcode/google/chromeos/ramoops.c index 1e3d7f0..88081db 100644 --- a/src/vendorcode/google/chromeos/ramoops.c +++ b/src/vendorcode/google/chromeos/ramoops.c @@ -27,7 +27,7 @@ chromeos_set_ramoops(ram_oops, size); } -BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, ramoops_alloc, NULL); +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_ENTRY, ramoops_alloc, NULL); void lb_ramoops(struct lb_header *header) { -- To view, visit https://review.coreboot.org/c/coreboot/+/82042?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibae06362cd80eacb16f6cf0eed8c9aa1fbfb2535 Gerrit-Change-Number: 82042 Gerrit-PatchSet: 1 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: arch/x86: Enable long mode entry into payload for x86_64 support
by Julius Werner (Code Review) 23 Apr '24

23 Apr '24

Attention is currently required from: Arthur Heymans, Jérémy Compostella, Kapil Porwal, Nico Huber, Patrick Rudolph, Subrata Banik. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81960?usp=email ) Change subject: arch/x86: Enable long mode entry into payload for x86_64 support ...................................................................... Patch Set 14: (2 comments) Patchset: PS14: Sorry for being late to this discussion. So is the decision here now that there's gonna be two entry points, or just a single one? Because using another payload segment type sounds like you want a whole second entry point, but your code is currently not doing that yet (it looks like it's just using the segment type as a boolean flag). Personally, I don't think the two entry points are really worth it. I'd posit that while compatibility of newer coreboot versions to older payloads is nice and something we have preserved for a long time, compatibility of older coreboot with newer payloads gets broken regularly anyway and not something people really care about. Basically every time we add a new coreboot table entry (which happens a lot), that's usually to communicate something to the payload that it requires (and it won't work right and often hang without it), and I don't recall anybody ever complaining about that. In practice I think that while payloads may be binaries that get reused after a coreboot update, the people who do build their own payload also tend to build their own coreboot anyway (and keep their payload repo synced to whatever coreboot branch they're planning to use it with, not ToT). If we're okay with only one entry point and all we need is a flag that says whether a payload is 32 or 64 bit, I don't think payload segments are a great way to model that. They're designed to always be associated with a memory area and not really efficient to store other stuff. Besides, the code currently in this patch looks like it expects the PAYLOAD_SEGMENT_X86_LONG_MODE_ENTRY beyond the PAYLOAD_SEGMENT_ENTRY(?), which is not correct and not safe because PAYLOAD_SEGMENT_ENTRY is defined as the segment that ends the segment list. Reading beyond it means you'd read beyond the end of the list on older payloads. I think the best way to model this would just be with a different CBFS file type (e.g. 0x22 CBFS_TYPE_SELF64). That also means the information will automatically be available in `arch_prog_run()` and you don't need any extra effort to extract it. File src/arch/x86/boot.c: https://review.coreboot.org/c/coreboot/+/81960/comment/e0d3dc98_ea30b305 : PS14, Line 32: void *mapping = cbfs_type_map(prog_name(&payload), NULL, &payload.cbfs_type); Please don't find and parse the entire payload again in this code. Instead, modify selfboot.c to find the new segment type and expose the info somehow (e.g. if we're going to have two different entry points then you'd have to add an `entry64` member to `struct prog`... otherwise, just adding a bool for this should be fine. Moving this to a CBFS type would make things easier because that's already stored in `struct prog` right now. -- To view, visit https://review.coreboot.org/c/coreboot/+/81960?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic5e6f0af11c05e8b075b8c20880c012747a1df9b Gerrit-Change-Number: 81960 Gerrit-PatchSet: 14 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: David Hendricks <david.hendricks(a)gmail.com> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Mon, 22 Apr 2024 23:55:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: Makefile.mk: Associate reproducible build to commit ID
by Felix Held (Code Review) 23 Apr '24

23 Apr '24

Attention is currently required from: Christian Walter, Elyes Haouas, Felix Singer, Martin L Roth, Martin Roth, Name of user not set #1005382, Naveen Iyer, Paul Menzel. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82006?usp=email ) Change subject: Makefile.mk: Associate reproducible build to commit ID ...................................................................... Patch Set 7: (1 comment) Patchset: PS7: > The regular build should be reproducible. If it isn't, that's a bug. […] hmm, might be that i misremembered things or things changed in the last few years, but if the regular build already is reproducible, this might not be needed. back in the days, the regular build wasn't reproducible and i assumed that the date in the binary is the build date, but if it's the commit date nowadays, the regular build might already be reproducible. so it looks like i gave wrong advice based on what i thought was the case here :/ -- To view, visit https://review.coreboot.org/c/coreboot/+/82006?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I97b0c4ea654df23844f31a3398b6f0d05dfec1ab Gerrit-Change-Number: 82006 Gerrit-PatchSet: 7 Gerrit-Owner: Naveen Iyer Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Naveen Iyer Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: Name of user not set #1005382 Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Naveen Iyer Gerrit-Attention: Name of user not set #1005382 Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Mon, 22 Apr 2024 23:22:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Name of user not set #1005382 Comment-In-Reply-To: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: Makefile.mk: Associate reproducible build to commit ID
by Naveen Iyer (Code Review) 23 Apr '24

23 Apr '24

Attention is currently required from: Christian Walter, Elyes Haouas, Felix Held, Felix Singer, Martin L Roth, Name of user not set #1005382, Paul Menzel. Naveen Iyer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82006?usp=email ) Change subject: Makefile.mk: Associate reproducible build to commit ID ...................................................................... Patch Set 7: (1 comment) File util/genbuild_h/genbuild_h.sh: https://review.coreboot.org/c/coreboot/+/82006/comment/0cf45692_25a3e49b : PS7, Line 37: H > does %H vs %h make any difference? would probably be good to use the same as in the already existing […] %H (capital H) gives the complete hash. Now, is the complete hash really necessary? I thought of hash collisions in the future. But that might be too far fetched. I can stick to %h (small H) for now. -- To view, visit https://review.coreboot.org/c/coreboot/+/82006?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I97b0c4ea654df23844f31a3398b6f0d05dfec1ab Gerrit-Change-Number: 82006 Gerrit-PatchSet: 7 Gerrit-Owner: Naveen Iyer Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Naveen Iyer Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: Name of user not set #1005382 Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Name of user not set #1005382 Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Mon, 22 Apr 2024 22:55:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[L] Change in coreboot[main]: [WIP] OptiPlex 3050 port
by Máté Kukri (Code Review) 22 Apr '24

22 Apr '24

Máté Kukri has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82053?usp=email ) Change subject: [WIP] OptiPlex 3050 port ...................................................................... [WIP] OptiPlex 3050 port - Boots Linux - SMBUS SPD reads fail, hard-coded SPD for now - Has BootGuard by default - Requires yet to be released magic ME exploit generator Change-Id: I8d443e39ee684a4eaa19c835a945cfe569c051e2 --- A src/mainboard/dell/optiplex_3050/Kconfig A src/mainboard/dell/optiplex_3050/Kconfig.name A src/mainboard/dell/optiplex_3050/Makefile.mk A src/mainboard/dell/optiplex_3050/acpi/dptf.asl A src/mainboard/dell/optiplex_3050/acpi/ec.asl A src/mainboard/dell/optiplex_3050/acpi/mainboard.asl A src/mainboard/dell/optiplex_3050/acpi/superio.asl A src/mainboard/dell/optiplex_3050/board_info.txt A src/mainboard/dell/optiplex_3050/bootblock.c A src/mainboard/dell/optiplex_3050/cmos.default A src/mainboard/dell/optiplex_3050/cmos.layout A src/mainboard/dell/optiplex_3050/devicetree.cb A src/mainboard/dell/optiplex_3050/dsdt.asl A src/mainboard/dell/optiplex_3050/gma-mainboard.ads A src/mainboard/dell/optiplex_3050/include/gpio.h A src/mainboard/dell/optiplex_3050/mainboard.c A src/mainboard/dell/optiplex_3050/ramstage.c A src/mainboard/dell/optiplex_3050/romstage.c A src/mainboard/dell/optiplex_3050/spd_50.bin A src/mainboard/dell/optiplex_3050/spd_52.bin 20 files changed, 704 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/82053/1 diff --git a/src/mainboard/dell/optiplex_3050/Kconfig b/src/mainboard/dell/optiplex_3050/Kconfig new file mode 100644 index 0000000..de1defa --- /dev/null +++ b/src/mainboard/dell/optiplex_3050/Kconfig @@ -0,0 +1,36 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if BOARD_DELL_OPTIPLEX_3050 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_16384 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select INTEL_GMA_HAVE_VBT + select INTEL_INT15 + select SOC_INTEL_KABYLAKE + select MAINBOARD_SUPPORTS_SKYLAKE_CPU + select MAINBOARD_SUPPORTS_KABYLAKE_CPU + select SKYLAKE_SOC_PCH_H + select MAINBOARD_HAS_LIBGFXINIT + +config CBFS_SIZE + default 0x100000 + +config MAINBOARD_DIR + default "dell/optiplex_3050" + +config MAINBOARD_PART_NUMBER + default "OptiPlex 3050" + +config PRERAM_CBMEM_CONSOLE_SIZE + hex + default 0xd00 + +config DIMM_SPD_SIZE + default 512 #DDR4 + +endif diff --git a/src/mainboard/dell/optiplex_3050/Kconfig.name b/src/mainboard/dell/optiplex_3050/Kconfig.name new file mode 100644 index 0000000..efab962 --- /dev/null +++ b/src/mainboard/dell/optiplex_3050/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config BOARD_DELL_OPTIPLEX_3050 + bool "OptiPlex 3050" diff --git a/src/mainboard/dell/optiplex_3050/Makefile.mk b/src/mainboard/dell/optiplex_3050/Makefile.mk new file mode 100644 index 0000000..510d82b --- /dev/null +++ b/src/mainboard/dell/optiplex_3050/Makefile.mk @@ -0,0 +1,17 @@ +## SPDX-License-Identifier: GPL-2.0-only + +subdirs-y += spd +bootblock-y += bootblock.c + +romstage-y += romstage.c + +ramstage-y += mainboard.c +ramstage-y += ramstage.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +cbfs-files-y += spd_50.bin +spd_50.bin-file := spd_50.bin +spd_50.bin-type := raw +cbfs-files-y += spd_52.bin +spd_52.bin-file := spd_52.bin +spd_52.bin-type := raw diff --git a/src/mainboard/dell/optiplex_3050/acpi/dptf.asl b/src/mainboard/dell/optiplex_3050/acpi/dptf.asl new file mode 100644 index 0000000..bec32ae --- /dev/null +++ b/src/mainboard/dell/optiplex_3050/acpi/dptf.asl @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define DPTF_CPU_PASSIVE 98 +#define DPTF_CPU_CRITICAL 125 +#define DPTF_CPU_ACTIVE_AC0 91 +#define DPTF_CPU_ACTIVE_AC1 85 +#define DPTF_CPU_ACTIVE_AC2 83 +#define DPTF_CPU_ACTIVE_AC3 80 +#define DPTF_CPU_ACTIVE_AC4 75 + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 }, + +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 10000, /* PowerLimitMinimum */ + 31000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 28000, /* TimeWindowMaximum */ + 100 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 15000, /* PowerLimitMinimum */ + 65000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 28000, /* TimeWindowMaximum */ + 100 /* StepSize */ + } +}) + +/* Include DPTF */ +#include <soc/intel/skylake/acpi/dptf/dptf.asl> diff --git a/src/mainboard/dell/optiplex_3050/acpi/ec.asl b/src/mainboard/dell/optiplex_3050/acpi/ec.asl new file mode 100644 index 0000000..16990d4 --- /dev/null +++ b/src/mainboard/dell/optiplex_3050/acpi/ec.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/dell/optiplex_3050/acpi/mainboard.asl b/src/mainboard/dell/optiplex_3050/acpi/mainboard.asl new file mode 100644 index 0000000..16990d4 --- /dev/null +++ b/src/mainboard/dell/optiplex_3050/acpi/mainboard.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/dell/optiplex_3050/acpi/superio.asl b/src/mainboard/dell/optiplex_3050/acpi/superio.asl new file mode 100644 index 0000000..16990d4 --- /dev/null +++ b/src/mainboard/dell/optiplex_3050/acpi/superio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/dell/optiplex_3050/board_info.txt b/src/mainboard/dell/optiplex_3050/board_info.txt new file mode 100644 index 0000000..340e2ab --- /dev/null +++ b/src/mainboard/dell/optiplex_3050/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.asus.com/supportonly/h110m-adp/helpdesk_cpu/ +ROM package: DIP-8 +ROM protocol: SPI +ROM socketed: y +Flashrom support: y +Release year: 2015 diff --git a/src/mainboard/dell/optiplex_3050/bootblock.c b/src/mainboard/dell/optiplex_3050/bootblock.c new file mode 100644 index 0000000..f12693b --- /dev/null +++ b/src/mainboard/dell/optiplex_3050/bootblock.c @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <soc/gpio.h> +#include "include/gpio.h" + +static void early_config_superio(void) +{ + +} + +static void early_config_gpio(void) +{ + /* This is a hack for FSP because it does things in MemoryInit() + * which it shouldn't do. We have to prepare certain gpios here + * because of the brokenness in FSP. */ + // gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} + +void bootblock_mainboard_init(void) +{ + early_config_gpio(); +} + +void bootblock_mainboard_early_init(void) +{ + early_config_superio(); +} diff --git a/src/mainboard/dell/optiplex_3050/cmos.default b/src/mainboard/dell/optiplex_3050/cmos.default new file mode 100644 index 0000000..84236aa --- /dev/null +++ b/src/mainboard/dell/optiplex_3050/cmos.default @@ -0,0 +1,6 @@ +## SPDX-License-Identifier: GPL-2.0-only + +boot_option=Fallback +debug_level=Debug +power_on_after_fail=Disable +nmi=Enable diff --git a/src/mainboard/dell/optiplex_3050/cmos.layout b/src/mainboard/dell/optiplex_3050/cmos.layout new file mode 100644 index 0000000..cff042a --- /dev/null +++ b/src/mainboard/dell/optiplex_3050/cmos.layout @@ -0,0 +1,55 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 6 debug_level + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail + +# coreboot config options: bootloader +#Used by ChromeOS: +416 128 r 0 vbnv + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/mainboard/dell/optiplex_3050/devicetree.cb b/src/mainboard/dell/optiplex_3050/devicetree.cb new file mode 100644 index 0000000..e89b964e --- /dev/null +++ b/src/mainboard/dell/optiplex_3050/devicetree.cb @@ -0,0 +1,138 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip soc/intel/skylake + register "deep_sx_config" = "DSX_EN_WAKE_PIN" + + register "eist_enable" = "1" + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_B" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + + # Enable DPTF + register "dptf_enable" = "1" + + # FSP Configuration + register "PrimaryDisplay" = "Display_PEG" + + # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch + # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s + register "PmConfigSlpS3MinAssert" = "0x02" + + # SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s + register "PmConfigSlpS4MinAssert" = "0x04" + + # SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s + register "PmConfigSlpSusMinAssert" = "0x03" + + # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s + register "PmConfigSlpAMinAssert" = "0x03" + + # PL2 override 91W + register "power_limits_config" = "{ .tdp_pl2_override = 91, }" + + # Send an extra VR mailbox command for the PS4 exit issue + register "SendVrMbxCmd" = "2" + + device cpu_cluster 0 on end + + device domain 0 on + # Host bridge + device pci 00.0 on end + + # PCIe x16 + device pci 01.0 on + end + + # Intel iGPU + device pci 02.0 on end + + # XHCI controller + device pci 14.0 on + register "usb2_ports" = "{ + [0] = USB2_PORT_MID(OC0), + [1] = USB2_PORT_MID(OC0), + [2] = USB2_PORT_MID(OC4), + [3] = USB2_PORT_MID(OC4), + [4] = USB2_PORT_MID(OC2), + [5] = USB2_PORT_MID(OC2), + [6] = USB2_PORT_MID(OC0), + [7] = USB2_PORT_MID(OC0), + [8] = USB2_PORT_MID(OC0), + [9] = USB2_PORT_MID(OC0), + [10] = USB2_PORT_MID(OC1), + [11] = USB2_PORT_MID(OC1), + [12] = USB2_PORT_MID(OC_SKIP), + [13] = USB2_PORT_MID(OC_SKIP), + }" + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC0), + [1] = USB3_PORT_DEFAULT(OC0), + [2] = USB3_PORT_DEFAULT(OC3), + [3] = USB3_PORT_DEFAULT(OC3), + [4] = USB3_PORT_DEFAULT(OC1), + [5] = USB3_PORT_DEFAULT(OC1), + [6] = USB3_PORT_DEFAULT(OC_SKIP), + [7] = USB3_PORT_DEFAULT(OC_SKIP), + [8] = USB3_PORT_DEFAULT(OC_SKIP), + [9] = USB3_PORT_DEFAULT(OC_SKIP), + }" + end + + # ME interface + device pci 16.0 on end + + # SATA + device pci 17.0 on + register "SataSalpSupport" = "1" + register "SataPortsEnable" = "{ + [0] = 1, + [1] = 1, + [2] = 1, + [3] = 1, + }" + end + + # RP #5 - PCIe 1x + device pci 1c.4 on + register "PcieRpEnable[4]" = "1" + register "PcieRpClkReqSupport[4]" = "0" + register "PcieRpHotPlug[4]" = "1" + end + + # RP #8 - Realtek LAN + device pci 1c.7 on + register "PcieRpEnable[7]" = "1" + register "PcieRpClkReqSupport[7]" = "0" + register "PcieRpHotPlug[7]" = "1" + end + + # RP #9 - PCIe 1x + device pci 1d.0 on + register "PcieRpEnable[8]" = "1" + register "PcieRpClkReqSupport[8]" = "0" + register "PcieRpHotPlug[8]" = "1" + end + + # LPC + device pci 1f.0 on + # Set @0x280-0x2ff I/O Range for SuperIO HWM + register "gen1_dec" = "0x007c0281" + + # Set LPC Serial IRQ mode + register "serirq_mode" = "SERIRQ_CONTINUOUS" + end + + # HD Audio + device pci 1f.3 on + register "PchHdaVcType" = "Vc1" + end + + # SMBus + device pci 1f.4 on end + end +end diff --git a/src/mainboard/dell/optiplex_3050/dsdt.asl b/src/mainboard/dell/optiplex_3050/dsdt.asl new file mode 100644 index 0000000..b02708f --- /dev/null +++ b/src/mainboard/dell/optiplex_3050/dsdt.asl @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 +) +{ + #include <acpi/dsdt_top.asl> + #include <soc/intel/common/block/acpi/acpi/platform.asl> + + // global NVS and variables + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + + // CPU + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + /* Image processing unit */ + #include <soc/intel/skylake/acpi/ipu.asl> + #include <soc/intel/skylake/acpi/systemagent.asl> + #include <soc/intel/skylake/acpi/pch.asl> + } + + // Dynamic Platform Thermal Framework + #include "acpi/dptf.asl" + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> + + // Mainboard specific + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/dell/optiplex_3050/gma-mainboard.ads b/src/mainboard/dell/optiplex_3050/gma-mainboard.ads new file mode 100644 index 0000000..3f7289a --- /dev/null +++ b/src/mainboard/dell/optiplex_3050/gma-mainboard.ads @@ -0,0 +1,18 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI1, -- DDI1 - DVI + HDMI2, -- DDI2 - HDMI + DP3, -- DDI3 - DP + eDP, -- eDP - VGA via RTD2168 (Doesn't seem to work) + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/dell/optiplex_3050/include/gpio.h b/src/mainboard/dell/optiplex_3050/include/gpio.h new file mode 100644 index 0000000..5f0eef4 --- /dev/null +++ b/src/mainboard/dell/optiplex_3050/include/gpio.h @@ -0,0 +1,246 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef CFG_GPIO_H +#define CFG_GPIO_H + +#include <gpio.h> + +/* Pad configuration was generated automatically using intelp2m utility */ +static const struct pad_config gpio_table[] = { + + /* ------- GPIO Community 0 ------- */ + + /* ------- GPIO Group GPP_A ------- */ + _PAD_CFG_STRUCT(GPP_A0, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPP_A1, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPP_A2, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPP_A3, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPP_A4, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPP_A5, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_A6, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_A7, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_A8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_A9, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_A10, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_A11, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), + PAD_CFG_GPO(GPP_A12, 0, PLTRST), + _PAD_CFG_STRUCT(GPP_A13, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_A14, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_A15, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), + PAD_CFG_GPO(GPP_A16, 0, PLTRST), + PAD_CFG_GPO(GPP_A17, 0, PLTRST), + PAD_CFG_GPO(GPP_A18, 0, PLTRST), + PAD_CFG_GPO(GPP_A19, 0, PLTRST), + PAD_CFG_GPO(GPP_A20, 0, PLTRST), + _PAD_CFG_STRUCT(GPP_A21, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + PAD_CFG_GPO(GPP_A22, 0, PLTRST), + PAD_CFG_GPO(GPP_A23, 0, PLTRST), + + /* ------- GPIO Group GPP_B ------- */ + PAD_CFG_GPO(GPP_B0, 0, PLTRST), + PAD_CFG_GPO(GPP_B1, 0, PLTRST), + PAD_CFG_GPO(GPP_B2, 0, DEEP), + PAD_CFG_GPO(GPP_B3, 1, RSMRST), + _PAD_CFG_STRUCT(GPP_B4, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + PAD_CFG_GPO(GPP_B5, 1, PLTRST), + PAD_CFG_GPO(GPP_B6, 1, PLTRST), + PAD_CFG_GPO(GPP_B7, 0, PLTRST), + _PAD_CFG_STRUCT(GPP_B8, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + PAD_CFG_GPO(GPP_B9, 0, PLTRST), + PAD_CFG_GPO(GPP_B10, 0, PLTRST), + PAD_CFG_GPO(GPP_B11, 1, PLTRST), + _PAD_CFG_STRUCT(GPP_B12, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_B13, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_B14, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), PAD_PULL(DN_20K)), + _PAD_CFG_STRUCT(GPP_B15, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + PAD_CFG_GPO(GPP_B16, 0, PLTRST), + PAD_CFG_GPO(GPP_B17, 0, PLTRST), + _PAD_CFG_STRUCT(GPP_B18, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, PAD_PULL(DN_20K)), + PAD_CFG_GPO(GPP_B19, 0, PLTRST), + PAD_CFG_GPO(GPP_B20, 0, DEEP), + PAD_CFG_GPO(GPP_B21, 0, DEEP), + _PAD_CFG_STRUCT(GPP_B22, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | 1, PAD_PULL(DN_20K)), + _PAD_CFG_STRUCT(GPP_B23, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), PAD_PULL(DN_20K)), + + /* ------- GPIO Community 1 ------- */ + + /* ------- GPIO Group GPP_C ------- */ +/* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), +/* SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + + + _PAD_CFG_STRUCT(GPP_C2, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(DN_20K)), + _PAD_CFG_STRUCT(GPP_C3, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_C4, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + PAD_CFG_GPI_TRIG_OWN(GPP_C5, DN_20K, DEEP, OFF, ACPI), + /* GPP_C6 - RESERVED */ + /* GPP_C7 - RESERVED */ + PAD_CFG_GPO(GPP_C8, 0, PLTRST), + PAD_CFG_GPO(GPP_C9, 0, PLTRST), + PAD_CFG_GPO(GPP_C10, 0, PLTRST), + PAD_CFG_GPO(GPP_C11, 0, PLTRST), + PAD_CFG_GPO(GPP_C12, 0, PLTRST), + PAD_CFG_GPO(GPP_C13, 0, PLTRST), + PAD_CFG_GPO(GPP_C14, 0, PLTRST), + PAD_CFG_GPO(GPP_C15, 0, PLTRST), + _PAD_CFG_STRUCT(GPP_C16, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_C17, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), 0), + PAD_CFG_GPO(GPP_C18, 0, PLTRST), + PAD_CFG_GPO(GPP_C19, 0, PLTRST), + PAD_CFG_GPO(GPP_C20, 0, PLTRST), + PAD_CFG_GPO(GPP_C21, 0, PLTRST), + PAD_CFG_GPO(GPP_C22, 0, PLTRST), + _PAD_CFG_STRUCT(GPP_C23, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + + /* ------- GPIO Group GPP_D ------- */ + PAD_CFG_GPO(GPP_D0, 0, PLTRST), + PAD_CFG_GPO(GPP_D1, 0, PLTRST), + PAD_CFG_GPO(GPP_D2, 0, PLTRST), + PAD_CFG_GPO(GPP_D3, 0, PLTRST), + PAD_CFG_GPO(GPP_D4, 0, PLTRST), + _PAD_CFG_STRUCT(GPP_D5, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + PAD_CFG_GPO(GPP_D6, 0, DEEP), + PAD_CFG_GPO(GPP_D7, 0, PLTRST), + PAD_CFG_GPO(GPP_D8, 0, PLTRST), + PAD_CFG_GPO(GPP_D9, 0, PLTRST), + PAD_CFG_GPO(GPP_D10, 0, PLTRST), + PAD_CFG_GPO(GPP_D11, 0, PLTRST), + PAD_CFG_GPO(GPP_D12, 0, PLTRST), + PAD_CFG_GPO(GPP_D13, 0, PLTRST), + PAD_CFG_GPO(GPP_D14, 0, PLTRST), + PAD_CFG_GPO(GPP_D15, 0, PLTRST), + PAD_CFG_GPO(GPP_D16, 0, PLTRST), + PAD_CFG_GPO(GPP_D17, 0, PLTRST), + PAD_CFG_GPO(GPP_D18, 0, PLTRST), + PAD_CFG_GPO(GPP_D19, 0, PLTRST), + PAD_CFG_GPO(GPP_D20, 0, PLTRST), + PAD_CFG_GPO(GPP_D21, 0, PLTRST), + PAD_CFG_GPO(GPP_D22, 0, PLTRST), + PAD_CFG_GPO(GPP_D23, 0, PLTRST), + + /* ------- GPIO Group GPP_E ------- */ + _PAD_CFG_STRUCT(GPP_E0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_E1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_E2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + PAD_CFG_GPO(GPP_E3, 0, DEEP), + PAD_CFG_GPO(GPP_E4, 0, DEEP), + PAD_CFG_GPO(GPP_E5, 0, PLTRST), + PAD_CFG_GPO(GPP_E6, 0, PLTRST), + _PAD_CFG_STRUCT(GPP_E7, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_E8, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_E9, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPP_E10, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPP_E11, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPP_E12, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), + + /* ------- GPIO Group GPP_F ------- */ + _PAD_CFG_STRUCT(GPP_F0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_F1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_F2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_F3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_F4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + PAD_CFG_GPI_TRIG_OWN(GPP_F5, NONE, PLTRST, OFF, ACPI), + _PAD_CFG_STRUCT(GPP_F6, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_F7, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_F8, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + PAD_CFG_GPO(GPP_F9, 0, RSMRST), + PAD_CFG_GPI_TRIG_OWN(GPP_F10, NONE, DEEP, OFF, ACPI), + _PAD_CFG_STRUCT(GPP_F11, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_F12, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + PAD_CFG_GPO(GPP_F13, 0, PLTRST), + PAD_CFG_GPI_TRIG_OWN(GPP_F14, NONE, DEEP, OFF, ACPI), + _PAD_CFG_STRUCT(GPP_F15, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPP_F16, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPP_F17, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), + PAD_CFG_TERM_GPO(GPP_F18, 0, UP_20K, DEEP), + PAD_CFG_GPO(GPP_F19, 0, PLTRST), + PAD_CFG_GPO(GPP_F20, 1, DEEP), + PAD_CFG_GPO(GPP_F21, 1, PLTRST), + PAD_CFG_GPO(GPP_F22, 1, PLTRST), + PAD_CFG_GPO(GPP_F23, 1, RSMRST), + + /* ------- GPIO Group GPP_G ------- */ + PAD_CFG_GPI_TRIG_OWN(GPP_G0, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_G1, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_G2, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_G3, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_G4, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_G5, NONE, PLTRST, OFF, ACPI), + _PAD_CFG_STRUCT(GPP_G6, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + PAD_CFG_GPI_TRIG_OWN(GPP_G7, NONE, PLTRST, OFF, ACPI), + _PAD_CFG_STRUCT(GPP_G8, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_G9, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + PAD_CFG_GPI_TRIG_OWN(GPP_G10, NONE, DEEP, OFF, ACPI), + _PAD_CFG_STRUCT(GPP_G11, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) | 1, 0), + _PAD_CFG_STRUCT(GPP_G12, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_G13, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + PAD_CFG_GPO(GPP_G14, 0, DEEP), + PAD_CFG_GPO(GPP_G15, 1, DEEP), + PAD_CFG_GPO(GPP_G16, 1, DEEP), + PAD_CFG_GPO(GPP_G17, 1, DEEP), + PAD_CFG_GPO(GPP_G18, 0, PLTRST), + PAD_CFG_GPO(GPP_G19, 1, DEEP), + PAD_CFG_GPO(GPP_G20, 1, PLTRST), + PAD_CFG_GPO(GPP_G21, 0, DEEP), + PAD_CFG_GPO(GPP_G22, 0, DEEP), + PAD_CFG_GPO(GPP_G23, 0, PLTRST), + + /* ------- GPIO Group GPP_H ------- */ + PAD_CFG_GPO(GPP_H0, 0, DEEP), + _PAD_CFG_STRUCT(GPP_H1, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + PAD_CFG_GPO(GPP_H2, 0, PLTRST), + PAD_CFG_GPO(GPP_H3, 0, PLTRST), + PAD_CFG_GPO(GPP_H4, 0, PLTRST), + PAD_CFG_GPO(GPP_H5, 0, PLTRST), + PAD_CFG_GPO(GPP_H6, 1, DEEP), + PAD_CFG_GPO(GPP_H7, 0, PLTRST), + PAD_CFG_GPO(GPP_H8, 0, PLTRST), + PAD_CFG_GPO(GPP_H9, 0, PLTRST), + PAD_CFG_GPO(GPP_H10, 0, PLTRST), + PAD_CFG_GPO(GPP_H11, 0, PLTRST), + PAD_CFG_TERM_GPO(GPP_H12, 1, DN_20K, DEEP), + PAD_CFG_GPO(GPP_H13, 1, PLTRST), + PAD_CFG_GPO(GPP_H14, 0, PLTRST), + PAD_CFG_GPO(GPP_H15, 0, PLTRST), + PAD_CFG_GPO(GPP_H16, 0, PLTRST), + PAD_CFG_GPO(GPP_H17, 0, PLTRST), + PAD_CFG_GPO(GPP_H18, 0, PLTRST), + PAD_CFG_GPO(GPP_H19, 0, PLTRST), + PAD_CFG_GPO(GPP_H20, 0, PLTRST), + PAD_CFG_GPO(GPP_H21, 0, PLTRST), + PAD_CFG_GPO(GPP_H22, 0, PLTRST), + PAD_CFG_GPO(GPP_H23, 0, PLTRST), + + /* ------- GPIO Community 2 ------- */ + + /* -------- GPIO Group GPD -------- */ + _PAD_CFG_STRUCT(GPD0, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), 0), + PAD_CFG_GPO(GPD1, 0, PWROK), + _PAD_CFG_STRUCT(GPD2, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPD3, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPD4, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), + _PAD_CFG_STRUCT(GPD5, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), + _PAD_CFG_STRUCT(GPD6, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), + PAD_CFG_GPO(GPD7, 1, RSMRST), + _PAD_CFG_STRUCT(GPD8, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), + _PAD_CFG_STRUCT(GPD9, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), + _PAD_CFG_STRUCT(GPD10, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), + PAD_CFG_GPO(GPD11, 1, RSMRST), + + /* ------- GPIO Community 3 ------- */ + + /* ------- GPIO Group GPP_I ------- */ + _PAD_CFG_STRUCT(GPP_I0, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_I1, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_I2, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_I3, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_I4, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_I5, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_I6, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | 1, PAD_PULL(DN_20K)), + _PAD_CFG_STRUCT(GPP_I7, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_I8, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) | 1, PAD_PULL(DN_20K)), + _PAD_CFG_STRUCT(GPP_I9, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_I10, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | 1, PAD_PULL(DN_20K)), +}; + +#endif /* CFG_GPIO_H */ diff --git a/src/mainboard/dell/optiplex_3050/mainboard.c b/src/mainboard/dell/optiplex_3050/mainboard.c new file mode 100644 index 0000000..f0dbc3f --- /dev/null +++ b/src/mainboard/dell/optiplex_3050/mainboard.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> + +static void mainboard_enable(struct device *dev) +{ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/dell/optiplex_3050/ramstage.c b/src/mainboard/dell/optiplex_3050/ramstage.c new file mode 100644 index 0000000..1a30ecc --- /dev/null +++ b/src/mainboard/dell/optiplex_3050/ramstage.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/ramstage.h> +#include "include/gpio.h" + +void mainboard_silicon_init_params(FSP_SIL_UPD *params) +{ + /* Configure pads prior to SiliconInit() in case there's any + * dependencies during hardware initialization. */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); + + params->CdClock = 3; +} diff --git a/src/mainboard/dell/optiplex_3050/romstage.c b/src/mainboard/dell/optiplex_3050/romstage.c new file mode 100644 index 0000000..f1764b2 --- /dev/null +++ b/src/mainboard/dell/optiplex_3050/romstage.c @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <assert.h> +#include <soc/romstage.h> +#include <stdint.h> +#include <string.h> +#include <spd_bin.h> +#include <cbfs.h> + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + size_t l; + + FSP_M_CONFIG * const mem_cfg = &mupd->FspmConfig; + + mem_cfg->DqPinsInterleaved = true; + mem_cfg->CaVrefConfig = 2; + + mem_cfg->MemorySpdDataLen = 512; + mem_cfg->MemorySpdPtr00 = (uintptr_t)cbfs_map("spd_50.bin", &l); + mem_cfg->MemorySpdPtr10 = (uintptr_t)cbfs_map("spd_52.bin", &l); + +/* + const u16 rcomp_resistors[] = {121, 75, 100}; + + assert(sizeof(mem_cfg->RcompResistor) == sizeof(rcomp_resistors)); + memcpy(mem_cfg->RcompResistor, rcomp_resistors, sizeof(rcomp_resistors)); + + const u16 rcomp_targets[] = {60, 26, 20, 20, 26}; + + assert(sizeof(mem_cfg->RcompTarget) == sizeof(rcomp_targets)); + memcpy(mem_cfg->RcompTarget, rcomp_targets, sizeof(rcomp_targets)); +*/ +} diff --git a/src/mainboard/dell/optiplex_3050/spd_50.bin b/src/mainboard/dell/optiplex_3050/spd_50.bin new file mode 100644 index 0000000..f1757b5 --- /dev/null +++ b/src/mainboard/dell/optiplex_3050/spd_50.bin Binary files differ diff --git a/src/mainboard/dell/optiplex_3050/spd_52.bin b/src/mainboard/dell/optiplex_3050/spd_52.bin new file mode 100644 index 0000000..126c273 --- /dev/null +++ b/src/mainboard/dell/optiplex_3050/spd_52.bin Binary files differ -- To view, visit https://review.coreboot.org/c/coreboot/+/82053?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8d443e39ee684a4eaa19c835a945cfe569c051e2 Gerrit-Change-Number: 82053 Gerrit-PatchSet: 1 Gerrit-Owner: Máté Kukri <kukri.mate(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: Makefile.mk: Associate reproducible build to commit ID
by Martin Roth (Code Review) 22 Apr '24

22 Apr '24

Attention is currently required from: Christian Walter, Elyes Haouas, Felix Held, Felix Singer, Martin L Roth, Name of user not set #1005382, Naveen Iyer, Paul Menzel. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82006?usp=email ) Change subject: Makefile.mk: Associate reproducible build to commit ID ...................................................................... Patch Set 7: (1 comment) Patchset: PS7: > the regular build includes the git hash, but also a build data, so it's not reproducible. […] The regular build should be reproducible. If it isn't, that's a bug. We can include the git hash - that's reproducible as well - we don't need a separate build. -- To view, visit https://review.coreboot.org/c/coreboot/+/82006?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I97b0c4ea654df23844f31a3398b6f0d05dfec1ab Gerrit-Change-Number: 82006 Gerrit-PatchSet: 7 Gerrit-Owner: Naveen Iyer Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Naveen Iyer Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: Name of user not set #1005382 Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Naveen Iyer Gerrit-Attention: Name of user not set #1005382 Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Mon, 22 Apr 2024 21:29:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Name of user not set #1005382 Comment-In-Reply-To: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[main]: Makefile.mk: Associate reproducible build to commit ID
by Felix Held (Code Review) 22 Apr '24

22 Apr '24

Attention is currently required from: Christian Walter, Elyes Haouas, Felix Singer, Martin L Roth, Martin Roth, Name of user not set #1005382, Naveen Iyer, Paul Menzel. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82006?usp=email ) Change subject: Makefile.mk: Associate reproducible build to commit ID ...................................................................... Patch Set 7: (3 comments) File Makefile.mk: https://review.coreboot.org/c/coreboot/+/82006/comment/e5c75454_04305592 : PS7, Line 28: KERNELVERSION := $(shell test -z "$$(git status --porcelain)" && git log --no-abbrev-commit -1 --format="format:%H" ) this does a similar thing as the case below, so it would probably be better to use that in that case too instead of sort-of reimplementing it. the check for the tree not being dirty could probably be integrated into that case and only be done in the BUILD_TIMELESS_WITH_GITREV case https://review.coreboot.org/c/coreboot/+/82006/comment/15786882_7068a7e6 : PS7, Line 496: CPPFLAGS_common += -D__TIMELESS__ this also needs to be done in the BUILD_TIMELESS_WITH_GITREV case for the build to be reproducible; otherwise the asserts will still contain line numbers File util/genbuild_h/genbuild_h.sh: https://review.coreboot.org/c/coreboot/+/82006/comment/6fa6fdee_3e6de4fd : PS7, Line 37: H does %H vs %h make any difference? would probably be good to use the same as in the already existing case after this one -- To view, visit https://review.coreboot.org/c/coreboot/+/82006?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I97b0c4ea654df23844f31a3398b6f0d05dfec1ab Gerrit-Change-Number: 82006 Gerrit-PatchSet: 7 Gerrit-Owner: Naveen Iyer Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Naveen Iyer Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: Name of user not set #1005382 Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Naveen Iyer Gerrit-Attention: Name of user not set #1005382 Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Mon, 22 Apr 2024 20:44:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: Makefile.mk: Associate reproducible build to commit ID
by Felix Held (Code Review) 22 Apr '24

22 Apr '24

Attention is currently required from: Christian Walter, Elyes Haouas, Felix Singer, Martin L Roth, Martin Roth, Name of user not set #1005382, Naveen Iyer, Paul Menzel. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82006?usp=email ) Change subject: Makefile.mk: Associate reproducible build to commit ID ...................................................................... Patch Set 7: (1 comment) Patchset: PS7: > Can I get GITREV info just from booting coreboot. […] the regular build includes the git hash, but also a build data, so it's not reproducible. the timeless build doesn't include a data, but also doesn't include the git hash. to have a reproducible build that contains the git hash of the commit it was built from, i suggested implementing another option that does exactly this -- To view, visit https://review.coreboot.org/c/coreboot/+/82006?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I97b0c4ea654df23844f31a3398b6f0d05dfec1ab Gerrit-Change-Number: 82006 Gerrit-PatchSet: 7 Gerrit-Owner: Naveen Iyer Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Naveen Iyer Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: Name of user not set #1005382 Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Naveen Iyer Gerrit-Attention: Name of user not set #1005382 Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Mon, 22 Apr 2024 20:32:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Name of user not set #1005382 Comment-In-Reply-To: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: comment

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