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Change subject: mainboard/intel: Add initial support for Avenue City CRB
......................................................................
Patch Set 24:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/81319/comment/ca113f26_05385c02 :
PS24, Line 7: mainboard/intel
> Done
opps, looks like you missed it 😊
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Change subject: mb/google/{brya,hades}: use soc index for variant_update_power_limits()
......................................................................
Patch Set 7:
(1 comment)
File src/mainboard/google/brya/variants/baseboard/brya/ramstage.c:
https://review.coreboot.org/c/coreboot/+/81436/comment/5f765e36_a2c81c6b :
PS5, Line 68: soc_config->tdp_pl4 = DIV_ROUND_UP(limits[i].pl4_power,
> SOC will use the lower PL1/PL2 value of MMIO and MSR. If user may want to override PL1/PL2 to higher value than original one which is in MSR, SOC will never take higher one since PL1/PL2 are limited by the lower values in MSR.
> IMO it would be better to set MSR PL1/PL2 values here, how do you think?
I would recommend to land this CL as is and move PL1/PL2 override discussion to a bug.
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Change subject: mb/google/brox: Enable PMC pins to work with PD
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Patch Set 2:
(3 comments)
File src/mainboard/google/brox/variants/baseboard/brox/gpio.c:
https://review.coreboot.org/c/coreboot/+/81207/comment/011e3c47_ed84cfda :
PS2, Line 105: NC
should remove NC?
https://review.coreboot.org/c/coreboot/+/81207/comment/e9686872_df850953 :
PS2, Line 137: NC
same
https://review.coreboot.org/c/coreboot/+/81207/comment/20613abe_db95787d :
PS2, Line 139: NC
same
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Change subject: mb/google/brox: Enable PMC pins to work with PD
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Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/81207/comment/6431911f_76e46687 :
PS1, Line 9: For PMC-PD communication we need to enable 3 pins.
> These pins are configured based on HW team's brox sheet.
this information for SoC (about native function) is captured in it's datasheet (EDS in your case), there should be a table called "pin mux" or something similar in the datasheet which should have info on all the native functions of all GPIO. It would be good if you could mention Doc Number and revision of the EDS which has this info about native function in commit msg.
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Change subject: mb/google/{brya,hades}: use soc index for variant_update_power_limits()
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Patch Set 7:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/81436/comment/285df4a0_a11fa176 :
PS5, Line 13: override the PL4 value
> Please add me in this bug b/328729536. […]
The purpose of this code is to override PL1/PL2/PL4 settings for the each board according to thier power/thermal design.
The main reason for this CL was current code cannot set tdp_pl4 value since the pointer variable is incorrect. I corrected it.
About setting tdp_pl1_override and tdp_pl2_override is just my suggestion. In case of "AC only" or "Critical battery" case, we may want to limit PL2/PL4 like this: https://review.coreboot.org/c/coreboot/+/79329.
We override PL1 and PL2 of coreboot DTT setting only. As I know DTT will use DTT policy in OS than coreboot DTT config, then DTT can set to higher value. So I thought PL2 MMIO override doesn't have any effect in this case. (e.g. coreboot DTT PL2: 40W, but OS DTT policy can be PL2: 60W) If I'm misunderstanding about DTT or it's nothing to be worried about, we just can forget this scenario.
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Change subject: mb/google/brya: Add VBT data files for bujia
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/81553/comment/ec493341_80770219 :
PS1, Line 1: Parent: 67dd3717 (mb/google/brya/var/bujia: Update devicetree setting)
var/bujia
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Change subject: mb/google/brya: Add VBT data files for bujia
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Patch Set 1: Code-Review+2
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