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Change subject: mb/google/dedede: Add VBTs and select INTEL_GMA_HAVE_VBT
......................................................................
Patch Set 1: Code-Review+2
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Change subject: util/showdevicetree: drop unmaintained tool
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/79934/comment/0459d99d_ba7836cf :
PS3, Line 7: [RFC]
> Patch seems good to me. […]
Done
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Hello Arthur Heymans, Martin L Roth, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#4).
Change subject: util/showdevicetree: drop unmaintained tool
......................................................................
util/showdevicetree: drop unmaintained tool
This tool doesn't have a makefile, when trying to compile it manually
with the given instructions it even fails to compile after fixing the
paths in the given command, and it references the non-existing
PCI_BUS_SEGN_BITS Kconfig symbol, so just drop this.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I8ca75db281a215bf3f194ab72a107f666dc0694e
---
D util/showdevicetree/description.md
D util/showdevicetree/showdt.c
2 files changed, 0 insertions(+), 157 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/79934/4
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Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80467?usp=email )
Change subject: mb/google/brox: Set PCH_EC_PCH_INT_ODL pin as IOAPIC
......................................................................
mb/google/brox: Set PCH_EC_PCH_INT_ODL pin as IOAPIC
Setting the EC interrupt GPIO as an APIC is able to solve many
problems that we are currently seeing:
1. Routing through the APIC make the IRQ# associated with this pin
unavailable to claim for other devices in the kernel. This is causing
EC interrupts to not work.
2. Since EC interrupt are not working, we are not able to flash the
EC from the DUT.
3. Also, the GPI_INT configuration does not allow us to set the
polarity of the GPIO, which means that it is by default set as active
high. As a result, we are seeing an excessive number of host command
interrupts to the EC. This disappears when we change the
configuration to APIC and set the polarity as INVERT.
BUG=b:319129926,b:324707182
BRANCH=None
TEST=1. After boot up, check if ec_cros_lpcs driver was successfully
registered. Look for the following string:
"cros_ec_lpcs GOOG0004:00: Chrome EC device registered"
2. Make sure can flash the EC image from the DUT
3. Make sure EC console is not getting continuous stream of host
commands.
Change-Id: I74bff88d2ddbaf1f4b085c31d582bd66e18c438a
Signed-off-by: Shelley Chen <shchen(a)google.com>
---
M src/mainboard/google/brox/variants/baseboard/brox/gpio.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/80467/1
diff --git a/src/mainboard/google/brox/variants/baseboard/brox/gpio.c b/src/mainboard/google/brox/variants/baseboard/brox/gpio.c
index 1464820..337fde1 100644
--- a/src/mainboard/google/brox/variants/baseboard/brox/gpio.c
+++ b/src/mainboard/google/brox/variants/baseboard/brox/gpio.c
@@ -140,7 +140,7 @@
PAD_NC(GPP_C7, NONE),
/* GPP_D0 : [NF1: ISH_GP0 NF2: BK0 NF5: SBK0 NF6: USB_C_GPP_D0] ==> PCH_EC_PCH_INT_ODL */
- PAD_CFG_GPI_INT_SWAPPED(GPP_D0, NONE, PLTRST, LEVEL),
+ PAD_CFG_GPI_APIC_LOW(GPP_D0, NONE, PLTRST),
/* GPP_D1 : [NF1: ISH_GP1 NF2: BK1 NF5: SBK1 NF6: USB_C_GPP_D1] ==> PCH_EC_PCH_WAKE_ODL */
PAD_CFG_GPI_IRQ_WAKE(GPP_D1, NONE, DEEP, EDGE_SINGLE, INVERT),
/* GPP_D2 : [NF1: ISH_GP2 NF2: BK2 NF5: SBK2 NF6: USB_C_GPP_D2] ==> ISH_ACCEL_DB_INT_L (NC) */
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Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79905?usp=email )
Change subject: [RFC] region: Introduce region_create() functions
......................................................................
Patch Set 6:
(1 comment)
File util/cbfstool/cbfstool.c:
https://review.coreboot.org/c/coreboot/+/79905/comment/a54cffb5_b906e4aa :
PS1, Line 334: if (region_create_untrusted(
> Was a bit too focused on the types with that answer. And sorry for […]
Sorry, I didn't mean to keep this open. From my side, if we agree on having the `region_create_untrusted()` (as I think we did in the other comment?), it should be fine to use it here.
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Hello Kapil Porwal, Nick Vaccaro, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: mb/intel/adlrvp: Include ADL-N ID 5
......................................................................
mb/intel/adlrvp: Include ADL-N ID 5
This patch adds ADL N 4-core MCH ID 0x4618.
Signed-off-by: Sean Rhodes <sean(a)starlabs.systems>
Change-Id: I7b9fc64ccf8e2401dcd55607e8f09b348efb3182
---
M src/soc/intel/alderlake/vr_config.c
1 file changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/80166/7
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