coreboot-gerrit June 2023

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[XS] Change in coreboot[master]: util/bincfg: fix regressions introduced within last modification
by Stefan Reinauer (Code Review) 10 Jun '23

10 Jun '23

Stefan Reinauer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/29281?usp=email ) Change subject: util/bincfg: fix regressions introduced within last modification ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/29281?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I14d47aff149e18f8f86e78dc4e9beb3bbaac3670 Gerrit-Change-Number: 29281 Gerrit-PatchSet: 2 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Denis 'GNUtoo' Carikli <GNUtoo(a)cyberdimension.org> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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[M] Change in coreboot[master]: security/tpm: Move TPM2 NVRAM specific settings
by Stefan Reinauer (Code Review) 10 Jun '23

10 Jun '23

Stefan Reinauer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/29326?usp=email ) Change subject: security/tpm: Move TPM2 NVRAM specific settings ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/29326?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec9d1c272ed8d0872c9bbc406e98a19ac7a376bd Gerrit-Change-Number: 29326 Gerrit-PatchSet: 5 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: abandon

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[S] Change in coreboot[master]: ec/google/chromeec: set SCI event mask early on s0
by Stefan Reinauer (Code Review) 10 Jun '23

10 Jun '23

Stefan Reinauer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/28721?usp=email ) Change subject: ec/google/chromeec: set SCI event mask early on s0 ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/28721?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4d2b3e12d1d63dba29c5365c5a2fbf7b221226b Gerrit-Change-Number: 28721 Gerrit-PatchSet: 1 Gerrit-Owner: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Dhaval Sharma <dhaval.v.sharma(a)intel.corp-partner.google.com> Gerrit-MessageType: abandon

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[M] Change in coreboot[master]: mb/intel/icelake_rvp: Add DPTF information
by Stefan Reinauer (Code Review) 10 Jun '23

10 Jun '23

Stefan Reinauer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/29804?usp=email ) Change subject: mb/intel/icelake_rvp: Add DPTF information ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/29804?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id206417e2e8029abe1de2a35f58dc4e801f3986b Gerrit-Change-Number: 29804 Gerrit-PatchSet: 2 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

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[M] Change in coreboot[master]: [RFC] commonlib/region: Check `xlate` regions early
by Stefan Reinauer (Code Review) 10 Jun '23

10 Jun '23

Stefan Reinauer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/30083?usp=email ) Change subject: [RFC] commonlib/region: Check `xlate` regions early ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/30083?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2cdb9dd1ab9c00b227839a03fff389ba6fe78b4a Gerrit-Change-Number: 30083 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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[S] Change in coreboot[master]: mb/google/hatch: Enable SATA for Hatch
by Stefan Reinauer (Code Review) 10 Jun '23

10 Jun '23

Stefan Reinauer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/30433?usp=email ) Change subject: mb/google/hatch: Enable SATA for Hatch ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/30433?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70ae8d78e3fe4815c545606e07efc14f53334f6c Gerrit-Change-Number: 30433 Gerrit-PatchSet: 1 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-MessageType: abandon

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[XS] Change in coreboot[master]: WIP: turn on CLK_AB2 DMIC
by Stefan Reinauer (Code Review) 10 Jun '23

10 Jun '23

Stefan Reinauer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/30110?usp=email ) Change subject: WIP: turn on CLK_AB2 DMIC ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/30110?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I428b8737ca384bac0594d1f1b608644e14a2aa6d Gerrit-Change-Number: 30110 Gerrit-PatchSet: 1 Gerrit-Owner: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Gerrit-Reviewer: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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[XS] Change in coreboot[master]: mb/google/octopus/variants/fleex: Add PL1 throttling for TSR2
by Stefan Reinauer (Code Review) 10 Jun '23

10 Jun '23

Stefan Reinauer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/30359?usp=email ) Change subject: mb/google/octopus/variants/fleex: Add PL1 throttling for TSR2 ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/30359?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5e359afeab7808d162aca233cc1d995aa3c0a29c Gerrit-Change-Number: 30359 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan L Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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[S] Change in coreboot[master]: mb/google/hatch: Add SMI handlers
by Stefan Reinauer (Code Review) 10 Jun '23

10 Jun '23

Stefan Reinauer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/30441?usp=email ) Change subject: mb/google/hatch: Add SMI handlers ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/30441?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7127b44712cd89b3d583e9948698870ca0c64b2b Gerrit-Change-Number: 30441 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamirbohra(a)google.com> Gerrit-MessageType: abandon

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Change in ...coreboot[master]: cbmem_top: Change the return value to uintptr_t
by Arthur Heymans (Code Review) 10 Jun '23

10 Jun '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30693 Change subject: cbmem_top: Change the return value to uintptr_t ...................................................................... cbmem_top: Change the return value to uintptr_t This avoid a lot of casts. Change-Id: Iecec1cffba9dba02d06b10fe88aec173dbc08093 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/cbmem.c M src/cpu/allwinner/a10/cbmem.c M src/cpu/allwinner/a10/ram_segs.h M src/cpu/amd/family_10h-family_15h/ram_calc.c M src/cpu/intel/haswell/romstage.c M src/cpu/intel/haswell/stage_cache.c M src/cpu/intel/model_206ax/stage_cache.c M src/cpu/ti/am335x/cbmem.c M src/drivers/amd/agesa/mtrr_fixme.c M src/drivers/intel/fsp1_0/fsp_util.c M src/drivers/intel/fsp2_0/hob_verify.c M src/include/cbmem.h M src/include/imd.h M src/lib/ext_stage_cache.c M src/lib/imd.c M src/mainboard/emulation/qemu-armv7/cbmem.c M src/mainboard/emulation/qemu-i440fx/memory.c M src/mainboard/emulation/qemu-power8/cbmem.c M src/northbridge/intel/e7505/memmap.c M src/northbridge/intel/fsp_rangeley/raminit.c M src/northbridge/intel/gm45/ram_calc.c M src/northbridge/intel/haswell/ram_calc.c M src/northbridge/intel/i440bx/ram_calc.c M src/northbridge/intel/i945/ram_calc.c M src/northbridge/intel/nehalem/ram_calc.c M src/northbridge/intel/pineview/ram_calc.c M src/northbridge/intel/sandybridge/ram_calc.c M src/northbridge/intel/x4x/ram_calc.c M src/northbridge/via/vx900/memmap.c M src/soc/amd/stoneyridge/northbridge.c M src/soc/amd/stoneyridge/ramtop.c M src/soc/amd/stoneyridge/romstage.c M src/soc/cavium/cn81xx/cbmem.c M src/soc/imgtec/pistachio/cbmem.c M src/soc/intel/apollolake/memmap.c M src/soc/intel/apollolake/romstage.c M src/soc/intel/baytrail/memmap.c M src/soc/intel/baytrail/romstage/romstage.c M src/soc/intel/braswell/memmap.c M src/soc/intel/broadwell/memmap.c M src/soc/intel/broadwell/romstage/romstage.c D src/soc/intel/cannonlake/cbmem.c M src/soc/intel/cannonlake/memmap.c M src/soc/intel/cannonlake/romstage/romstage.c M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/denverton_ns/memmap.c M src/soc/intel/denverton_ns/romstage.c M src/soc/intel/fsp_baytrail/memmap.c M src/soc/intel/fsp_broadwell_de/memmap.c D src/soc/intel/icelake/cbmem.c M src/soc/intel/icelake/memmap.c M src/soc/intel/icelake/romstage/romstage.c M src/soc/intel/quark/memmap.c M src/soc/intel/quark/romstage/fsp2_0.c M src/soc/intel/skylake/memmap.c M src/soc/intel/skylake/romstage/romstage_fsp20.c M src/soc/mediatek/common/cbmem.c M src/soc/nvidia/tegra124/cbmem.c M src/soc/nvidia/tegra210/cbmem.c M src/soc/qualcomm/ipq40xx/cbmem.c M src/soc/qualcomm/ipq806x/cbmem.c M src/soc/qualcomm/sdm845/cbmem.c M src/soc/rockchip/common/cbmem.c M src/soc/samsung/exynos5250/cbmem.c M src/soc/samsung/exynos5420/cbmem.c M src/soc/sifive/fu540/cbmem.c M src/soc/ucb/riscv/cbmem.c 67 files changed, 133 insertions(+), 176 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/30693/1 diff --git a/src/arch/x86/cbmem.c b/src/arch/x86/cbmem.c index 73967e1..bb3c1ef 100644 --- a/src/arch/x86/cbmem.c +++ b/src/arch/x86/cbmem.c @@ -17,16 +17,16 @@ #if IS_ENABLED(CONFIG_CBMEM_TOP_BACKUP) -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - static void *cbmem_top_backup; - void *top_backup; + static uintptr_t cbmem_top_backup; + uintptr_t top_backup; if (ENV_RAMSTAGE && cbmem_top_backup != NULL) return cbmem_top_backup; /* Top of CBMEM is at highest usable DRAM address below 4GiB. */ - top_backup = (void *)restore_top_of_low_cacheable(); + top_backup = restore_top_of_low_cacheable(); if (ENV_RAMSTAGE) cbmem_top_backup = top_backup; diff --git a/src/cpu/allwinner/a10/cbmem.c b/src/cpu/allwinner/a10/cbmem.c index a4c563a3..42331a6 100644 --- a/src/cpu/allwinner/a10/cbmem.c +++ b/src/cpu/allwinner/a10/cbmem.c @@ -20,7 +20,7 @@ #include "ram_segs.h" #include <cbmem.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { return a1x_get_cbmem_top(); } diff --git a/src/cpu/allwinner/a10/ram_segs.h b/src/cpu/allwinner/a10/ram_segs.h index fa915cd..4b4f0e5 100644 --- a/src/cpu/allwinner/a10/ram_segs.h +++ b/src/cpu/allwinner/a10/ram_segs.h @@ -22,21 +22,21 @@ /* * Put CBMEM at top of RAM */ -static inline void *a1x_get_cbmem_top(void) +static inline uintptr_t a1x_get_cbmem_top(void) { - return _dram + (CONFIG_DRAM_SIZE_MB << 20); + return (uintptr_t)_dram + (CONFIG_DRAM_SIZE_MB << 20); } /* * By CBFS cache, we mean a cached copy, in RAM, of the entire CBFS region. */ -static inline void *a1x_get_cbfs_cache_top(void) +static inline uintptr_t a1x_get_cbfs_cache_top(void) { /* Arbitrary 16 MiB gap for cbmem tables and bouncebuffer */ return a1x_get_cbmem_top() - (16 << 20); } -static inline void *a1x_get_cbfs_cache_base(void) +static inline uintptr_t a1x_get_cbfs_cache_base(void) { return a1x_get_cbfs_cache_top() - CONFIG_ROM_SIZE; } diff --git a/src/cpu/amd/family_10h-family_15h/ram_calc.c b/src/cpu/amd/family_10h-family_15h/ram_calc.c index 57bd2fc..7d62064 100644 --- a/src/cpu/amd/family_10h-family_15h/ram_calc.c +++ b/src/cpu/amd/family_10h-family_15h/ram_calc.c @@ -89,9 +89,9 @@ return cc6_size; } -void *cbmem_top(void) +uintptr_t cbmem_top(void) { uint32_t topmem = rdmsr(TOP_MEM).lo; - return (void *) topmem - get_uma_memory_size(topmem) - get_cc6_memory_size(); + return topmem - get_uma_memory_size(topmem) - get_cc6_memory_size(); } diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 688f357..8d39892 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -65,7 +65,7 @@ * above top of the ram. This satisfies MTRR alignment requirement * with different TSEG size configurations. */ - top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); + top_of_ram = ALIGN_DOWN(cbmem_top(), 8*MiB); postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 16*MiB, MTRR_TYPE_WRBACK); diff --git a/src/cpu/intel/haswell/stage_cache.c b/src/cpu/intel/haswell/stage_cache.c index 009cc09..82cb95d 100644 --- a/src/cpu/intel/haswell/stage_cache.c +++ b/src/cpu/intel/haswell/stage_cache.c @@ -22,5 +22,5 @@ /* The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. * The top of RAM is defined to be the TSEG base address. */ *size = RESERVED_SMM_SIZE; - *base = (void *)((uint32_t)cbmem_top() + RESERVED_SMM_OFFSET); + *base = (void *)(cbmem_top() + RESERVED_SMM_OFFSET); } diff --git a/src/cpu/intel/model_206ax/stage_cache.c b/src/cpu/intel/model_206ax/stage_cache.c index 26dc5e0..4dcd6b4 100644 --- a/src/cpu/intel/model_206ax/stage_cache.c +++ b/src/cpu/intel/model_206ax/stage_cache.c @@ -24,5 +24,5 @@ * The top of RAM is defined to be the TSEG base address. */ *size = RESERVED_SMM_SIZE; - *base = (void *)((uintptr_t)cbmem_top() + RESERVED_SMM_OFFSET); + *base = (void *)(cbmem_top() + RESERVED_SMM_OFFSET); } diff --git a/src/cpu/ti/am335x/cbmem.c b/src/cpu/ti/am335x/cbmem.c index a626ec6..116d82d 100644 --- a/src/cpu/ti/am335x/cbmem.c +++ b/src/cpu/ti/am335x/cbmem.c @@ -15,7 +15,7 @@ #include <cbmem.h> #include <symbols.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return _dram + (CONFIG_DRAM_SIZE_MB << 20); + return (uintptr_t)_dram + (CONFIG_DRAM_SIZE_MB << 20); } diff --git a/src/drivers/amd/agesa/mtrr_fixme.c b/src/drivers/amd/agesa/mtrr_fixme.c index 1fbb553..49db504 100644 --- a/src/drivers/amd/agesa/mtrr_fixme.c +++ b/src/drivers/amd/agesa/mtrr_fixme.c @@ -56,7 +56,7 @@ * writeback possible. */ - uintptr_t top_of_ram = (uintptr_t) cbmem_top(); + uintptr_t top_of_ram = cbmem_top(); top_of_ram = ALIGN_UP(top_of_ram, 4 * MiB); set_range_uc(top_of_ram - 4 * MiB, 4 * MiB); @@ -89,7 +89,7 @@ * speed make them WB after CAR teardown. */ if (s3resume) { - uintptr_t top_of_ram = (uintptr_t) cbmem_top(); + uintptr_t top_of_ram = cbmem_top(); top_of_ram = ALIGN_DOWN(top_of_ram, 4*MiB); postcar_frame_add_mtrr(pcf, top_of_ram - 4*MiB, 4*MiB, diff --git a/src/drivers/intel/fsp1_0/fsp_util.c b/src/drivers/intel/fsp1_0/fsp_util.c index 71f6416..e0dfddb 100644 --- a/src/drivers/intel/fsp1_0/fsp_util.c +++ b/src/drivers/intel/fsp1_0/fsp_util.c @@ -199,7 +199,7 @@ * @param hob_list_ptr pointer to the start of the hob list * @return pointer to the start of the FSP reserved memory or NULL if not found. */ -void *find_fsp_reserved_mem(void *hob_list_ptr) +uintptr_t find_fsp_reserved_mem(void *hob_list_ptr) { EFI_GUID fsp_reserved_guid = FSP_HOB_RESOURCE_OWNER_FSP_GUID; EFI_HOB_RESOURCE_DESCRIPTOR *fsp_reserved_mem = @@ -209,7 +209,7 @@ if (fsp_reserved_mem == NULL) return NULL; - return (void *)((uintptr_t)fsp_reserved_mem->PhysicalStart); + return ((uintptr_t)fsp_reserved_mem->PhysicalStart); } #endif /* FSP_RESERVE_MEMORY_SIZE */ diff --git a/src/drivers/intel/fsp2_0/hob_verify.c b/src/drivers/intel/fsp2_0/hob_verify.c index 317b2c9..a3c878e 100644 --- a/src/drivers/intel/fsp2_0/hob_verify.c +++ b/src/drivers/intel/fsp2_0/hob_verify.c @@ -61,7 +61,7 @@ die("Space between FSP reserved region and BIOS TOLUM!\n"); } - if (range_entry_end(&tolum) != (uintptr_t)cbmem_top()) { + if (range_entry_end(&tolum) != cbmem_top()) { printk(BIOS_CRIT, "TOLUM end: 0x%08llx != 0x%p: cbmem_top\n", range_entry_end(&tolum), cbmem_top()); die("Space between cbmem_top and BIOS TOLUM!\n"); diff --git a/src/include/cbmem.h b/src/include/cbmem.h index ad48e35..e7f04cc 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -74,7 +74,7 @@ * below 4GiB. * x86 boards or chipsets must return NULL before the cbmem backing store has * been initialized. */ -void *cbmem_top(void); +uintptr_t cbmem_top(void); /* Add a cbmem entry of a given size and id. These return NULL on failure. The * add function performs a find first and do not check against the original diff --git a/src/include/imd.h b/src/include/imd.h index 6575312..cd2d297 100644 --- a/src/include/imd.h +++ b/src/include/imd.h @@ -59,7 +59,7 @@ * to be called at least once before any other imd related functions * can be used. */ -void imd_handle_init(struct imd *imd, void *upper_limit); +void imd_handle_init(struct imd *imd, uintptr_t upper_limit); /* * Initialize a handle with a shallow recovery. This function doesn't diff --git a/src/lib/ext_stage_cache.c b/src/lib/ext_stage_cache.c index c3d4aee..f353681 100644 --- a/src/lib/ext_stage_cache.c +++ b/src/lib/ext_stage_cache.c @@ -32,12 +32,12 @@ static void stage_cache_create_empty(void) { struct imd *imd; - void *base; + uintptr_t base; size_t size; imd = imd_get(); stage_cache_external_region(&base, &size); - imd_handle_init(imd, (void *)(size + (uintptr_t)base)); + imd_handle_init(imd, size + base); printk(BIOS_DEBUG, "External stage cache:\n"); imd_create_tiered_empty(imd, 4096, 4096, 1024, 32); @@ -48,12 +48,12 @@ static void stage_cache_recover(void) { struct imd *imd; - void *base; + uintptr_t base; size_t size; imd = imd_get(); stage_cache_external_region(&base, &size); - imd_handle_init(imd, (void *)(size + (uintptr_t)base)); + imd_handle_init(imd, size + base); if (imd_recover(imd)) printk(BIOS_DEBUG, "Unable to recover external stage cache.\n"); } diff --git a/src/lib/imd.c b/src/lib/imd.c index 17ec2d9..143f617 100644 --- a/src/lib/imd.c +++ b/src/lib/imd.c @@ -132,11 +132,10 @@ e->id = id; } -static void imdr_init(struct imdr *ir, void *upper_limit) +static void imdr_init(struct imdr *ir, uintptr_t upper_limit) { - uintptr_t limit = (uintptr_t)upper_limit; /* Upper limit is aligned down to 4KiB */ - ir->limit = ALIGN_DOWN(limit, LIMIT_ALIGN); + ir->limit = ALIGN_DOWN(upper_limit, LIMIT_ALIGN); ir->r = NULL; } @@ -396,10 +395,10 @@ } /* Initialize imd handle. */ -void imd_handle_init(struct imd *imd, void *upper_limit) +void imd_handle_init(struct imd *imd, uintptr_t upper_limit) { imdr_init(&imd->lg, upper_limit); - imdr_init(&imd->sm, NULL); + imdr_init(&imd->sm, 0); } void imd_handle_init_partial_recovery(struct imd *imd) @@ -411,7 +410,7 @@ if (imd->lg.limit == 0) return; - imd_handle_init(imd, (void *)imd->lg.limit); + imd_handle_init(imd, imd->lg.limit); /* Initialize root pointer for the large regions. */ imdr = &imd->lg; @@ -468,7 +467,7 @@ return 0; fail: - imd_handle_init(imd, (void *)imdr->limit); + imd_handle_init(imd, imdr->limit); return -1; } @@ -495,7 +494,7 @@ /* Tear down any changes on failure. */ if (imdr_recover(&imd->sm) != 0) { - imd_handle_init(imd, (void *)imd->lg.limit); + imd_handle_init(imd, imd->lg.limit); return -1; } diff --git a/src/mainboard/emulation/qemu-armv7/cbmem.c b/src/mainboard/emulation/qemu-armv7/cbmem.c index f26ca6c..6c3ac57 100644 --- a/src/mainboard/emulation/qemu-armv7/cbmem.c +++ b/src/mainboard/emulation/qemu-armv7/cbmem.c @@ -59,7 +59,7 @@ return discovered; } -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return _dram + (probe_ramsize() << 20); + return (uintptr_t)_dram + (probe_ramsize() << 20); } diff --git a/src/mainboard/emulation/qemu-i440fx/memory.c b/src/mainboard/emulation/qemu-i440fx/memory.c index dea96f2..973eecd 100644 --- a/src/mainboard/emulation/qemu-i440fx/memory.c +++ b/src/mainboard/emulation/qemu-i440fx/memory.c @@ -50,7 +50,7 @@ return tomk; } -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return (void *) (qemu_get_memory_size() * 1024); + return qemu_get_memory_size() * 1024; } diff --git a/src/mainboard/emulation/qemu-power8/cbmem.c b/src/mainboard/emulation/qemu-power8/cbmem.c index 3df6b80..4391cdb 100644 --- a/src/mainboard/emulation/qemu-power8/cbmem.c +++ b/src/mainboard/emulation/qemu-power8/cbmem.c @@ -15,10 +15,9 @@ #include <cbmem.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { /* Top of cbmem is at lowest usable DRAM address below 4GiB. */ /* For now, last 1M of 4G */ - void *ptr = (void *) ((1ULL << 32) - 1048576); - return ptr; + return (1ULL << 32) - 1048576; } diff --git a/src/northbridge/intel/e7505/memmap.c b/src/northbridge/intel/e7505/memmap.c index 1b86012..f16cf9a 100644 --- a/src/northbridge/intel/e7505/memmap.c +++ b/src/northbridge/intel/e7505/memmap.c @@ -23,7 +23,7 @@ #include <program_loading.h> #include "e7505.h" -void *cbmem_top(void) +uintptr_t cbmem_top(void) { pci_devfn_t mch = PCI_DEV(0, 0, 0); uintptr_t tolm; @@ -32,7 +32,7 @@ tolm = pci_read_config16(mch, TOLM) >> 11; tolm <<= 27; - return (void *)tolm; + return tolm; } #define ROMSTAGE_RAM_STACK_SIZE 0x5000 @@ -59,7 +59,7 @@ postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); /* Cache CBMEM region as WB. */ - top_of_ram = (uintptr_t)cbmem_top(); + top_of_ram = cbmem_top(); postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); diff --git a/src/northbridge/intel/fsp_rangeley/raminit.c b/src/northbridge/intel/fsp_rangeley/raminit.c index 675a6f4..771d331 100644 --- a/src/northbridge/intel/fsp_rangeley/raminit.c +++ b/src/northbridge/intel/fsp_rangeley/raminit.c @@ -37,7 +37,7 @@ return tom; } -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return (void *) (smm_region_start() - FSP_RESERVE_MEMORY_SIZE); + return smm_region_start() - FSP_RESERVE_MEMORY_SIZE; } diff --git a/src/northbridge/intel/gm45/ram_calc.c b/src/northbridge/intel/gm45/ram_calc.c index af1a46d..1bb2031 100644 --- a/src/northbridge/intel/gm45/ram_calc.c +++ b/src/northbridge/intel/gm45/ram_calc.c @@ -117,10 +117,10 @@ * 1 MiB alignment. As this may cause very greedy MTRR setup, push * CBMEM top downwards to 4 MiB boundary. */ -void *cbmem_top(void) +uintptr_t cbmem_top(void) { uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB); - return (void *) top_of_ram; + return top_of_ram; } #define ROMSTAGE_RAM_STACK_SIZE 0x5000 @@ -145,7 +145,7 @@ /* Cache 8 MiB region below the top of ram and 2 MiB above top of * ram to cover both cbmem as the TSEG region. */ - top_of_ram = (uintptr_t)cbmem_top(); + top_of_ram = cbmem_top(); postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); postcar_frame_add_mtrr(&pcf, northbridge_get_tseg_base(), diff --git a/src/northbridge/intel/haswell/ram_calc.c b/src/northbridge/intel/haswell/ram_calc.c index d3e88f2..2c8217e 100644 --- a/src/northbridge/intel/haswell/ram_calc.c +++ b/src/northbridge/intel/haswell/ram_calc.c @@ -30,7 +30,7 @@ return tom & ~((1 << 20) - 1); } -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return (void *)smm_region_start(); + return smm_region_start(); } diff --git a/src/northbridge/intel/i440bx/ram_calc.c b/src/northbridge/intel/i440bx/ram_calc.c index 3362d93..1c09857 100644 --- a/src/northbridge/intel/i440bx/ram_calc.c +++ b/src/northbridge/intel/i440bx/ram_calc.c @@ -24,7 +24,7 @@ #include <program_loading.h> #include "i440bx.h" -void *cbmem_top(void) +uintptr_t cbmem_top(void) { /* Base of TSEG is top of usable DRAM */ /* @@ -64,7 +64,7 @@ int tseg_size = 128 * KiB * (1 << (tseg >> 1)); tom -= tseg_size; } - return (void *)tom; + return tom; } #define ROMSTAGE_RAM_STACK_SIZE 0x5000 @@ -88,7 +88,7 @@ postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); /* Cache CBMEM region as WB. */ - top_of_ram = (uintptr_t)cbmem_top(); + top_of_ram = cbmem_top(); postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); diff --git a/src/northbridge/intel/i945/ram_calc.c b/src/northbridge/intel/i945/ram_calc.c index fd37aea..b58b3c6 100644 --- a/src/northbridge/intel/i945/ram_calc.c +++ b/src/northbridge/intel/i945/ram_calc.c @@ -70,10 +70,10 @@ * 1 MiB alignment. As this may cause very greedy MTRR setup, push * CBMEM top downwards to 4 MiB boundary. */ -void *cbmem_top(void) +uintptr_t cbmem_top(void) { uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB); - return (void *) top_of_ram; + return top_of_ram; } /** Decodes used Graphics Mode Select (GMS) to kilobytes. */ @@ -110,7 +110,7 @@ /* Cache 8 MiB region below the top of ram and 2 MiB above top of * ram to cover both cbmem as the TSEG region. */ - top_of_ram = (uintptr_t)cbmem_top(); + top_of_ram = cbmem_top(); postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); postcar_frame_add_mtrr(&pcf, northbridge_get_tseg_base(), diff --git a/src/northbridge/intel/nehalem/ram_calc.c b/src/northbridge/intel/nehalem/ram_calc.c index baf087e..d80ba07 100644 --- a/src/northbridge/intel/nehalem/ram_calc.c +++ b/src/northbridge/intel/nehalem/ram_calc.c @@ -32,9 +32,9 @@ return tom; } -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return (void *) smm_region_start(); + return smm_region_start(); } #define ROMSTAGE_RAM_STACK_SIZE 0x5000 @@ -60,7 +60,7 @@ * above top of the ram. This satisfies MTRR alignment requirement * with different TSEG size configurations. */ - top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); + top_of_ram = ALIGN_DOWN(cbmem_top(), 8*MiB); postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); postcar_frame_add_mtrr(&pcf, top_of_ram, 8*MiB, MTRR_TYPE_WRBACK); diff --git a/src/northbridge/intel/pineview/ram_calc.c b/src/northbridge/intel/pineview/ram_calc.c index 21b926b..bfdfd60 100644 --- a/src/northbridge/intel/pineview/ram_calc.c +++ b/src/northbridge/intel/pineview/ram_calc.c @@ -130,10 +130,10 @@ * 1 MiB alignment. As this may cause very greedy MTRR setup, push * CBMEM top downwards to 4 MiB boundary. */ -void *cbmem_top(void) +uintptr_t cbmem_top(void) { uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB); - return (void *) top_of_ram; + return top_of_ram; } @@ -159,7 +159,7 @@ /* Cache 8 MiB region below the top of ram and 2 MiB above top of * ram to cover both cbmem as the TSEG region. */ - top_of_ram = (uintptr_t)cbmem_top(); + top_of_ram = cbmem_top(); postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); postcar_frame_add_mtrr(&pcf, northbridge_get_tseg_base(), diff --git a/src/northbridge/intel/sandybridge/ram_calc.c b/src/northbridge/intel/sandybridge/ram_calc.c index 00e3e78..4fc4407 100644 --- a/src/northbridge/intel/sandybridge/ram_calc.c +++ b/src/northbridge/intel/sandybridge/ram_calc.c @@ -38,9 +38,9 @@ return tom; } -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return (void *) smm_region_start(); + return smm_region_start(); } #define ROMSTAGE_RAM_STACK_SIZE 0x5000 @@ -62,7 +62,7 @@ /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); - top_of_ram = (uintptr_t)cbmem_top(); + top_of_ram = cbmem_top(); /* Cache 8MiB below the top of ram. On sandybridge systems the top of * ram under 4GiB is the start of the TSEG region. It is required to * be 8MiB aligned. Set this area as cacheable so it can be used later diff --git a/src/northbridge/intel/x4x/ram_calc.c b/src/northbridge/intel/x4x/ram_calc.c index 6484326..6537427 100644 --- a/src/northbridge/intel/x4x/ram_calc.c +++ b/src/northbridge/intel/x4x/ram_calc.c @@ -128,10 +128,10 @@ * 1 MiB alignment. As this may cause very greedy MTRR setup, push * CBMEM top downwards to 4 MiB boundary. */ -void *cbmem_top(void) +uintptr_t cbmem_top(void) { uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB); - return (void *) top_of_ram; + return top_of_ram; } #define ROMSTAGE_RAM_STACK_SIZE 0x5000 @@ -156,7 +156,7 @@ /* Cache 8 MiB region below the top of ram and 2 MiB above top of * ram to cover both cbmem as the TSEG region. */ - top_of_ram = (uintptr_t)cbmem_top(); + top_of_ram = cbmem_top(); postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); postcar_frame_add_mtrr(&pcf, northbridge_get_tseg_base(), diff --git a/src/northbridge/via/vx900/memmap.c b/src/northbridge/via/vx900/memmap.c index 8cc7607..e255265 100644 --- a/src/northbridge/via/vx900/memmap.c +++ b/src/northbridge/via/vx900/memmap.c @@ -113,7 +113,7 @@ return (pci_read_config16(MCU, 0x84) & 0xfff0) >> 4; } -void *cbmem_top(void) +uintptr_t cbmem_top(void) { uintptr_t tolm; uintptr_t fb_size; @@ -122,7 +122,7 @@ fb_size = vx900_get_chrome9hd_fb_size (); if (tolm > 0xfc0 || tolm <= 0x3ff || fb_size == 0x0) - return NULL; + return 0; - return (void *)((tolm - fb_size) << 20); + return ((tolm - fb_size) << 20); } diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index 4a856a9..8172a76 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -398,7 +398,7 @@ { uint64_t uma_base = get_uma_base(); uint32_t uma_size = get_uma_size(); - uint32_t mem_useable = (uintptr_t)cbmem_top(); + uint32_t mem_useable = cbmem_top(); msr_t tom = rdmsr(TOP_MEM); msr_t high_tom = rdmsr(TOP_MEM2); uint64_t high_mem_useable; diff --git a/src/soc/amd/stoneyridge/ramtop.c b/src/soc/amd/stoneyridge/ramtop.c index 15968ab..4302811 100644 --- a/src/soc/amd/stoneyridge/ramtop.c +++ b/src/soc/amd/stoneyridge/ramtop.c @@ -57,7 +57,7 @@ *size = BERT_REGION_MAX_SIZE; } -void *cbmem_top(void) +uintptr_t cbmem_top(void) { msr_t tom = rdmsr(TOP_MEM); @@ -65,14 +65,14 @@ return 0; /* 8MB alignment to keep MTRR usage low */ - return (void *)ALIGN_DOWN(restore_top_of_low_cacheable() + return ALIGN_DOWN(restore_top_of_low_cacheable() - CONFIG_SMM_TSEG_SIZE - BERT_REGION_MAX_SIZE, 8*MiB); } static uintptr_t smm_region_start(void) { - return (uintptr_t)cbmem_top() + BERT_REGION_MAX_SIZE; + return cbmem_top() + BERT_REGION_MAX_SIZE; } static size_t smm_region_size(void) diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index 9f8aed8..35a9ba9 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -160,7 +160,7 @@ * location of ramstage in cbmem is not known. Instruct postcar to cache * 16 megs under cbmem top which is a safe bet to cover ramstage. */ - top_of_ram = (uintptr_t) cbmem_top(); + top_of_ram = cbmem_top(); postcar_frame_add_mtrr(&pcf, top_of_ram - 16*MiB, 16*MiB, MTRR_TYPE_WRBACK); diff --git a/src/soc/cavium/cn81xx/cbmem.c b/src/soc/cavium/cn81xx/cbmem.c index 397fd26..a44ad5c 100644 --- a/src/soc/cavium/cn81xx/cbmem.c +++ b/src/soc/cavium/cn81xx/cbmem.c @@ -19,9 +19,9 @@ #include <stdlib.h> #include <symbols.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { /* Make sure not to overlap with reserved ATF scratchpad */ - return (void *)min((uintptr_t)_dram + (sdram_size_mb() - 1) * MiB, + return min((uintptr_t)_dram + (sdram_size_mb() - 1) * MiB, 4ULL * GiB); } diff --git a/src/soc/imgtec/pistachio/cbmem.c b/src/soc/imgtec/pistachio/cbmem.c index 112df7c..af76722 100644 --- a/src/soc/imgtec/pistachio/cbmem.c +++ b/src/soc/imgtec/pistachio/cbmem.c @@ -18,7 +18,7 @@ #include <stdlib.h> #include <symbols.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return _dram + (CONFIG_DRAM_SIZE_MB << 20); + return (uintptr_t)_dram + (CONFIG_DRAM_SIZE_MB << 20); } diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c index be15e16..4f7a9e8 100644 --- a/src/soc/intel/apollolake/memmap.c +++ b/src/soc/intel/apollolake/memmap.c @@ -25,11 +25,11 @@ #include <soc/systemagent.h> #include <soc/pci_devs.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { const struct device *dev; const config_t *config; - void *tolum = (void *)sa_get_tseg_base(); + uintptr_t tolum = sa_get_tseg_base(); if (!IS_ENABLED(CONFIG_SOC_INTEL_GLK)) return tolum; diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 4f4f9f5..9db1c99 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -252,7 +252,7 @@ * location of ramstage in cbmem is not known. Instruct postcar to cache * 16 megs under cbmem top which is a safe bet to cover ramstage. */ - top_of_ram = (uintptr_t) cbmem_top(); + top_of_ram = cbmem_top(); /* cbmem_top() needs to be at least 16 MiB aligned */ assert(ALIGN_DOWN(top_of_ram, 16*MiB) == top_of_ram); postcar_frame_add_mtrr(&pcf, top_of_ram - 16*MiB, 16*MiB, diff --git a/src/soc/intel/baytrail/memmap.c b/src/soc/intel/baytrail/memmap.c index f1131f6..7d3a98b 100644 --- a/src/soc/intel/baytrail/memmap.c +++ b/src/soc/intel/baytrail/memmap.c @@ -23,7 +23,7 @@ return (iosf_bunit_read(BUNIT_SMRRL) << 20); } -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return (void *) smm_region_start(); + return smm_region_start(); } diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index a52d3b1..6596fdf 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -252,7 +252,7 @@ * above top of the ram. This satisfies MTRR alignment requirement * with different TSEG size configurations. */ - top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); + top_of_ram = ALIGN_DOWN(cbmem_top(), 8*MiB); postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 16*MiB, MTRR_TYPE_WRBACK); diff --git a/src/soc/intel/braswell/memmap.c b/src/soc/intel/braswell/memmap.c index d7c9952..03371b5 100644 --- a/src/soc/intel/braswell/memmap.c +++ b/src/soc/intel/braswell/memmap.c @@ -81,7 +81,7 @@ return 0; } -void *cbmem_top(void) +uintptr_t cbmem_top(void) { char *smm_base; size_t smm_size; @@ -115,5 +115,5 @@ */ smm_region((void **)&smm_base, &smm_size); - return (void *)smm_base; + return smm_base; } diff --git a/src/soc/intel/broadwell/memmap.c b/src/soc/intel/broadwell/memmap.c index 175c20c..3166627 100644 --- a/src/soc/intel/broadwell/memmap.c +++ b/src/soc/intel/broadwell/memmap.c @@ -36,7 +36,7 @@ return tom; } -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return (void *) dpr_region_start(); + return dpr_region_start(); } diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index afc8216..bd3cdc4 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -56,7 +56,7 @@ * above top of the ram. This satisfies MTRR alignment requirement * with different TSEG size configurations. */ - top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); + top_of_ram = ALIGN_DOWN(cbmem_top(), 8*MiB); postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 16*MiB, MTRR_TYPE_WRBACK); diff --git a/src/soc/intel/cannonlake/cbmem.c b/src/soc/intel/cannonlake/cbmem.c deleted file mode 100644 index 300556a..0000000 --- a/src/soc/intel/cannonlake/cbmem.c +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2017 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <cbmem.h> - -void *cbmem_top(void) -{ - /* not implemented yet */ - return (void *) NULL; -} diff --git a/src/soc/intel/cannonlake/memmap.c b/src/soc/intel/cannonlake/memmap.c index 64e07be..c2caa93 100644 --- a/src/soc/intel/cannonlake/memmap.c +++ b/src/soc/intel/cannonlake/memmap.c @@ -294,7 +294,7 @@ * | | * +-------------------------+ */ -void *cbmem_top(void) +uintptr_t cbmem_top(void) { struct ebda_config ebda_cfg; @@ -309,5 +309,5 @@ retrieve_ebda_object(&ebda_cfg); - return (void *)(uintptr_t)ebda_cfg.tolum_base; + return (uintptr_t)ebda_cfg.tolum_base; } diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c index 246e0ea..33bc256 100644 --- a/src/soc/intel/cannonlake/romstage/romstage.c +++ b/src/soc/intel/cannonlake/romstage/romstage.c @@ -136,7 +136,7 @@ * Instruct postcar to cache 16 megs under cbmem top which is * a safe bet to cover ramstage. */ - top_of_ram = (uintptr_t) cbmem_top(); + top_of_ram = cbmem_top(); printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); top_of_ram -= 16*MiB; postcar_frame_add_mtrr(&pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 9608359..0d55357 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -157,7 +157,7 @@ /* Get SoC reserve memory size as per user selection */ reserved_mmio_size = soc_reserved_mmio_size(); - top_of_ram = (uintptr_t)cbmem_top(); + top_of_ram = cbmem_top(); /* 0 - > 0xa0000 */ base_k = 0; diff --git a/src/soc/intel/denverton_ns/memmap.c b/src/soc/intel/denverton_ns/memmap.c index a42d861..6c38f30 100644 --- a/src/soc/intel/denverton_ns/memmap.c +++ b/src/soc/intel/denverton_ns/memmap.c @@ -59,7 +59,10 @@ power_of_2(iqat_region_size + tseg_region_size); } -void *cbmem_top(void) { return (void *)top_of_32bit_ram(); } +uintptr_t cbmem_top(void) +{ + return top_of_32bit_ram(); +} static inline uintptr_t smm_region_start(void) { diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c index 34fd7bb..f19505e 100644 --- a/src/soc/intel/denverton_ns/romstage.c +++ b/src/soc/intel/denverton_ns/romstage.c @@ -166,7 +166,7 @@ * location of ramstage in cbmem is not known. Instruct postcar to cache * 16 megs under cbmem top which is a safe bet to cover ramstage. */ - top_of_ram = (uintptr_t)cbmem_top(); + top_of_ram = cbmem_top(); postcar_frame_add_mtrr(&pcf, top_of_ram - 16 * MiB, 16 * MiB, MTRR_TYPE_WRBACK); diff --git a/src/soc/intel/fsp_baytrail/memmap.c b/src/soc/intel/fsp_baytrail/memmap.c index 1886c6f..ff9ce5d 100644 --- a/src/soc/intel/fsp_baytrail/memmap.c +++ b/src/soc/intel/fsp_baytrail/memmap.c @@ -35,7 +35,7 @@ * @return pointer to the first byte of reserved memory */ -void *cbmem_top(void) +uintptr_t cbmem_top(void) { return find_fsp_reserved_mem(*(void **)CBMEM_FSP_HOB_PTR); } diff --git a/src/soc/intel/fsp_broadwell_de/memmap.c b/src/soc/intel/fsp_broadwell_de/memmap.c index 7510094..8ec6d99 100644 --- a/src/soc/intel/fsp_broadwell_de/memmap.c +++ b/src/soc/intel/fsp_broadwell_de/memmap.c @@ -17,7 +17,7 @@ #include <cbmem.h> #include <drivers/intel/fsp1_0/fsp_util.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { return find_fsp_reserved_mem(*(void **)CBMEM_FSP_HOB_PTR); } diff --git a/src/soc/intel/icelake/cbmem.c b/src/soc/intel/icelake/cbmem.c deleted file mode 100644 index 4f44777..0000000 --- a/src/soc/intel/icelake/cbmem.c +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <cbmem.h> - -void *cbmem_top(void) -{ - /* not implemented yet */ - return (void *) NULL; -} diff --git a/src/soc/intel/icelake/memmap.c b/src/soc/intel/icelake/memmap.c index 027b8b0..8e1d4d6 100644 --- a/src/soc/intel/icelake/memmap.c +++ b/src/soc/intel/icelake/memmap.c @@ -293,7 +293,7 @@ * | | * +-------------------------+ */ -void *cbmem_top(void) +uintptr_t cbmem_top(void) { struct ebda_config ebda_cfg; @@ -308,5 +308,5 @@ retrieve_ebda_object(&ebda_cfg); - return (void *)(uintptr_t)ebda_cfg.tolum_base; + return ebda_cfg.tolum_base; } diff --git a/src/soc/intel/icelake/romstage/romstage.c b/src/soc/intel/icelake/romstage/romstage.c index 432cae5..9968b3d 100644 --- a/src/soc/intel/icelake/romstage/romstage.c +++ b/src/soc/intel/icelake/romstage/romstage.c @@ -136,7 +136,7 @@ * Instruct postcar to cache 16 megs under cbmem top which is * a safe bet to cover ramstage. */ - top_of_ram = (uintptr_t) cbmem_top(); + top_of_ram = cbmem_top(); printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); top_of_ram -= 16*MiB; postcar_frame_add_mtrr(&pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); diff --git a/src/soc/intel/quark/memmap.c b/src/soc/intel/quark/memmap.c index d67856c..9a2706d 100644 --- a/src/soc/intel/quark/memmap.c +++ b/src/soc/intel/quark/memmap.c @@ -16,7 +16,7 @@ #include <cbmem.h> #include <soc/reg_access.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { uint32_t top_of_memory; @@ -30,5 +30,5 @@ top_of_memory -= 0x10000; /* Return the top of memory */ - return (void *)top_of_memory; + return top_of_memory; } diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c index 23051bd..52962be 100644 --- a/src/soc/intel/quark/romstage/fsp2_0.c +++ b/src/soc/intel/quark/romstage/fsp2_0.c @@ -65,7 +65,7 @@ die("Unable to initialize postcar frame.\n"); /* Locate the top of RAM */ - top_of_low_usable_memory = (uintptr_t) cbmem_top(); + top_of_low_usable_memory = cbmem_top(); top_of_ram = ALIGN(top_of_low_usable_memory, 16 * MiB); /* Cache postcar and ramstage */ diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c index f0ccb1d..e464bdc 100644 --- a/src/soc/intel/skylake/memmap.c +++ b/src/soc/intel/skylake/memmap.c @@ -335,7 +335,7 @@ * | | * +-------------------------+ */ -void *cbmem_top(void) +uintptr_t cbmem_top(void) { struct ebda_config ebda_cfg; @@ -350,5 +350,5 @@ retrieve_ebda_object(&ebda_cfg); - return (void *)(uintptr_t)ebda_cfg.tolum_base; + return ebda_cfg.tolum_base; } diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index 2a60158..5030eb8 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -161,7 +161,7 @@ * Instruct postcar to cache 16 megs under cbmem top which is * a safe bet to cover ramstage. */ - top_of_ram = (uintptr_t) cbmem_top(); + top_of_ram = cbmem_top(); printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); top_of_ram -= 16*MiB; postcar_frame_add_mtrr(&pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); diff --git a/src/soc/mediatek/common/cbmem.c b/src/soc/mediatek/common/cbmem.c index 8906565..7d0aad6 100644 --- a/src/soc/mediatek/common/cbmem.c +++ b/src/soc/mediatek/common/cbmem.c @@ -21,7 +21,7 @@ #define MAX_DRAM_ADDRESS ((uintptr_t)4 * GiB) -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return (void *)min((uintptr_t)_dram + sdram_size(), MAX_DRAM_ADDRESS); + return min((uintptr_t)_dram + sdram_size(), MAX_DRAM_ADDRESS); } diff --git a/src/soc/nvidia/tegra124/cbmem.c b/src/soc/nvidia/tegra124/cbmem.c index 4b52a51..d11816a 100644 --- a/src/soc/nvidia/tegra124/cbmem.c +++ b/src/soc/nvidia/tegra124/cbmem.c @@ -17,7 +17,7 @@ #include <soc/display.h> #include <soc/sdram.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return (void *)((sdram_max_addressable_mb() - FB_SIZE_MB) << 20UL); + return ((sdram_max_addressable_mb() - FB_SIZE_MB) << 20UL); } diff --git a/src/soc/nvidia/tegra210/cbmem.c b/src/soc/nvidia/tegra210/cbmem.c index 63ae497..21f8819 100644 --- a/src/soc/nvidia/tegra210/cbmem.c +++ b/src/soc/nvidia/tegra210/cbmem.c @@ -16,7 +16,7 @@ #include <cbmem.h> #include <soc/addressmap.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { static uintptr_t addr; @@ -32,5 +32,5 @@ addr = end_mib << 20; } - return (void *)addr; + return addr; } diff --git a/src/soc/qualcomm/ipq40xx/cbmem.c b/src/soc/qualcomm/ipq40xx/cbmem.c index 05325cc..db859e8 100644 --- a/src/soc/qualcomm/ipq40xx/cbmem.c +++ b/src/soc/qualcomm/ipq40xx/cbmem.c @@ -23,7 +23,7 @@ cbmem_backing_store_ready = 1; } -void *cbmem_top(void) +uintptr_t cbmem_top(void) { /* * In romstage, make sure that cbmem backing store is ready before @@ -34,5 +34,5 @@ if (ENV_ROMSTAGE && (cbmem_backing_store_ready == 0)) return NULL; - return _memlayout_cbmem_top; + return (uintptr_t)_memlayout_cbmem_top; } diff --git a/src/soc/qualcomm/ipq806x/cbmem.c b/src/soc/qualcomm/ipq806x/cbmem.c index 9674db6..d86b113 100644 --- a/src/soc/qualcomm/ipq806x/cbmem.c +++ b/src/soc/qualcomm/ipq806x/cbmem.c @@ -23,7 +23,7 @@ cbmem_backing_store_ready = 1; } -void *cbmem_top(void) +uintptr_t cbmem_top(void) { /* * In romstage, make sure that cbmem backing store is ready before @@ -35,5 +35,5 @@ if (ENV_ROMSTAGE && (cbmem_backing_store_ready == 0)) return NULL; - return _memlayout_cbmem_top; + return (uintptr_t)_memlayout_cbmem_top; } diff --git a/src/soc/qualcomm/sdm845/cbmem.c b/src/soc/qualcomm/sdm845/cbmem.c index 3b9ad4a..5897f18 100644 --- a/src/soc/qualcomm/sdm845/cbmem.c +++ b/src/soc/qualcomm/sdm845/cbmem.c @@ -15,7 +15,7 @@ #include <cbmem.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return (void *)((uintptr_t)4 * GiB); + return ((uintptr_t)4 * GiB); } diff --git a/src/soc/rockchip/common/cbmem.c b/src/soc/rockchip/common/cbmem.c index 401f8b2..105e178 100644 --- a/src/soc/rockchip/common/cbmem.c +++ b/src/soc/rockchip/common/cbmem.c @@ -19,8 +19,8 @@ #include <stdlib.h> #include <symbols.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return (void *)min((uintptr_t)_dram + sdram_size_mb() * MiB, + return min((uintptr_t)_dram + sdram_size_mb() * MiB, MAX_DRAM_ADDRESS); } diff --git a/src/soc/samsung/exynos5250/cbmem.c b/src/soc/samsung/exynos5250/cbmem.c index 1874495..dc02577 100644 --- a/src/soc/samsung/exynos5250/cbmem.c +++ b/src/soc/samsung/exynos5250/cbmem.c @@ -17,7 +17,7 @@ #include <cbmem.h> #include <soc/cpu.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return (void *)(get_fb_base_kb() * KiB); + return get_fb_base_kb() * KiB; } diff --git a/src/soc/samsung/exynos5420/cbmem.c b/src/soc/samsung/exynos5420/cbmem.c index e1999e8..4606c19 100644 --- a/src/soc/samsung/exynos5420/cbmem.c +++ b/src/soc/samsung/exynos5420/cbmem.c @@ -17,7 +17,7 @@ #include <soc/cpu.h> #include <stddef.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return (void *)(get_fb_base_kb() * KiB); + return (get_fb_base_kb() * KiB); } diff --git a/src/soc/sifive/fu540/cbmem.c b/src/soc/sifive/fu540/cbmem.c index 1c68de8..523e62c 100644 --- a/src/soc/sifive/fu540/cbmem.c +++ b/src/soc/sifive/fu540/cbmem.c @@ -19,8 +19,8 @@ #include <stdlib.h> #include <symbols.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return (void *)min((uintptr_t)_dram + sdram_size_mb() * MiB, + return min((uintptr_t)_dram + sdram_size_mb() * MiB, FU540_MAXDRAM); } diff --git a/src/soc/ucb/riscv/cbmem.c b/src/soc/ucb/riscv/cbmem.c index 2ee400a..7e0c4d5 100644 --- a/src/soc/ucb/riscv/cbmem.c +++ b/src/soc/ucb/riscv/cbmem.c @@ -13,7 +13,7 @@ #include <cbmem.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { uintptr_t base; size_t size; @@ -23,5 +23,5 @@ base = 0x80000000; size = 128 * MiB; - return (void *)(base + size); + return (base + size); } -- To view, visit https://review.coreboot.org/c/coreboot/+/30693 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iecec1cffba9dba02d06b10fe88aec173dbc08093 Gerrit-Change-Number: 30693 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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coreboot-gerrit June 2023