coreboot-gerrit June 2023

coreboot-gerrit@coreboot.org

1 participants
5387 discussions

Change in coreboot[master]: xmb/google/volteer: Add BOOT_*_SUPPORT to FW_CONFIG
by Chen Wisley (Code Review) 10 Jun '23

10 Jun '23

Chen Wisley has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47733 ) Change subject: xmb/google/volteer: Add BOOT_*_SUPPORT to FW_CONFIG ...................................................................... xmb/google/volteer: Add BOOT_*_SUPPORT to FW_CONFIG bit 22 for BOOT_SUPPORT_NVME bit 23 for BOOT_SUPPORT_SATA bit 24 for BOOT_SUPPORT_EMMC: bit24 BUG=none BRANCH=volteer TEST=emerge-volteer coreboot Change-Id: I41a6c624c8e32a6115b496f523dbd7a7c3f038c4 Signed-off-by: Wisley Chen <wisley.chen(a)quantatw.com> --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/47733/1 diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 50be736..18d1f6b 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -38,6 +38,15 @@ option SD_GL9755S 1 option SD_RTS5261 2 end + field BOOT_NVME_MASK 22 + option BOOT_SUPPORT_NVME 1 + end + field BOOT_SATA_MASK 23 + option BOOT_SUPPORT_SATA 1 + end + field BOOT_EMMC_MASK 24 + option BOOT_SUPPORT_EMMC 1 + end end chip soc/intel/tigerlake -- To view, visit https://review.coreboot.org/c/coreboot/+/47733 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41a6c624c8e32a6115b496f523dbd7a7c3f038c4 Gerrit-Change-Number: 47733 Gerrit-PatchSet: 1 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: cpu/x86/sipi_vector: Properly use uintptr_t
by Patrick Rudolph (Code Review) 10 Jun '23

10 Jun '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47711 ) Change subject: cpu/x86/sipi_vector: Properly use uintptr_t ...................................................................... cpu/x86/sipi_vector: Properly use uintptr_t Change-Id: Ifc60e1efa6fe6a3029ef9e5e63ce50afa8c8c51c Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/cpu/x86/sipi_vector.S M src/include/cpu/x86/mp.h 2 files changed, 13 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/47711/1 diff --git a/src/cpu/x86/sipi_vector.S b/src/cpu/x86/sipi_vector.S index ad614ae..cb5641a 100644 --- a/src/cpu/x86/sipi_vector.S +++ b/src/cpu/x86/sipi_vector.S @@ -15,6 +15,11 @@ * C code. The C handler loads microcode, sets up MSRs, and enables caching * before calling into the MP init provided 'c_handler' */ +#if ENV_X86_64 +#define uintptr_t quad +#else +#define uintptr_t long +#endif .section ".module_parameters", "aw", @progbits ap_start_params: @@ -25,19 +30,19 @@ idt_ptr: .long 0 stack_top: -.long 0 +.uintptr_t 0 stack_size: .long 0 microcode_lock: .long 0 microcode_ptr: -.long 0 +.uintptr_t 0 msr_table_ptr: -.long 0 +.uintptr_t 0 msr_count: .long 0 c_handler: -.long 0 +.uintptr_t 0 ap_count: .long 0 diff --git a/src/include/cpu/x86/mp.h b/src/include/cpu/x86/mp.h index b55e2e7..ed6e91f 100644 --- a/src/include/cpu/x86/mp.h +++ b/src/include/cpu/x86/mp.h @@ -149,13 +149,13 @@ uint32_t gdt; uint16_t unused; uint32_t idt_ptr; - uint32_t stack_top; + uintptr_t stack_top; uint32_t stack_size; uint32_t microcode_lock; /* 0xffffffff means parallel loading. */ - uint32_t microcode_ptr; - uint32_t msr_table_ptr; + uintptr_t microcode_ptr; + uintptr_t msr_table_ptr; uint32_t msr_count; - uint32_t c_handler; + uintptr_t c_handler; atomic_t ap_count; } __packed; -- To view, visit https://review.coreboot.org/c/coreboot/+/47711 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifc60e1efa6fe6a3029ef9e5e63ce50afa8c8c51c Gerrit-Change-Number: 47711 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

4 3

[S] Change in coreboot[master]: soc/intel/common/block/cse: Modify heci_send_receive to support MCHI ...
by Stefan Reinauer (Code Review) 10 Jun '23

10 Jun '23

Stefan Reinauer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/46881?usp=email ) Change subject: soc/intel/common/block/cse: Modify heci_send_receive to support MCHI address ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/46881?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice6f6bb0069080b9ac75a5323475c002e03eb751 Gerrit-Change-Number: 46881 Gerrit-PatchSet: 6 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamirbohra(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik Vaghela <maulikvaghela(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

1 0

[S] Change in coreboot[master]: mb/google/dedede: Enable microcode update
by Stefan Reinauer (Code Review) 10 Jun '23

10 Jun '23

Stefan Reinauer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/47162?usp=email ) Change subject: mb/google/dedede: Enable microcode update ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/47162?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I956bc82bdb68049058335ff86c22742a235256c2 Gerrit-Change-Number: 47162 Gerrit-PatchSet: 5 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

1 0

[XS] Change in coreboot[master]: vendorcode/amd/cimx/sb800: Add parentheses
by Stefan Reinauer (Code Review) 10 Jun '23

10 Jun '23

Stefan Reinauer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/21018?usp=email ) Change subject: vendorcode/amd/cimx/sb800: Add parentheses ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/21018?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idfd5f784872a37794ee43c8ec0a936f7be68ad64 Gerrit-Change-Number: 21018 Gerrit-PatchSet: 2 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

1 0

Change in coreboot[master]: soc/intel/jasperlake: [TEST-ONLY] SPI read CAR test
by Aamir Bohra (Code Review) 10 Jun '23

10 Jun '23

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47788 ) Change subject: soc/intel/jasperlake: [TEST-ONLY] SPI read CAR test ...................................................................... soc/intel/jasperlake: [TEST-ONLY] SPI read CAR test Change-Id: I4813572a31240b2796cacfa97044f9ed091ec108 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/soc/intel/jasperlake/bootblock/bootblock.c 1 file changed, 29 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/47788/1 diff --git a/src/soc/intel/jasperlake/bootblock/bootblock.c b/src/soc/intel/jasperlake/bootblock/bootblock.c index 96e6268..a1254cf 100644 --- a/src/soc/intel/jasperlake/bootblock/bootblock.c +++ b/src/soc/intel/jasperlake/bootblock/bootblock.c @@ -1,10 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootblock_common.h> +#include <console/console.h> #include <intelblocks/systemagent.h> #include <intelblocks/tco.h> #include <intelblocks/uart.h> #include <soc/bootblock.h> +#include <string.h> + asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { @@ -22,6 +25,31 @@ uart_bootblock_init(); } +static void report_cache_info(void) +{ + struct cpuid_result res; + uintptr_t addr = 0xFF000000; + char buf[1024]; + uint32_t kbcount=0; + res = cpuid_ext(0x04, 0x03); + const size_t assoc = CPUID_CACHE_WAYS_OF_ASSOC(res) + 1; + const size_t partitions = CPUID_CACHE_PHYS_LINE(res) + 1; + const size_t cache_line_size = CPUID_CACHE_COHER_LINE(res) + 1; + const size_t number_of_sets = CPUID_CACHE_NO_OF_SETS(res) + 1; + const size_t cache_size = assoc * partitions * cache_line_size * number_of_sets; + printk(BIOS_INFO, "assoc=%zd par=%zd line_size=%zd sets=%zd\n", + assoc, partitions, cache_line_size, number_of_sets); + printk(BIOS_INFO, "@@ dedede cache_size 0x%lx bytes\n", cache_size); + + while (addr < 0xFFFF0000) { + memcpy(buf, (void *)addr, 1024); + printk(BIOS_ERR, "TEST : %lx %x KBcount : %d \n", addr, buf[0], kbcount); + addr += 1024; + ++kbcount; + } + +} + void bootblock_soc_init(void) { report_platform_info(); @@ -29,4 +57,5 @@ /* Programming TCO_BASE_ADDRESS and TCO Timer Halt */ tco_configure(); + report_cache_info(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/47788 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4813572a31240b2796cacfa97044f9ed091ec108 Gerrit-Change-Number: 47788 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: src/soc/intel/tigerlake: Get SPI-DMI destination Id
by Srinidhi N Kaushik (Code Review) 10 Jun '23

10 Jun '23

Srinidhi N Kaushik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48067 ) Change subject: src/soc/intel/tigerlake: Get SPI-DMI destination Id ...................................................................... src/soc/intel/tigerlake: Get SPI-DMI destination Id Add support to get SPI_DMI destination id. This change implements SOC function that rteruns SPI-DMI Destination id by calling soc_get_spi_dmi_destination_id(). BUG=b:171534504 Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Change-Id: Idf500f1ccf576bbb903bdb5e218263d3f1295ae8 --- M src/soc/intel/tigerlake/spi.c 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/48067/1 diff --git a/src/soc/intel/tigerlake/spi.c b/src/soc/intel/tigerlake/spi.c index 63d9d80..fa63713 100644 --- a/src/soc/intel/tigerlake/spi.c +++ b/src/soc/intel/tigerlake/spi.c @@ -7,7 +7,9 @@ */ #include <intelblocks/spi.h> +#include <intelblocks/fast_spi.h> #include <soc/pci_devs.h> +#include <soc/pcr_ids.h> int spi_soc_devfn_to_bus(unsigned int devfn) { @@ -23,3 +25,8 @@ } return -1; } + +uint32_t soc_get_spi_dmi_destination_id() +{ + return SPI_DMI_DESTINATION_ID; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/48067 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf500f1ccf576bbb903bdb5e218263d3f1295ae8 Gerrit-Change-Number: 48067 Gerrit-PatchSet: 1 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: configs: Add builder Kontron mAL-10 config
by Maxim Polyakov (Code Review) 10 Jun '23

10 Jun '23

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47886 ) Change subject: configs: Add builder Kontron mAL-10 config ...................................................................... configs: Add builder Kontron mAL-10 config Add config file that can be used to build the coreboot image for the Kontron mAL-10 module. Change-Id: I7144a49410d05783224760ebc1933011b22a108b Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- A configs/config.kontron_mal10 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/47886/1 diff --git a/configs/config.kontron_mal10 b/configs/config.kontron_mal10 new file mode 100644 index 0000000..fa9ecf1 --- /dev/null +++ b/configs/config.kontron_mal10 @@ -0,0 +1,7 @@ +CONFIG_VENDOR_KONTRON=y +CONFIG_FMDFILE="src/mainboard/kontron/mal10/mal10.fmd" +CONFIG_NEED_IFWI=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_BOARD_KONTRON_COME_MAL10=y +CONFIG_USE_LEGACY_8254_TIMER=y +CONFIG_PAYLOAD_NONE=y -- To view, visit https://review.coreboot.org/c/coreboot/+/47886 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7144a49410d05783224760ebc1933011b22a108b Gerrit-Change-Number: 47886 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: console,soc: print wr protect status
by Sridhar Siricilla (Code Review) 10 Jun '23

10 Jun '23

Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48342 ) Change subject: console,soc: print wr protect status ...................................................................... console,soc: print wr protect status Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I140fcee714ca550d403be1e0042e9f729f4417a5 --- M src/console/init.c M src/soc/intel/common/block/cse/cse_lite.c 2 files changed, 13 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/48342/1 diff --git a/src/console/init.c b/src/console/init.c index c598077..9cb467c 100644 --- a/src/console/init.c +++ b/src/console/init.c @@ -7,6 +7,8 @@ #include <device/pci.h> #include <option.h> #include <version.h> +#include <spi_flash.h> + #define FIRST_CONSOLE (ENV_BOOTBLOCK || (CONFIG(NO_BOOTBLOCK_CONSOLE) && ENV_ROMSTAGE)) diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index 8fd87b8..d77241a 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -10,6 +10,7 @@ #include <security/vboot/vboot_common.h> #include <security/vboot/misc.h> #include <soc/intel/common/reset.h> +#include <spi_flash.h> /* Converts bp index to boot partition string */ #define GET_BP_STR(bp_index) (bp_index ? "RW" : "RO") @@ -373,7 +374,12 @@ /* Set the CSE's next boot partition and issues system reset */ static bool cse_set_and_boot_from_next_bp(enum boot_partition_id bp) { - if (!cse_set_next_boot_partition(bp)) + { + u8 spi_sts; + spi_flash_status(boot_device_spi_flash(), &spi_sts); + printk(BIOS_DEBUG, "SPI_STATUS: 0x%x\n", spi_sts); + + if (!cse_set_next_boot_partition(bp)) return false; /* Allow the board to perform a reset for CSE RO<->RW jump */ @@ -775,6 +781,10 @@ { static struct get_bp_info_rsp cse_bp_info; + u8 spi_sts; + spi_flash_status(boot_device_spi_flash(), &spi_sts); + printk(BIOS_DEBUG, "SPI_STATUS: 0x%x\n", spi_sts); + if (vboot_recovery_mode_enabled()) { printk(BIOS_DEBUG, "cse_lite: Skip switching to RW in the recovery path\n"); return; -- To view, visit https://review.coreboot.org/c/coreboot/+/48342 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I140fcee714ca550d403be1e0042e9f729f4417a5 Gerrit-Change-Number: 48342 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: newchange

4 11

Change in coreboot[master]: mb/amd/mandolin: cereme: Use 64K instead of 0x1000 for size notation
by Paul Menzel (Code Review) 10 Jun '23

10 Jun '23

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46558 ) Change subject: mb/amd/mandolin: cereme: Use 64K instead of 0x1000 for size notation ...................................................................... mb/amd/mandolin: cereme: Use 64K instead of 0x1000 for size notation Use the more readable size notation, which also unifies it with Mandolin’s FMD. Change-Id: I95c22d8d775104dc046601418bd402317dd8e676 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/mainboard/amd/mandolin/variants/cereme/board.fmd 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/46558/1 diff --git a/src/mainboard/amd/mandolin/variants/cereme/board.fmd b/src/mainboard/amd/mandolin/variants/cereme/board.fmd index b55b8b5..31a0b2a 100644 --- a/src/mainboard/amd/mandolin/variants/cereme/board.fmd +++ b/src/mainboard/amd/mandolin/variants/cereme/board.fmd @@ -1,7 +1,7 @@ FLASH@0xFF000000 16M { BIOS { EC 0x20000 - RW_MRC_CACHE 0x10000 + RW_MRC_CACHE 64K FMAP 0x1000 COREBOOT(CBFS) } -- To view, visit https://review.coreboot.org/c/coreboot/+/46558 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I95c22d8d775104dc046601418bd402317dd8e676 Gerrit-Change-Number: 46558 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

3 2

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit June 2023