coreboot-gerrit June 2023

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Change in coreboot[master]: sb/intel/lynxpoint: call pch_gpi_routing() in -H instead of -LP PCH
by Iru Cai (vimacs) (Code Review) 10 Jun '23

10 Jun '23

Hello Iru Cai, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/41485 to review the following change. Change subject: sb/intel/lynxpoint: call pch_gpi_routing() in -H instead of -LP PCH ...................................................................... sb/intel/lynxpoint: call pch_gpi_routing() in -H instead of -LP PCH GPI_ROUT is in LynxPoint-H PCH [1], and not in LynxPoint-LP [2]. So call pch_gpi_routing() when PCH is not -LP. Also add GPI_ROUT2 register according to the datasheet. Need testing on real hardware. [1] Intel 8 Series/C220 Series Chipset Family Platform Controller Hub (PCH) Datasheet, Document Number 328904-003 [2] Mobile 4th Generation Intel Core Processor Family I/O Datasheet, Document Number: 329003-003 Change-Id: Id9999ea9cb44565832d44a57423e89ede1c6b238 Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- M src/southbridge/intel/lynxpoint/chip.h M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/pch.h 3 files changed, 22 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/41485/1 diff --git a/src/southbridge/intel/lynxpoint/chip.h b/src/southbridge/intel/lynxpoint/chip.h index ed362a2..ce38faa 100644 --- a/src/southbridge/intel/lynxpoint/chip.h +++ b/src/southbridge/intel/lynxpoint/chip.h @@ -44,6 +44,14 @@ uint8_t gpi13_routing; uint8_t gpi14_routing; uint8_t gpi15_routing; + uint8_t gpi17_routing; + uint8_t gpi19_routing; + uint8_t gpi21_routing; + uint8_t gpi22_routing; + uint8_t gpi43_routing; + uint8_t gpi56_routing; + uint8_t gpi57_routing; + uint8_t gpi60_routing; uint32_t gpe0_en_1; uint32_t gpe0_en_2; diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 3535312..e15452e 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -161,6 +161,18 @@ reg32 |= (config->gpi15_routing & 0x03) << 30; pci_write_config32(dev, GPIO_ROUT, reg32); + + reg32 = 0; + reg32 |= (config->gpi17_routing & 0x03) << 0; + reg32 |= (config->gpi19_routing & 0x03) << 2; + reg32 |= (config->gpi21_routing & 0x03) << 4; + reg32 |= (config->gpi22_routing & 0x03) << 6; + reg32 |= (config->gpi43_routing & 0x03) << 8; + reg32 |= (config->gpi56_routing & 0x03) << 10; + reg32 |= (config->gpi57_routing & 0x03) << 12; + reg32 |= (config->gpi60_routing & 0x03) << 14; + + pci_write_config32(dev, GPIO_ROUT2, reg32); } static void pch_power_options(struct device *dev) @@ -243,7 +255,7 @@ * Set the board's GPI routing on LynxPoint-H. * This is done as part of GPIO configuration on LynxPoint-LP. */ - if (pch_is_lp()) + if (!pch_is_lp()) pch_gpi_routing(dev); /* GPE setup based on device tree configuration */ diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 19f8637..8e1f9f1 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -214,6 +214,7 @@ #define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */ #define GPIO_CNTL 0x4C /* LPC GPIO Control Register */ #define GPIO_ROUT 0xb8 +#define GPIO_ROUT2 0xbc #define PIRQA_ROUT 0x60 #define PIRQB_ROUT 0x61 -- To view, visit https://review.coreboot.org/c/coreboot/+/41485 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9999ea9cb44565832d44a57423e89ede1c6b238 Gerrit-Change-Number: 41485 Gerrit-PatchSet: 1 Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: WIP: spm: Code to dump back the content
by Nicolas Boichat (Code Review) 10 Jun '23

10 Jun '23

Nicolas Boichat has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47357 ) Change subject: WIP: spm: Code to dump back the content ...................................................................... WIP: spm: Code to dump back the content Wondering if we should clean this up and commit it, might be useful in the future. Change-Id: Iebd276d293f30dc9c5d67d0d83aa117826c74444 --- M src/soc/mediatek/mt8192/spm.c 1 file changed, 174 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/47357/1 diff --git a/src/soc/mediatek/mt8192/spm.c b/src/soc/mediatek/mt8192/spm.c index 85d2e13..8d69696 100644 --- a/src/soc/mediatek/mt8192/spm.c +++ b/src/soc/mediatek/mt8192/spm.c @@ -8,6 +8,9 @@ #include <soc/spm.h> #include <soc/symbols.h> #include <timer.h> +#include <arch/cache.h> + +static u8 spm_dump[0x4000] __aligned(16); static struct pwr_ctrl spm_init_ctrl = { /* Auto-gen Start */ @@ -493,6 +496,9 @@ u32 dmem_start; u32 con0; + dcache_clean_invalidate_all(); + printk(BIOS_INFO, "SPM firmware @%08lx.\n", (long)(_dram_dma+16)); + ptr = (uintptr_t) pcm->buf + 0x40000000; pmem_words = pcm->desc.pmem_words; total_words = pcm->desc.total_words; @@ -512,15 +518,155 @@ write32(&mtk_spm->md32pcm_dma0_wpto, dmem_start); write32(&mtk_spm->md32pcm_dma0_count, total_words); write32(&mtk_spm->md32pcm_dma0_con, MD32PCM_DMA0_CON_VAL); + write32(&mtk_spm->md32pcm_dma0_start, 0); write32(&mtk_spm->md32pcm_dma0_start, MD32PCM_DMA0_START_VAL); + + { + u32 rlct[32]; u32 pc[32]; int i; + for (i = 0; i < ARRAY_SIZE(rlct); i++) { + pc[i] = read32(&mtk_spm->md32pcm_pc); + rlct[i] = read32(&mtk_spm->md32pcm_dma0_rlct); + udelay(1); + } + + printk(BIOS_INFO, "spm md32pcm_dma0_rlct @%08lx\n", (long)&mtk_spm->md32pcm_dma0_rlct); + for (i = 0; i < ARRAY_SIZE(rlct); i++) { + printk(BIOS_INFO, "spm rlct[%d] = 0x%x\n", i, rlct[i]); + printk(BIOS_INFO, "spm pc[%d] = 0x%x\n", i, pc[i]); + } + } } else { write32(&mtk_spm->pcm_con1, read32(&mtk_spm->pcm_con1) | SPM_REGWR_CFG_KEY | RG_IM_SLAVE_LSB); } + while (read32(&mtk_spm->md32pcm_dma0_rlct) != 0x0) + ; + /* kick IM to fetch (only toggle IM_KICK) */ con0 = read32(&mtk_spm->pcm_con0); write32(&mtk_spm->pcm_con0, con0 | SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB); + printk(BIOS_INFO, "SPM con0 0x%08x/0x%08x\n", con0, con0 | SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB); +} + +static void spm_read_back(struct dyna_load_pcm *pcm) +{ + uintptr_t ptr; + u32 pmem_words; + u32 total_words; + u32 pmem_start; + u32 dmem_start; + + dcache_clean_invalidate_all(); + + printk(BIOS_INFO, "SPM firmware readback(a)%08lx.\n", (long)spm_dump); + + ptr = (uintptr_t) spm_dump + 0x40000000; + pmem_words = pcm->desc.pmem_words; + total_words = pcm->desc.total_words; + pmem_start = pcm->desc.pmem_start; + dmem_start = pcm->desc.dmem_start; + + write32(&mtk_spm->md32pcm_dma0_src, pmem_start); + write32(&mtk_spm->md32pcm_dma0_dst, ptr); + write32(&mtk_spm->md32pcm_dma0_wppt, pmem_words); + write32(&mtk_spm->md32pcm_dma0_wpto, dmem_start); + write32(&mtk_spm->md32pcm_dma0_count, pmem_words); + write32(&mtk_spm->md32pcm_dma0_con, MD32PCM_DMA0_CON_VAL); + write32(&mtk_spm->md32pcm_dma0_start, 0); + write32(&mtk_spm->md32pcm_dma0_start, MD32PCM_DMA0_START_VAL); + + { + u32 rlct[32]; int i; + for (i = 0; i < ARRAY_SIZE(rlct); i++) { + rlct[i] = read32(&mtk_spm->md32pcm_dma0_rlct); + udelay(10); + } + + printk(BIOS_INFO, "spm md32pcm_dma0_rlct @%08lx\n", (long)&mtk_spm->md32pcm_dma0_rlct); + for (i = 0; i < ARRAY_SIZE(rlct); i++) { + printk(BIOS_INFO, "spm rlct[%d] = 0x%x\n", i, rlct[i]); + } + } + + /* No need to wait for DMA to finish here, printf is slow enough */ + + dcache_clean_invalidate_all(); + { + int i; + + printk(BIOS_INFO, "SPM firmware DUMP.\n"); + + u32 *spm_dump32 = (u32 *)spm_dump; + u32 *dram_dma32 = (u32 *)(_dram_dma+16); + + for (i = 0; i < pmem_words; i++) { + printk(BIOS_INFO, "%08x(%08lx): cbfs(0x%08x) back(0x%08x) %s\n", + i, (long)&dram_dma32[i], dram_dma32[i], spm_dump32[i], + spm_dump32[i] == dram_dma32[i] ? "" : "DIFF"); + } + } +} + +static void spm_read_back_data(struct dyna_load_pcm *pcm) +{ + uintptr_t ptr; + u32 pmem_words; + u32 dmem_words; + u32 total_words; + u32 pmem_start; + u32 dmem_start; + + dcache_clean_invalidate_all(); + + printk(BIOS_INFO, "SPM firmware readback DATA(a)%08lx.\n", (long)spm_dump); + + ptr = (uintptr_t) spm_dump + 0x40000000; + pmem_words = pcm->desc.pmem_words; + total_words = pcm->desc.total_words; + pmem_start = pcm->desc.pmem_start; + dmem_start = pcm->desc.dmem_start; + dmem_words = total_words-pmem_words; + + write32(&mtk_spm->md32pcm_dma0_src, dmem_start); + write32(&mtk_spm->md32pcm_dma0_dst, ptr); + write32(&mtk_spm->md32pcm_dma0_wppt, dmem_words); + write32(&mtk_spm->md32pcm_dma0_wpto, dmem_start); + write32(&mtk_spm->md32pcm_dma0_count, dmem_words); + write32(&mtk_spm->md32pcm_dma0_con, MD32PCM_DMA0_CON_VAL); + write32(&mtk_spm->md32pcm_dma0_start, 0); + write32(&mtk_spm->md32pcm_dma0_start, MD32PCM_DMA0_START_VAL); + + { + u32 rlct[32]; int i; + for (i = 0; i < ARRAY_SIZE(rlct); i++) { + rlct[i] = read32(&mtk_spm->md32pcm_dma0_rlct); + udelay(10); + } + + printk(BIOS_INFO, "spm md32pcm_dma0_rlct @%08lx\n", (long)&mtk_spm->md32pcm_dma0_rlct); + for (i = 0; i < ARRAY_SIZE(rlct); i++) { + printk(BIOS_INFO, "spm rlct[%d] = 0x%x\n", i, rlct[i]); + } + } + + /* No need to wait for DMA to finish here, printf is slow enough */ + + dcache_clean_invalidate_all(); + { + int i; + + printk(BIOS_INFO, "SPM firmware DUMP (DATA).\n"); + + u32 *spm_dump32 = (u32 *)spm_dump; + u32 *dram_dma32 = (u32 *)(_dram_dma+16)+pmem_words; + + for (i = 0; i < dmem_words; i++) { + printk(BIOS_INFO, "%08x(%08lx): cbfs(0x%08x) back(0x%08x) %s\n", + i, (long)&dram_dma32[i], dram_dma32[i], spm_dump32[i], + spm_dump32[i] == dram_dma32[i] ? "" : "DIFF"); + } + } } static void spm_init_pcm_register(void) @@ -655,9 +801,12 @@ write32(&mtk_spm->spm_sw_rsv_8, pwrctrl->pcm_flags1); } +static u32 pc[4096]; + static void spm_kick_pcm_to_run(struct pwr_ctrl *pwrctrl) { u32 con0, rstn; + int i, cnt; /* Waiting for loading SPMFW done*/ while (read32(&mtk_spm->md32pcm_dma0_rlct) != 0x0) @@ -680,14 +829,24 @@ write32(&mtk_spm->md32pcm_cfgreg_sw_rstn, rstn | MD32PCM_CFGREG_SW_RSTN_RESET); - /* Waiting for SPM init done */ - udelay(SPM_INIT_DONE_US); + for (cnt = 0; cnt < ARRAY_SIZE(pc); cnt++) { + pc[cnt] = read32(&mtk_spm->md32pcm_pc); + if (pc[cnt] == 0x3f4) + break; + /* Waiting for SPM init done */ + //udelay(SPM_INIT_DONE_US/ARRAY_SIZE(pc)); + } + + printk(BIOS_INFO, "spm pc @%08lx (%d loops)\n", (long)&mtk_spm->md32pcm_pc, cnt); + for (i = 0; i < cnt; i++) + printk(BIOS_INFO, "spm pc[%d] = 0x%x\n", i, pc[i]); } -int spm_init(void) +static inline int spm_init_lon(void) { struct dyna_load_pcm pcm; struct stopwatch sw; + int i; stopwatch_init(&sw); @@ -702,6 +861,8 @@ spm_reset_and_init_pcm(); spm_kick_im_to_fetch(&pcm); + spm_read_back(&pcm); + spm_read_back_data(&pcm); spm_init_pcm_register(); spm_set_wakeup_event(&spm_init_ctrl); spm_kick_pcm_to_run(&spm_init_ctrl); @@ -710,5 +871,15 @@ __func__, stopwatch_duration_msecs(&sw), read32(&mtk_spm->md32pcm_pc)); + for (i = 0; i < sizeof(*mtk_spm)/4; i++) { + u32* p = (u32 *)mtk_spm; + printk(BIOS_INFO, "SPM: %08lx=%08x\n", (long)&p[i], read32(&p[i])); + } + return 0; } + +int spm_init(void) { + /* Shorten __func__ in function above */ + return spm_init_lon(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/47357 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iebd276d293f30dc9c5d67d0d83aa117826c74444 Gerrit-Change-Number: 47357 Gerrit-PatchSet: 1 Gerrit-Owner: Nicolas Boichat <drinkcat(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer: Add variant_devtree_update
by Chen Wisley (Code Review) 10 Jun '23

10 Jun '23

Hello Wisley Chen, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/47354 to review the following change. Change subject: mb/google/volteer: Add variant_devtree_update ...................................................................... mb/google/volteer: Add variant_devtree_update Add variant_devtree_update() to override devicetree setting. BUG=none BRANCH=volteer TEST=emerge-volteer coreboot Signed-off-by: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Change-Id: Ida87617669e6c843b48427e87e9bb154a5df7d9e --- M src/mainboard/google/volteer/mainboard.c M src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h 2 files changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/47354/1 diff --git a/src/mainboard/google/volteer/mainboard.c b/src/mainboard/google/volteer/mainboard.c index acba972..77f9f57 100644 --- a/src/mainboard/google/volteer/mainboard.c +++ b/src/mainboard/google/volteer/mainboard.c @@ -64,6 +64,11 @@ } } +void __weak variant_devtree_update(void) +{ + /* Override dev tree settings per board */ +} + static void mainboard_init(struct device *dev) { mainboard_ec_init(); @@ -114,6 +119,7 @@ cfg->gpio_override_pm = 1; memset(cfg->gpio_pm, 0, sizeof(cfg->gpio_pm)); } + variant_devtree_update(); } static void mainboard_chip_init(void *chip_info) diff --git a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h index 8408198..4d5dc87 100644 --- a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h @@ -21,4 +21,7 @@ const struct ddr_memory_cfg *variant_memory_params(void); int variant_memory_sku(void); +/* Modify devictree settings during ramstage. */ +void variant_devtree_update(void); + #endif /* __BASEBOARD_VARIANTS_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/47354 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida87617669e6c843b48427e87e9bb154a5df7d9e Gerrit-Change-Number: 47354 Gerrit-PatchSet: 1 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

2 1

Change in coreboot[master]: HACK: Random SPM debugging code
by Nicolas Boichat (Code Review) 10 Jun '23

10 Jun '23

Nicolas Boichat has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47359 ) Change subject: HACK: Random SPM debugging code ...................................................................... HACK: Random SPM debugging code Change-Id: I5880a91628e6999094257c49d1a4f0348fc69eeb --- M src/soc/mediatek/mt8192/spm.c 1 file changed, 46 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/47359/1 diff --git a/src/soc/mediatek/mt8192/spm.c b/src/soc/mediatek/mt8192/spm.c index e263fc3..cf8b10e 100644 --- a/src/soc/mediatek/mt8192/spm.c +++ b/src/soc/mediatek/mt8192/spm.c @@ -493,6 +493,9 @@ u32 dmem_start; u32 con0; + printk(BIOS_INFO, "SPM firmware @%08lx (Pmem:%08x/Total:%08x).\n", + (long)(pcm->buf), pcm->desc.pmem_words, pcm->desc.total_words); + ptr = (uintptr_t) pcm->buf + 0x40000000; pmem_words = pcm->desc.pmem_words; total_words = pcm->desc.total_words; @@ -517,7 +520,23 @@ write32(&mtk_spm->md32pcm_dma0_wpto, dmem_start); write32(&mtk_spm->md32pcm_dma0_count, total_words); write32(&mtk_spm->md32pcm_dma0_con, MD32PCM_DMA0_CON_VAL); + write32(&mtk_spm->md32pcm_dma0_start, 0); write32(&mtk_spm->md32pcm_dma0_start, MD32PCM_DMA0_START_VAL); + + { + u32 rlct[32]; u32 pc[32]; int i; + for (i = 0; i < ARRAY_SIZE(rlct); i++) { + pc[i] = read32(&mtk_spm->md32pcm_pc); + rlct[i] = read32(&mtk_spm->md32pcm_dma0_rlct); + udelay(1); + } + + printk(BIOS_INFO, "spm md32pcm_dma0_rlct @%08lx\n", (long)&mtk_spm->md32pcm_dma0_rlct); + for (i = 0; i < ARRAY_SIZE(rlct); i++) { + printk(BIOS_INFO, "spm rlct[%d] = 0x%x\n", i, rlct[i]); + printk(BIOS_INFO, "spm pc[%d] = 0x%x\n", i, pc[i]); + } + } } else { write32(&mtk_spm->pcm_con1, read32(&mtk_spm->pcm_con1) | SPM_REGWR_CFG_KEY | RG_IM_SLAVE_LSB); @@ -526,6 +545,7 @@ /* kick IM to fetch (only toggle IM_KICK) */ con0 = read32(&mtk_spm->pcm_con0); write32(&mtk_spm->pcm_con0, con0 | SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB); + printk(BIOS_INFO, "SPM con0 0x%08x/0x%08x\n", con0, con0 | SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB); } #define SPM_DEBUG_DUMP 1 @@ -721,9 +741,12 @@ write32(&mtk_spm->spm_sw_rsv_8, pwrctrl->pcm_flags1); } +static u32 pc[4096]; + static void spm_kick_pcm_to_run(struct pwr_ctrl *pwrctrl) { u32 con0, rstn; + int i, cnt; /* Waiting for loading SPMFW done*/ while (read32(&mtk_spm->md32pcm_dma0_rlct) != 0x0) @@ -746,14 +769,24 @@ write32(&mtk_spm->md32pcm_cfgreg_sw_rstn, rstn | MD32PCM_CFGREG_SW_RSTN_RESET); - /* Waiting for SPM init done */ - udelay(SPM_INIT_DONE_US); + for (cnt = 0; cnt < ARRAY_SIZE(pc); cnt++) { + pc[cnt] = read32(&mtk_spm->md32pcm_pc); + if (pc[cnt] == 0x3f4) + break; + /* Waiting for SPM init done */ + //udelay(SPM_INIT_DONE_US/ARRAY_SIZE(pc)); + } + + printk(BIOS_INFO, "spm pc @%08lx (%d loops)\n", (long)&mtk_spm->md32pcm_pc, cnt); + for (i = 0; i < cnt; i++) + printk(BIOS_INFO, "spm pc[%d] = 0x%x\n", i, pc[i]); } -int spm_init(void) +static inline int spm_init_lon(void) { struct dyna_load_pcm pcm; struct stopwatch sw; + int i; stopwatch_init(&sw); @@ -780,5 +813,15 @@ __func__, stopwatch_duration_msecs(&sw), read32(&mtk_spm->md32pcm_pc)); + for (i = 0; i < sizeof(*mtk_spm)/4; i++) { + u32* p = (u32 *)mtk_spm; + printk(BIOS_INFO, "SPM: %08lx=%08x\n", (long)&p[i], read32(&p[i])); + } + return 0; } + +int spm_init(void) { + /* Shorten __func__ in function above */ + return spm_init_lon(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/47359 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5880a91628e6999094257c49d1a4f0348fc69eeb Gerrit-Change-Number: 47359 Gerrit-PatchSet: 1 Gerrit-Owner: Nicolas Boichat <drinkcat(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/scaleway/tagada: Add bmcinfo field confMRC to configure FSP MRC code
by Julien Viard de Galbert (Code Review) 10 Jun '23

10 Jun '23

Julien Viard de Galbert has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47479 ) Change subject: mb/scaleway/tagada: Add bmcinfo field confMRC to configure FSP MRC code ...................................................................... mb/scaleway/tagada: Add bmcinfo field confMRC to configure FSP MRC code The BMC now expose an extra field to give more control over the FSP MRC options. Change-Id: I2cad2ec24ff61d384e040c23a24782d8934b6f0b Signed-off-by: Julien Viard de Galbert <jviarddegalbert(a)online.net> --- M src/mainboard/scaleway/tagada/bmcinfo.c M src/mainboard/scaleway/tagada/bmcinfo.h M src/mainboard/scaleway/tagada/romstage.c 3 files changed, 21 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/47479/1 diff --git a/src/mainboard/scaleway/tagada/bmcinfo.c b/src/mainboard/scaleway/tagada/bmcinfo.c index 9f30a7e..b2037fc 100644 --- a/src/mainboard/scaleway/tagada/bmcinfo.c +++ b/src/mainboard/scaleway/tagada/bmcinfo.c @@ -21,6 +21,7 @@ u8 bootOption; u8 hwRev; // Note: Initial implementation ended here u8 disableNic1; + u8 confMRC; u8 endMarker; // Insert new fields before } biosBmcInfo_t; @@ -162,6 +163,15 @@ return 0; } +int bmcinfo_conf_mrc(void) +{ + if (IS_BMC_INFO_FIELD_VALID(confMRC)) { + printk(BIOS_DEBUG, "bmcInfo confMRC=%x\n", BMC_INFO->confMRC); + return BMC_INFO->confMRC; + } + return CONF_MRC_DEFAULT; +} + /* Add override functions below */ /* Override default uart baudrate */ diff --git a/src/mainboard/scaleway/tagada/bmcinfo.h b/src/mainboard/scaleway/tagada/bmcinfo.h index 016de9b..de014bb 100644 --- a/src/mainboard/scaleway/tagada/bmcinfo.h +++ b/src/mainboard/scaleway/tagada/bmcinfo.h @@ -13,6 +13,13 @@ // Reset after boot sequence (don't go to EFI shell) #define BOOT_OPTION_NO_EFISHELL 0x80 +// Enable FastBoot +#define CONF_MRC_FAST_BOOT 1 +// Enable MRC RMT reporting +#define CONF_MRC_RMT_ENABLE 2 + +#define CONF_MRC_DEFAULT (CONF_MRC_FAST_BOOT | CONF_MRC_RMT_ENABLE) + char *bmcinfo_serial(void); u8 *bmcinfo_uuid(void); int bmcinfo_slot(void); @@ -23,5 +30,6 @@ int bmcinfo_relax_security(void); int bmcinfo_boot_option(void); int bmcinfo_disable_nic1(void); +int bmcinfo_conf_mrc(void); #endif /* MAINBOARD_BMCINFO_H */ diff --git a/src/mainboard/scaleway/tagada/romstage.c b/src/mainboard/scaleway/tagada/romstage.c index f041b6f..6b3ac47 100644 --- a/src/mainboard/scaleway/tagada/romstage.c +++ b/src/mainboard/scaleway/tagada/romstage.c @@ -41,6 +41,7 @@ // Enable Rmt and Fast Boot by default, RMT will be run only on first // boot or when dimms change - mupd->FspmConfig.PcdMrcRmtSupport = 1; - mupd->FspmConfig.PcdFastBoot = 1; + int confMRC = bmcinfo_conf_mrc(); + mupd->FspmConfig.PcdMrcRmtSupport = (confMRC & CONF_MRC_RMT_ENABLE)?1:0; + mupd->FspmConfig.PcdFastBoot = (confMRC & CONF_MRC_FAST_BOOT)?1:0; } -- To view, visit https://review.coreboot.org/c/coreboot/+/47479 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2cad2ec24ff61d384e040c23a24782d8934b6f0b Gerrit-Change-Number: 47479 Gerrit-PatchSet: 1 Gerrit-Owner: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-MessageType: newchange

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[XS] Change in coreboot[master]: MAKE: MOAAAAAR $$$$$$$$
by Stefan Reinauer (Code Review) 10 Jun '23

10 Jun '23

Stefan Reinauer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/29639?usp=email ) Change subject: MAKE: MOAAAAAR $$$$$$$$ ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/29639?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19d3016e67f8930345e0da9564abcc5e5f8ab365 Gerrit-Change-Number: 29639 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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[M] Change in coreboot[master]: nb/intel/x4x: allow to force RAM timings ignoring SPD values
by Stefan Reinauer (Code Review) 10 Jun '23

10 Jun '23

Stefan Reinauer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/28200?usp=email ) Change subject: nb/intel/x4x: allow to force RAM timings ignoring SPD values ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/28200?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia0bb1ff22c89e62c62b53211ca2544430f6cfee0 Gerrit-Change-Number: 28200 Gerrit-PatchSet: 1 Gerrit-Owner: Stefan T <stefan.tauner(a)gmx.at> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Stefan T <stefan.tauner(a)gmx.at> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: mb/hatch + soc/intel/cannonlake: Enable TetonGlacierMode on hatch
by David Jimenez (Code Review) 10 Jun '23

10 Jun '23

David Jimenez has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38947 ) Change subject: mb/hatch + soc/intel/cannonlake: Enable TetonGlacierMode on hatch ...................................................................... mb/hatch + soc/intel/cannonlake: Enable TetonGlacierMode on hatch Enabling TetonGlacierMode allows for reconfiguring the PCIe lanes at runtime for hybrid drives. BUG=b:149171631 BRANCH=none TEST=Swap between x4 NVMe drives and 2x2 Teton Glacier hybrid drives and run lsblk, lspci, and nvme tools to confirm dynamic PCIe configuration Signed-off-by: David Jimenez <dvjimenez(a)chromium.org> Change-Id: If775b40e6922ac7d111ac00c7c51eec6623ed4df --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/fsp_params.c 3 files changed, 15 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/38947/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index f7cf3cd..f360c10 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -50,6 +50,8 @@ register "PchUnlockGpioPads" = "1" # SD card WP pin confguration register "ScsSdCardWpPinEnabled" = "0" + # Auto-switch between X4 NVMe and X2 NVMe for hybrid storage support + register "TetonGlacierMode" = "1" # NOTE: if any variant wants to override this value, use the same format # as register "common_soc_config.pch_thermal_trip" = "value", instead of @@ -163,7 +165,7 @@ register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN register "usb3_ports[5]" = "USB3_PORT_EMPTY" - # Enable Root port 9(x4) for NVMe. + # Enable Root port 9(x2) for NVMe. register "PcieRpEnable[8]" = "1" register "PcieRpLtrEnable[8]" = "1" # RP 9 uses CLK SRC 1 @@ -171,6 +173,10 @@ # ClkReq-to-ClkSrc mapping for CLK SRC 1 register "PcieClkSrcClkReq[1]" = "1" + # Enable Root port 11(x2) for NVMe hybrid storage devices. + register "PcieRpEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "1" + # PCIe port 14 for M.2 E-key WLAN register "PcieRpEnable[13]" = "1" register "PcieRpLtrEnable[13]" = "1" @@ -324,9 +330,9 @@ device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on end # PCI Express Port 9 (X4 NVME) + device pci 1d.0 on end # PCI Express Port 9 (X2 NVME) device pci 1d.1 off end # PCI Express Port 10 - device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.2 on end # PCI Express Port 11 (x2 NVME) device pci 1d.3 off end # PCI Express Port 12 device pci 1d.4 off end # PCI Express port 13 device pci 1d.5 on diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index fd37d26..16265d2 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -242,6 +242,9 @@ * Setting to 0 (default) disables Heci1 and hides the device from OS */ uint8_t HeciEnabled; + // Enables support for Teton Glacier hybrid storage device + uint8_t TetonGlacierMode; + /* PL1 Override value in Watts */ uint32_t tdp_pl1_override; /* PL2 Override value in Watts */ diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index dc4a2a8..e8ad62f 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -374,6 +374,9 @@ #endif params->Device4Enable = config->Device4Enable; + /* Teton Glacier hybrid storage support */ + params->TetonGlacierMode = config->TetonGlacierMode; + /* VrConfig Settings for 5 domains * 0 = System Agent, 1 = IA Core, 2 = Ring, * 3 = GT unsliced, 4 = GT sliced */ -- To view, visit https://review.coreboot.org/c/coreboot/+/38947 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If775b40e6922ac7d111ac00c7c51eec6623ed4df Gerrit-Change-Number: 38947 Gerrit-PatchSet: 1 Gerrit-Owner: David Jimenez <dvjimenez(a)chromium.org> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: soc/intel/common/block/cse: Add functions to support setting DAM state
by Stefan Reinauer (Code Review) 10 Jun '23

10 Jun '23

Stefan Reinauer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/46882?usp=email ) Change subject: soc/intel/common/block/cse: Add functions to support setting DAM state ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/46882?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If42eb150577e9f76318e77ae31eb6f5844a4143d Gerrit-Change-Number: 46882 Gerrit-PatchSet: 6 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamirbohra(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik Vaghela <maulikvaghela(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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[M] Change in coreboot[master]: soc/intel/common/block/cse: Add MCHI MCA group functions to cse lib
by Stefan Reinauer (Code Review) 10 Jun '23

10 Jun '23

Stefan Reinauer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/46880?usp=email ) Change subject: soc/intel/common/block/cse: Add MCHI MCA group functions to cse lib ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/46880?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1bdb83daffc291c618f3193b5b4e159c3eff188e Gerrit-Change-Number: 46880 Gerrit-PatchSet: 6 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamirbohra(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik Vaghela <maulikvaghela(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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