coreboot-gerrit June 2023

coreboot-gerrit@coreboot.org

1 participants
5387 discussions

Change in coreboot[master]: mb/emulation/qemu-armv7/memlayout: Move regions
by Patrick Rudolph (Code Review) 10 Jun '23

10 Jun '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44395 ) Change subject: mb/emulation/qemu-armv7/memlayout: Move regions ...................................................................... mb/emulation/qemu-armv7/memlayout: Move regions Move pre RAM regions into SRAM. Tested using uImage/FIT, still boots into GNU/Linux 5.5.7. Change-Id: I32b3664f018eded576262cf7b52a94dcd6d4f346 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/mainboard/emulation/qemu-armv7/memlayout.ld 1 file changed, 9 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/44395/1 diff --git a/src/mainboard/emulation/qemu-armv7/memlayout.ld b/src/mainboard/emulation/qemu-armv7/memlayout.ld index b0408ed..c1e99eb 100644 --- a/src/mainboard/emulation/qemu-armv7/memlayout.ld +++ b/src/mainboard/emulation/qemu-armv7/memlayout.ld @@ -28,19 +28,19 @@ REGION(nor_flash1, 0x40000000, 0x4000000, 4K) REGION(nor_flash2, 0x44000000, 0x4000000, 4K) SRAM_START(0x48000000) + STACK(0x48000000, 64K) + FMAP_CACHE(0x48010000, 4K) + TIMESTAMP(0x48011000, 1K) + TTB_SUBTABLES(0x48012000, 4K) + TTB(0x48014000, 32K) + BOOTBLOCK(0x48020000, 128K) + ROMSTAGE(0x48040000, 128K) SRAM_END(0x4C000000) REGION(videoram, 0x4c000000, 0x1000000, 4K) REGION(ethernet, 0x4e000000, 0x1000000, 4K) REGION(usb, 0x4f000000, 0x1000000, 4K) DRAM_START(0x60000000) - STACK(0x60000000, 64K) - BOOTBLOCK(0x60010000, 128K) - FMAP_CACHE(0x60030000, 4K) - TIMESTAMP(0x60031000, 1K) - TTB_SUBTABLES(0x60032000, 4K) - TTB(0x60034000, 32K) - ROMSTAGE(0x60040000, 128K) - RAMSTAGE(0x60060000, 16M) - POSTRAM_CBFS_CACHE(0x61060000, 8M) + RAMSTAGE(0x60000000, 16M) + POSTRAM_CBFS_CACHE(0x61000000, 8M) } -- To view, visit https://review.coreboot.org/c/coreboot/+/44395 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32b3664f018eded576262cf7b52a94dcd6d4f346 Gerrit-Change-Number: 44395 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

2 1

Change in coreboot[master]: soc/intel/tigerlake: Clean up report_cpu_info() function
by Alexey Buyanov (Code Review) 10 Jun '23

10 Jun '23

Alexey Buyanov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44050 ) Change subject: soc/intel/tigerlake: Clean up report_cpu_info() function ...................................................................... soc/intel/tigerlake: Clean up report_cpu_info() function This patch uses the fill_processor_name function in order to fetch the CPU Name. BUG=none TEST=successfully built and booted TGLRVP Signed-off-by: Alexey Buyanov <alexey.buyanov(a)intel.com> Change-Id: I97be5d6b0a6fc5785c10ace3b78a1bc9c9f31230 --- M src/soc/intel/tigerlake/bootblock/report_platform.c 1 file changed, 4 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/44050/1 diff --git a/src/soc/intel/tigerlake/bootblock/report_platform.c b/src/soc/intel/tigerlake/bootblock/report_platform.c index 6acc0c3..d715725 100644 --- a/src/soc/intel/tigerlake/bootblock/report_platform.c +++ b/src/soc/intel/tigerlake/bootblock/report_platform.c @@ -10,6 +10,7 @@ #include <device/pci_ops.h> #include <console/console.h> #include <cpu/x86/msr.h> +#include <cpu/x86/name.h> #include <device/pci.h> #include <device/pci_ids.h> #include <intelblocks/mp_init.h> @@ -99,35 +100,14 @@ static void report_cpu_info(void) { - struct cpuid_result cpuidr; - u32 i, index, cpu_id, cpu_feature_flag; - const char cpu_not_found[] = "Platform info not available"; - const char *cpu_name = cpu_not_found; /* 48 bytes are reported */ + u32 i, cpu_id, cpu_feature_flag; + char cpu_name[49]; int vt, txt, aes; msr_t microcode_ver; static const char *const mode[] = {"NOT ", ""}; const char *cpu_type = "Unknown"; - u32 p[13]; - index = 0x80000000; - cpuidr = cpuid(index); - if (cpuidr.eax >= 0x80000004) { - int j = 0; - - for (i = 2; i <= 4; i++) { - cpuidr = cpuid(index + i); - p[j++] = cpuidr.eax; - p[j++] = cpuidr.ebx; - p[j++] = cpuidr.ecx; - p[j++] = cpuidr.edx; - } - p[12] = 0; - cpu_name = (char *)p; - - /* Skip leading spaces in CPU name string */ - while (cpu_name[0] == ' ' && strlen(cpu_name) > 0) - cpu_name++; - } + fill_processor_name(cpu_name); microcode_ver.lo = 0; microcode_ver.hi = 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/44050 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I97be5d6b0a6fc5785c10ace3b78a1bc9c9f31230 Gerrit-Change-Number: 44050 Gerrit-PatchSet: 1 Gerrit-Owner: Alexey Buyanov <alexey.buyanov(a)intel.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: mb/intel/tglrvp: Enable CSE Firmware Lite SKU
by Shreesh Chhabbi (Code Review) 10 Jun '23

10 Jun '23

Hello Jamie Ryu, Shreesh Chhabbi, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44853 to review the following change. Change subject: mb/intel/tglrvp: Enable CSE Firmware Lite SKU ...................................................................... mb/intel/tglrvp: Enable CSE Firmware Lite SKU BUG=None BRANCH=None TEST=Build and boot tglrvp with CSE Lite and Consumer SKU Change-Id: I78b2000acad24314d239d32ee60b5c6583aae363 Signed-off-by: Jamie Ryu <jamie.m.ryu(a)intel.com> --- M src/mainboard/intel/tglrvp/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/44853/1 diff --git a/src/mainboard/intel/tglrvp/Kconfig b/src/mainboard/intel/tglrvp/Kconfig index 3e55f56..2ad6e79 100644 --- a/src/mainboard/intel/tglrvp/Kconfig +++ b/src/mainboard/intel/tglrvp/Kconfig @@ -18,6 +18,7 @@ select DRIVERS_INTEL_ISH select EC_ACPI select PCIEXP_HOTPLUG + select SOC_INTEL_CSE_LITE_SKU config CHROMEOS bool -- To view, visit https://review.coreboot.org/c/coreboot/+/44853 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78b2000acad24314d239d32ee60b5c6583aae363 Gerrit-Change-Number: 44853 Gerrit-PatchSet: 1 Gerrit-Owner: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Gerrit-MessageType: newchange

2 1

Change in coreboot[master]: prodrive/hermes: Disable USB power on S5
by Patrick Rudolph (Code Review) 10 Jun '23

10 Jun '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44526 ) Change subject: prodrive/hermes: Disable USB power on S5 ...................................................................... prodrive/hermes: Disable USB power on S5 Change-Id: I9d78e8966b7ccc06b04045fda6bda36eab464051 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/prodrive/hermes/dsdt.asl 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/44526/1 diff --git a/src/mainboard/prodrive/hermes/dsdt.asl b/src/mainboard/prodrive/hermes/dsdt.asl index 4d8d170..c1bed5f 100644 --- a/src/mainboard/prodrive/hermes/dsdt.asl +++ b/src/mainboard/prodrive/hermes/dsdt.asl @@ -20,6 +20,16 @@ #include <soc/intel/common/block/acpi/acpi/northbridge.asl> #include <soc/intel/cannonlake/acpi/southbridge.asl> } + Method (MPTS,1) { + if (Arg0 == 5) { + /* Disable USB power on S5 */ + \_SB.PCI0.CTXS(GPP_G0) + \_SB.PCI0.CTXS(GPP_G1) + \_SB.PCI0.CTXS(GPP_G2) + \_SB.PCI0.CTXS(GPP_G3) + \_SB.PCI0.CTXS(GPP_G4) + } + } } #include <southbridge/intel/common/acpi/sleepstates.asl> -- To view, visit https://review.coreboot.org/c/coreboot/+/44526 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9d78e8966b7ccc06b04045fda6bda36eab464051 Gerrit-Change-Number: 44526 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

2 1

Change in coreboot[master]: mtrr.h: refine _POW2_MASK
by ky0ko (Code Review) 10 Jun '23

10 Jun '23

ky0ko has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44845 ) Change subject: mtrr.h: refine _POW2_MASK ...................................................................... mtrr.h: refine _POW2_MASK this patch adjusts _POW2_MASK to work with rom sizes between 64KiB and 512MiB, additionally fixing incorrectness for sizes 128MiB and above that previously were present. Change-Id: I0272c0c43cba44f6fbfb5dc539509b4ed9b92e75 Signed-off-by: ky0ko <ky0ko(a)disroot.org> --- M src/include/cpu/x86/mtrr.h 1 file changed, 4 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/44845/1 diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 42964b0..fd4159d 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -176,9 +176,11 @@ #endif /* !defined(__ASSEMBLER__) */ /* Align up/down to next power of 2, suitable for assembler - too. Range of result 256kB to 128MB is good enough here. */ + too. Range works from 64kB to 512MB. */ #define _POW2_MASK(x) ((x>>1)|(x>>2)|(x>>3)|(x>>4)|(x>>5)| \ - (x>>6)|(x>>7)|(x>>8)|((1<<18)-1)) + (x>>6)|(x>>7)|(x>>8)|(x>>9)|(x>>10)| \ + (x>>11)|(x>>12)|(x>>13)|((1<<16)-1)) + #define _ALIGN_UP_POW2(x) ((x + _POW2_MASK(x)) & ~_POW2_MASK(x)) #define _ALIGN_DOWN_POW2(x) ((x) & ~_POW2_MASK(x)) -- To view, visit https://review.coreboot.org/c/coreboot/+/44845 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0272c0c43cba44f6fbfb5dc539509b4ed9b92e75 Gerrit-Change-Number: 44845 Gerrit-PatchSet: 1 Gerrit-Owner: ky0ko <ky0ko(a)disroot.org> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: [WIP] 3rdparty/libgfxinit: Update submodule pointer
by Angel Pons (Code Review) 10 Jun '23

10 Jun '23

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44071 ) Change subject: [WIP] 3rdparty/libgfxinit: Update submodule pointer ...................................................................... [WIP] 3rdparty/libgfxinit: Update submodule pointer This brings in Bay Trail support. Change-Id: Ia4b265862e2a7cce8e3d272dee9d22aba8358fa5 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M 3rdparty/libgfxinit 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/44071/1 diff --git a/3rdparty/libgfxinit b/3rdparty/libgfxinit index 3318bf2..729fff7 160000 --- a/3rdparty/libgfxinit +++ b/3rdparty/libgfxinit @@ -1 +1 @@ -Subproject commit 3318bf26803c77d41b18bef6d7ae4e051b97f9f2 +Subproject commit 729fff7de5070bbfd2975065549b1f9fbf057976 -- To view, visit https://review.coreboot.org/c/coreboot/+/44071 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia4b265862e2a7cce8e3d272dee9d22aba8358fa5 Gerrit-Change-Number: 44071 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

2 6

Change in coreboot[master]: mb/volteer: Disable Precision Time Measurement for PCIe RP 9
by Shreesh Chhabbi (Code Review) 10 Jun '23

10 Jun '23

Hello Shreesh Chhabbi, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/45302 to review the following change. Change subject: mb/volteer: Disable Precision Time Measurement for PCIe RP 9 ...................................................................... mb/volteer: Disable Precision Time Measurement for PCIe RP 9 Change-Id: Id42d0485a5ff8cb2c1886c460e6ec2f1fb540516 Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/45302/1 diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 1b8b0d6..eb1f1a9 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -99,6 +99,9 @@ register "PcieClkSrcUsage[5]" = "0xFF" register "PcieClkSrcUsage[6]" = "0xFF" + # PCIe RP PTM + register "PciePtm[8]" = "0" + # Enable SATA register "SataEnable" = "1" register "SataMode" = "0" -- To view, visit https://review.coreboot.org/c/coreboot/+/45302 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id42d0485a5ff8cb2c1886c460e6ec2f1fb540516 Gerrit-Change-Number: 45302 Gerrit-PatchSet: 1 Gerrit-Owner: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Reviewer: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Gerrit-MessageType: newchange

2 1

Change in coreboot[master]: nb/intel/sandybridge: Read spds only once if measured boot is enabled
by Bill XIE (Code Review) 10 Jun '23

10 Jun '23

Bill XIE has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39969 ) Change subject: nb/intel/sandybridge: Read spds only once if measured boot is enabled ...................................................................... nb/intel/sandybridge: Read spds only once if measured boot is enabled Without considering s3 resume, spd may be used various times depending on various condition. If spd is stored in CBFS and read various times, PCR value may become inconsistent. As mentioned in CB:39906, in order to avoid this, we could read spd exactly once, and use the data read out various times, when measured boot is enabled. Change-Id: I02cad7e85d5e66fd9efb674e4dc9868233f6c233 Signed-off-by: Bill XIE <persmule(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit.c 1 file changed, 27 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/39969/1 diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index b096a11..f3c81a6 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -98,6 +98,17 @@ } } +static bool spd_is_available(const spd_raw_data spds[], size_t num_spd) +{ + /* An available spd should at least have an non-zero id */ + size_t i, j, sum = 0; + for (i = 0; i < num_spd; i++) { + for (j = 117; j < 128; j++) + sum += spds[i][j]; + } + return (sum > 0); +} + static void dram_find_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl) { int dimms = 0, ch_dimms; @@ -222,6 +233,8 @@ struct region_device rdev; ramctr_timing *ctrl_cached = NULL; + if (CONFIG(TPM_MEASURED_BOOT)) + memset(spds, 0, sizeof(spds)); MCHBAR32(SAPMCTL) |= 1; /* Wait for ME to be ready */ @@ -271,8 +284,14 @@ /* Verify MRC cache for fast boot */ if (!s3resume && ctrl_cached) { /* Load SPD unique information data. */ - memset(spds, 0, sizeof(spds)); - mainboard_get_spd(spds, 1); + if (CONFIG(TPM_MEASURED_BOOT)) { + /* if CONFIG(TPM_MEASURED_BOOT), + we manage to get spds only ONCE */ + mainboard_get_spd(spds, 0); + } else { + memset(spds, 0, sizeof(spds)); + mainboard_get_spd(spds, 1); + } /* check SPD CRC16 to make sure the DIMMs haven't been replaced */ fast_boot = verify_crc16_spds_ddr3(spds, ctrl_cached); @@ -307,8 +326,12 @@ ctrl.cpu = cpuid; /* Get DDR3 SPD data */ - memset(spds, 0, sizeof(spds)); - mainboard_get_spd(spds, 0); + if (!CONFIG(TPM_MEASURED_BOOT) || !spd_is_available(spds, 4)) { + /* without CONFIG(TPM_MEASURED_BOOT), the previous read may + only contains id, so read it again */ + memset(spds, 0, sizeof(spds)); + mainboard_get_spd(spds, 0); + } dram_find_spds_ddr3(spds, &ctrl); err = try_init_dram_ddr3(&ctrl, fast_boot, s3resume, me_uma_size); -- To view, visit https://review.coreboot.org/c/coreboot/+/39969 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I02cad7e85d5e66fd9efb674e4dc9868233f6c233 Gerrit-Change-Number: 39969 Gerrit-PatchSet: 1 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-MessageType: newchange

4 12

Change in coreboot[master]: soc/intel/common: Call pci_dev_enable_bus_master() from .final ops
by Subrata Banik (Code Review) 10 Jun '23

10 Jun '23

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44512 ) Change subject: soc/intel/common: Call pci_dev_enable_bus_master() from .final ops ...................................................................... soc/intel/common: Call pci_dev_enable_bus_master() from .final ops Enable PCI_COMMAND_MASTER for all PCI controller to ensure device can behave as a bus master. Otherwise, the device can not generate PCI accesses. BUG=b:154900210 TEST=Able to build and boot CML and TGL platform. Change-Id: Ife65f6029d2f966e321f616e85f59f4c37c42145 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/dsp/dsp.c M src/soc/intel/common/block/dtt/dtt.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/hda/hda.c M src/soc/intel/common/block/i2c/i2c.c M src/soc/intel/common/block/ipu/ipu.c M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/common/block/p2sb/p2sb.c M src/soc/intel/common/block/pcie/pcie.c M src/soc/intel/common/block/pmc/pmc.c M src/soc/intel/common/block/sata/sata.c M src/soc/intel/common/block/scs/mmc.c M src/soc/intel/common/block/scs/sd.c M src/soc/intel/common/block/smbus/smbus.c M src/soc/intel/common/block/spi/spi.c M src/soc/intel/common/block/sram/sram.c M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/common/block/uart/uart.c M src/soc/intel/common/block/xdci/xdci.c M src/soc/intel/common/block/xhci/xhci.c 21 files changed, 21 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/44512/1 diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 4b598e2..5d73812 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -870,6 +870,7 @@ .read_resources = pci_dev_read_resources, .enable_resources = pci_dev_enable_resources, .init = pci_dev_init, + .final = pci_dev_enable_bus_master, .ops_pci = &pci_dev_ops_pci, }; diff --git a/src/soc/intel/common/block/dsp/dsp.c b/src/soc/intel/common/block/dsp/dsp.c index 776a22b..80f758a 100644 --- a/src/soc/intel/common/block/dsp/dsp.c +++ b/src/soc/intel/common/block/dsp/dsp.c @@ -8,6 +8,7 @@ .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, + .final = pci_dev_enable_bus_master, .ops_pci = &pci_dev_ops_pci, .scan_bus = scan_static_bus, }; diff --git a/src/soc/intel/common/block/dtt/dtt.c b/src/soc/intel/common/block/dtt/dtt.c index f396993..a04bc7b 100644 --- a/src/soc/intel/common/block/dtt/dtt.c +++ b/src/soc/intel/common/block/dtt/dtt.c @@ -14,6 +14,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .scan_bus = scan_generic_bus, + .final = pci_dev_enable_bus_master, .ops_pci = &pci_dev_ops_pci, }; diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index 38d41df..0aa832b 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -170,6 +170,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = gma_init, + .final = pci_dev_enable_bus_master, .ops_pci = &pci_dev_ops_pci, #if CONFIG(HAVE_ACPI_TABLES) .acpi_fill_ssdt = gma_generate_ssdt, diff --git a/src/soc/intel/common/block/hda/hda.c b/src/soc/intel/common/block/hda/hda.c index e4bcf99..2f8bc24 100644 --- a/src/soc/intel/common/block/hda/hda.c +++ b/src/soc/intel/common/block/hda/hda.c @@ -53,6 +53,7 @@ #if CONFIG(SOC_INTEL_COMMON_BLOCK_HDA_VERB) .init = hda_init, #endif + .final = pci_dev_enable_bus_master, .ops_pci = &pci_dev_ops_pci, .scan_bus = scan_static_bus }; diff --git a/src/soc/intel/common/block/i2c/i2c.c b/src/soc/intel/common/block/i2c/i2c.c index 0de3bd3..5b2a755 100644 --- a/src/soc/intel/common/block/i2c/i2c.c +++ b/src/soc/intel/common/block/i2c/i2c.c @@ -168,6 +168,7 @@ .enable_resources = pci_dev_enable_resources, .scan_bus = scan_smbus, .ops_i2c_bus = &dw_i2c_bus_ops, + .final = pci_dev_enable_bus_master, .ops_pci = &pci_dev_ops_pci, .init = dw_i2c_device_init, #if CONFIG(HAVE_ACPI_TABLES) diff --git a/src/soc/intel/common/block/ipu/ipu.c b/src/soc/intel/common/block/ipu/ipu.c index f7b01aa..58030a1 100644 --- a/src/soc/intel/common/block/ipu/ipu.c +++ b/src/soc/intel/common/block/ipu/ipu.c @@ -8,6 +8,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_bus_enable_resources, .scan_bus = scan_generic_bus, + .final = pci_dev_enable_bus_master, .ops_pci = &pci_dev_ops_pci, }; diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c index 212fd70..a16f10f 100644 --- a/src/soc/intel/common/block/lpc/lpc.c +++ b/src/soc/intel/common/block/lpc/lpc.c @@ -105,6 +105,7 @@ #endif .init = lpc_soc_init, .scan_bus = scan_static_bus, + .final = pci_dev_enable_bus_master, .ops_pci = &pci_dev_ops_pci, }; diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c index d97cd8d..f7c7545 100644 --- a/src/soc/intel/common/block/p2sb/p2sb.c +++ b/src/soc/intel/common/block/p2sb/p2sb.c @@ -124,6 +124,7 @@ static const struct device_operations device_ops = { .read_resources = read_resources, .set_resources = noop_set_resources, + .final = pci_dev_enable_bus_master, .ops_pci = &pci_dev_ops_pci, }; diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c index e506905..55ada78 100644 --- a/src/soc/intel/common/block/pcie/pcie.c +++ b/src/soc/intel/common/block/pcie/pcie.c @@ -64,6 +64,7 @@ .enable_resources = pci_bus_enable_resources, .init = pch_pcie_init, .scan_bus = pciexp_scan_bridge, + .final = pci_dev_enable_bus_master, .ops_pci = &pcie_ops, }; diff --git a/src/soc/intel/common/block/pmc/pmc.c b/src/soc/intel/common/block/pmc/pmc.c index 24f28e3..44a77b2 100644 --- a/src/soc/intel/common/block/pmc/pmc.c +++ b/src/soc/intel/common/block/pmc/pmc.c @@ -103,6 +103,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = pmc_soc_init, + .final = pci_dev_enable_bus_master, .ops_pci = &pci_dev_ops_pci, .scan_bus = scan_static_bus, }; diff --git a/src/soc/intel/common/block/sata/sata.c b/src/soc/intel/common/block/sata/sata.c index 1889700..eb1d8c6 100644 --- a/src/soc/intel/common/block/sata/sata.c +++ b/src/soc/intel/common/block/sata/sata.c @@ -4,17 +4,11 @@ #include <device/pci.h> #include <device/pci_ids.h> -static void sata_final(struct device *dev) -{ - /* Set Bus Master */ - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); -} - static struct device_operations sata_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .final = sata_final, + .final = pci_dev_enable_bus_master, .ops_pci = &pci_dev_ops_pci, }; diff --git a/src/soc/intel/common/block/scs/mmc.c b/src/soc/intel/common/block/scs/mmc.c index 6772f74..debec19 100644 --- a/src/soc/intel/common/block/scs/mmc.c +++ b/src/soc/intel/common/block/scs/mmc.c @@ -67,6 +67,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = mmc_soc_init, + .final = pci_dev_enable_bus_master, .ops_pci = &pci_dev_ops_pci, }; diff --git a/src/soc/intel/common/block/scs/sd.c b/src/soc/intel/common/block/scs/sd.c index 04ebb13..17d508f 100644 --- a/src/soc/intel/common/block/scs/sd.c +++ b/src/soc/intel/common/block/scs/sd.c @@ -48,6 +48,7 @@ #if CONFIG(HAVE_ACPI_TABLES) .acpi_fill_ssdt = sd_fill_ssdt, #endif + .final = pci_dev_enable_bus_master, .ops_pci = &pci_dev_ops_pci, }; diff --git a/src/soc/intel/common/block/smbus/smbus.c b/src/soc/intel/common/block/smbus/smbus.c index ae9f650..70581dc 100644 --- a/src/soc/intel/common/block/smbus/smbus.c +++ b/src/soc/intel/common/block/smbus/smbus.c @@ -70,6 +70,7 @@ .enable_resources = pci_dev_enable_resources, .scan_bus = scan_smbus, .init = pch_smbus_init, + .final = pci_dev_enable_bus_master, .ops_pci = &pci_dev_ops_pci, .ops_smbus_bus = &lops_smbus_bus, }; diff --git a/src/soc/intel/common/block/spi/spi.c b/src/soc/intel/common/block/spi/spi.c index 295df09..d73c008 100644 --- a/src/soc/intel/common/block/spi/spi.c +++ b/src/soc/intel/common/block/spi/spi.c @@ -35,6 +35,7 @@ .enable_resources = pci_dev_enable_resources, .scan_bus = scan_generic_bus, .ops_spi_bus = &spi_bus_ops, + .final = pci_dev_enable_bus_master, .ops_pci = &pci_dev_ops_pci, }; diff --git a/src/soc/intel/common/block/sram/sram.c b/src/soc/intel/common/block/sram/sram.c index 426a5f7..002b164 100644 --- a/src/soc/intel/common/block/sram/sram.c +++ b/src/soc/intel/common/block/sram/sram.c @@ -29,6 +29,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = soc_sram_init, + .final = pci_dev_enable_bus_master, .ops_pci = &pci_dev_ops_pci, }; diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 39ac53f..4eb7c9d 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -306,6 +306,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = sa_soc_systemagent_init, + .final = pci_dev_enable_bus_master, .ops_pci = &pci_dev_ops_pci, #if CONFIG(HAVE_ACPI_TABLES) .write_acpi_tables = sa_write_acpi_tables, diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c index ed4f9c6..039dcd2 100644 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -229,6 +229,7 @@ .read_resources = uart_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = uart_common_enable_resources, + .final = pci_dev_enable_bus_master, .ops_pci = &pci_dev_ops_pci, }; diff --git a/src/soc/intel/common/block/xdci/xdci.c b/src/soc/intel/common/block/xdci/xdci.c index 54cb076..4008177 100644 --- a/src/soc/intel/common/block/xdci/xdci.c +++ b/src/soc/intel/common/block/xdci/xdci.c @@ -18,6 +18,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = soc_xdci_init, + .final = pci_dev_enable_bus_master, .ops_pci = &pci_dev_ops_pci, }; diff --git a/src/soc/intel/common/block/xhci/xhci.c b/src/soc/intel/common/block/xhci/xhci.c index 47f2567..f8b9571 100644 --- a/src/soc/intel/common/block/xhci/xhci.c +++ b/src/soc/intel/common/block/xhci/xhci.c @@ -98,6 +98,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = soc_xhci_init, + .final = pci_dev_enable_bus_master, .ops_pci = &pci_dev_ops_pci, .scan_bus = scan_static_bus, #if CONFIG(HAVE_ACPI_TABLES) -- To view, visit https://review.coreboot.org/c/coreboot/+/44512 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ife65f6029d2f966e321f616e85f59f4c37c42145 Gerrit-Change-Number: 44512 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

7 24

Change in coreboot[master]: [DONOTSUBMIT]lib: Introduce memory bugs to help test ASan
by Harshit Sharma (Code Review) 10 Jun '23

10 Jun '23

Harshit Sharma has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43938 ) Change subject: [DONOTSUBMIT]lib: Introduce memory bugs to help test ASan ...................................................................... [DONOTSUBMIT]lib: Introduce memory bugs to help test ASan Introduces a few memory bugs into cbfs code to make testing easier for the ones who are willing to try out ASan on their hardware. Change-Id: I0839f2fd2863934ec28e2322bab04b9cc33363b4 Signed-off-by: Harshit Sharma <harshitsharmajs(a)gmail.com> --- M src/lib/cbfs.c 1 file changed, 21 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/43938/1 diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index cb66f81..839de94 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -330,9 +330,30 @@ return 0; } +#if ENV_RAMSTAGE + int global_array[5] = {-1}; +#endif + int cbfs_boot_region_device(struct region_device *rdev) { + int stack_array[5], i, *p; boot_device_init(); + + /* global out-of-bounds */ +#if ENV_RAMSTAGE + for (i = 10; i > 0; i--) + global_array[i] = i; +#endif + /* stack out-of-bounds */ + for (i = 10; i > 0; i--) + stack_array[i] = i; + + /* use-after-scope */ + { + int x = 5; + p = &x; + } + *p = 10; return vboot_locate_cbfs(rdev) && fmap_locate_area_as_rdev("COREBOOT", rdev); } -- To view, visit https://review.coreboot.org/c/coreboot/+/43938 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0839f2fd2863934ec28e2322bab04b9cc33363b4 Gerrit-Change-Number: 43938 Gerrit-PatchSet: 1 Gerrit-Owner: Harshit Sharma <harshitsharmajs(a)gmail.com> Gerrit-MessageType: newchange

4 21

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit June 2023