coreboot-gerrit June 2023

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[M] Change in coreboot[master]: vc/intel/fsp/fsp20/meteorlake: Add VR config entries
by Subrata Banik (Code Review) 14 Jun '23

14 Jun '23

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75761?usp=email ) Change subject: vc/intel/fsp/fsp20/meteorlake: Add VR config entries ...................................................................... vc/intel/fsp/fsp20/meteorlake: Add VR config entries This patch adds UPD entries into the FSP header file to configure VRs (IA, GT and SA). - `IccLimit` : VR Fast Vmode ICC Limit support - `EnableFastVmode` : Enable/Disable VR FastVmode - `CepEnable` : Enable/Disable CEP (Current Excursion Protection BUG=b:286809233 TEST=Able to build google/rex. Change-Id: I477ab7e4c07156759962bd2eab9dff28a0a3f006 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75761 Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Ronak Kanabar <ronak.kanabar(a)intel.com> --- M src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h 1 file changed, 74 insertions(+), 46 deletions(-) Approvals: build bot (Jenkins): Verified Ronak Kanabar: Looks good to me, approved Kapil Porwal: Looks good to me, approved diff --git a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h index f8edff8..aacb42a 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h @@ -1433,7 +1433,35 @@ /** Offset 0x06B4 - Reserved **/ - UINT8 Reserved33[336]; + UINT8 Reserved33[166]; + +/** Offset 0x075A - VR Fast Vmode ICC Limit support + Voltage Regulator Fast Vmode ICC Limit. A value of 400 = 100A. A value of 0 corresponds + to feature disabled (no reactive protection). This value represents the current + threshold where the VR would initiate reactive protection if Fast Vmode is enabled. + The value is represented in 1/4 A increments. Range 0-2040. [0] for IA, [1] for + GT, [2] for SA, [3] through [5] are Reserved. +**/ + UINT16 IccLimit[6]; + +/** Offset 0x0766 - Enable/Disable VR FastVmode. The VR will initiate reactive protection if Fast Vmode is enabled. + Enable/Disable VR FastVmode; [0] for IA, [1] for GT, 0: Disable; 1: Enable. + [2] for SA, 0: Disable; 1: Enable. + 0: Disable, 1: Enable +**/ + UINT8 EnableFastVmode[6]; + +/** Offset 0x076C - Enable CEP + Enable/Disable CEP (Current Excursion Protection) Support. [0] for IA, [1] for GT, + 0: Disable; 1: Enable. [2] for SA, 0: Disable; 1: Enable. [3] through + [5] are Reserved. + $EN_DIS +**/ + UINT8 CepEnable[6]; + +/** Offset 0x0772 - Reserved +**/ + UINT8 Reserved34[146]; /** Offset 0x0804 - BiosGuard Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable @@ -1455,7 +1483,7 @@ /** Offset 0x0807 - Reserved **/ - UINT8 Reserved34; + UINT8 Reserved35; /** Offset 0x0808 - PrmrrSize Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable @@ -1469,7 +1497,7 @@ /** Offset 0x0810 - Reserved **/ - UINT8 Reserved35[8]; + UINT8 Reserved36[8]; /** Offset 0x0818 - TxtDprMemoryBase Enable/Disable. 0: Disable, define default value of TxtDprMemoryBase , 1: enable @@ -1524,7 +1552,7 @@ /** Offset 0x0849 - Reserved **/ - UINT8 Reserved36[32]; + UINT8 Reserved37[32]; /** Offset 0x0869 - Enable PCH HSIO PCIE Rx Set Ctle Enable PCH PCIe Gen 3 Set CTLE Value. @@ -1711,7 +1739,7 @@ /** Offset 0x0A85 - Reserved **/ - UINT8 Reserved37; + UINT8 Reserved38; /** Offset 0x0A86 - SMBUS Base Address SMBUS Base Address (IO space). @@ -1731,7 +1759,7 @@ /** Offset 0x0A99 - Reserved **/ - UINT8 Reserved38[16]; + UINT8 Reserved39[16]; /** Offset 0x0AA9 - SOC/IOE ClkReq-to-ClkSrc mapping Number of ClkReq signal assigned to ClkSrc @@ -1740,7 +1768,7 @@ /** Offset 0x0AB9 - Reserved **/ - UINT8 Reserved39[55]; + UINT8 Reserved40[55]; /** Offset 0x0AF0 - Enable PCH PCIE RP Mask Enable/disable PCH PCIE Root Ports. 0: disable, 1: enable. One bit for each port, @@ -1792,7 +1820,7 @@ /** Offset 0x0AFE - Reserved **/ - UINT8 Reserved40[2]; + UINT8 Reserved41[2]; /** Offset 0x0B00 - DMIC<N> ClkA Pin Muxing (N - DMIC number) Determines DMIC<N> ClkA Pin muxing. See GPIO_*_MUXING_DMIC<N>_CLKA_* @@ -1812,7 +1840,7 @@ /** Offset 0x0B11 - Reserved **/ - UINT8 Reserved41[3]; + UINT8 Reserved42[3]; /** Offset 0x0B14 - DMIC<N> Data Pin Muxing Determines DMIC<N> Data Pin muxing. See GPIO_*_MUXING_DMIC<N>_DATA_* @@ -1837,7 +1865,7 @@ /** Offset 0x0B27 - Reserved **/ - UINT8 Reserved42; + UINT8 Reserved43; /** Offset 0x0B28 - iDisp-Link T-mode iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 2: 4T, 3: 8T, 4: 16T @@ -1853,7 +1881,7 @@ /** Offset 0x0B2A - Reserved **/ - UINT8 Reserved43[6]; + UINT8 Reserved44[6]; /** Offset 0x0B30 - CNVi DDR RFI Mitigation Enable/Disable DDR RFI Mitigation. Default is ENABLE. 0: DISABLE, 1: ENABLE @@ -1863,7 +1891,7 @@ /** Offset 0x0B31 - Reserved **/ - UINT8 Reserved44[11]; + UINT8 Reserved45[11]; /** Offset 0x0B3C - Debug Interfaces Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub, @@ -1885,7 +1913,7 @@ /** Offset 0x0B3F - Reserved **/ - UINT8 Reserved45; + UINT8 Reserved46; /** Offset 0x0B40 - Serial Io Uart Debug BaudRate Set default BaudRate Supported from 0 - default to 6000000. Recommended values 9600, @@ -1913,7 +1941,7 @@ /** Offset 0x0B47 - Reserved **/ - UINT8 Reserved46; + UINT8 Reserved47; /** Offset 0x0B48 - Serial Io Uart Debug Mmio Base Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSerialIoUartMode @@ -1929,7 +1957,7 @@ /** Offset 0x0B4D - Reserved **/ - UINT8 Reserved47; + UINT8 Reserved48; /** Offset 0x0B4E - Ring PLL voltage offset Core PLL voltage offset. 0: No offset. Range 0-15 @@ -1943,7 +1971,7 @@ /** Offset 0x0B50 - Reserved **/ - UINT8 Reserved48; + UINT8 Reserved49; /** Offset 0x0B51 - Memory Controller PLL voltage offset Core PLL voltage offset. 0: No offset. Range 0-15 @@ -2061,7 +2089,7 @@ /** Offset 0x0B64 - Reserved **/ - UINT8 Reserved49; + UINT8 Reserved50; /** Offset 0x0B65 - Write Timing Centering 1D Enables/Disable Write Timing Centering 1D @@ -2089,7 +2117,7 @@ /** Offset 0x0B69 - Reserved **/ - UINT8 Reserved50[10]; + UINT8 Reserved51[10]; /** Offset 0x0B73 - Read Equalization Training Enables/Disable Read Equalization Training @@ -2099,7 +2127,7 @@ /** Offset 0x0B74 - Reserved **/ - UINT8 Reserved51[2]; + UINT8 Reserved52[2]; /** Offset 0x0B76 - Write Timing Centering 2D Enables/Disable Write Timing Centering 2D @@ -2127,7 +2155,7 @@ /** Offset 0x0B7A - Reserved **/ - UINT8 Reserved52; + UINT8 Reserved53; /** Offset 0x0B7B - Command Voltage Centering Enables/Disable Command Voltage Centering @@ -2155,7 +2183,7 @@ /** Offset 0x0B7F - Reserved **/ - UINT8 Reserved53; + UINT8 Reserved54; /** Offset 0x0B80 - DIMM SPD Alias Test Enables/Disable DIMM SPD Alias Test @@ -2171,7 +2199,7 @@ /** Offset 0x0B82 - Reserved **/ - UINT8 Reserved54; + UINT8 Reserved55; /** Offset 0x0B83 - Dimm ODT Training Enables/Disable Dimm ODT Training @@ -2205,7 +2233,7 @@ /** Offset 0x0B88 - Reserved **/ - UINT8 Reserved55[2]; + UINT8 Reserved56[2]; /** Offset 0x0B8A - DIMM CA ODT Training Enable/Disable DIMM CA ODT Training @@ -2215,7 +2243,7 @@ /** Offset 0x0B8B - Reserved **/ - UINT8 Reserved56[3]; + UINT8 Reserved57[3]; /** Offset 0x0B8E - Read Vref Decap Training Enable/Disable Read Vref Decap Training @@ -2237,7 +2265,7 @@ /** Offset 0x0B91 - Reserved **/ - UINT8 Reserved57[4]; + UINT8 Reserved58[4]; /** Offset 0x0B95 - Duty Cycle Correction Training Enable/Disable Duty Cycle Correction Training @@ -2247,7 +2275,7 @@ /** Offset 0x0B96 - Reserved **/ - UINT8 Reserved58[17]; + UINT8 Reserved59[17]; /** Offset 0x0BA7 - ECC Support Enables/Disable ECC Support @@ -2281,7 +2309,7 @@ /** Offset 0x0BB3 - Reserved **/ - UINT8 Reserved59; + UINT8 Reserved60; /** Offset 0x0BB4 - IbeccProtectedRegionBases IBECC Protected Region Bases per IBECC instance @@ -2361,7 +2389,7 @@ /** Offset 0x0BEE - Reserved **/ - UINT8 Reserved60; + UINT8 Reserved61; /** Offset 0x0BEF - Exit On Failure (MRC) Enables/Disable Exit On Failure (MRC) @@ -2371,7 +2399,7 @@ /** Offset 0x0BF0 - Reserved **/ - UINT8 Reserved61[4]; + UINT8 Reserved62[4]; /** Offset 0x0BF4 - Select if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP ESelect if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP @@ -2630,7 +2658,7 @@ /** Offset 0x0C2B - Reserved **/ - UINT8 Reserved62[2]; + UINT8 Reserved63[2]; /** Offset 0x0C2D - Rapl Power Floor Ch0 Power budget ,range[255;0],(0= 5.3W Def) @@ -2650,7 +2678,7 @@ /** Offset 0x0C30 - Reserved **/ - UINT8 Reserved63; + UINT8 Reserved64; /** Offset 0x0C31 - Energy Performance Gain Enable/disable Energy Performance Gain. 0: Disable; 1: Enable @@ -2660,7 +2688,7 @@ /** Offset 0x0C32 - Reserved **/ - UINT8 Reserved64; + UINT8 Reserved65; /** Offset 0x0C33 - User Manual Threshold Disabled: Predefined threshold will be used.\n @@ -2678,7 +2706,7 @@ /** Offset 0x0C35 - Reserved **/ - UINT8 Reserved65; + UINT8 Reserved66; /** Offset 0x0C36 - Power Down Mode This option controls command bus tristating during idle periods @@ -2715,7 +2743,7 @@ /** Offset 0x0C3B - Reserved **/ - UINT8 Reserved66[8]; + UINT8 Reserved67[8]; /** Offset 0x0C43 - Ask MRC to clear memory content Ask MRC to clear memory content 0: Do not Clear Memory; 1: Clear Memory. @@ -2730,7 +2758,7 @@ /** Offset 0x0C45 - Reserved **/ - UINT8 Reserved67; + UINT8 Reserved68; /** Offset 0x0C46 - Post Code Output Port This option configures Post Code Output Port @@ -2750,7 +2778,7 @@ /** Offset 0x0C4A - Reserved **/ - UINT8 Reserved68[2]; + UINT8 Reserved69[2]; /** Offset 0x0C4C - BCLK RFI Frequency Bclk RFI Frequency for each SAGV point in Hz units. 98000000Hz = 98MHz 0 - No @@ -2793,7 +2821,7 @@ /** Offset 0x0C62 - Reserved **/ - UINT8 Reserved69[13]; + UINT8 Reserved70[13]; /** Offset 0x0C6F - Command Pins Mapping BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller @@ -2809,7 +2837,7 @@ /** Offset 0x0C71 - Reserved **/ - UINT8 Reserved70[24]; + UINT8 Reserved71[24]; /** Offset 0x0C89 - Skip external display device scanning Enable: Do not scan for external display device, Disable (Default): Scan external @@ -2845,7 +2873,7 @@ /** Offset 0x0C8E - Reserved **/ - UINT8 Reserved71[2]; + UINT8 Reserved72[2]; /** Offset 0x0C90 - PMR Size Size of PMR memory buffer. 0x400000 for normal boot and 0x200000 for S3 boot @@ -2859,7 +2887,7 @@ /** Offset 0x0C95 - Reserved **/ - UINT8 Reserved72[143]; + UINT8 Reserved73[143]; /** Offset 0x0D24 - TotalFlashSize Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable @@ -2875,7 +2903,7 @@ /** Offset 0x0D28 - Reserved **/ - UINT8 Reserved73[28]; + UINT8 Reserved74[28]; /** Offset 0x0D44 - Smbus dynamic power gating Disable or Enable Smbus dynamic power gating. @@ -2891,7 +2919,7 @@ /** Offset 0x0D46 - Reserved **/ - UINT8 Reserved74[2]; + UINT8 Reserved75[2]; /** Offset 0x0D48 - SMBUS SPD Write Disable Set/Clear Smbus SPD Write Disable. 0: leave SPD Write Disable bit; 1: set SPD Write @@ -2902,7 +2930,7 @@ /** Offset 0x0D49 - Reserved **/ - UINT8 Reserved75[34]; + UINT8 Reserved76[34]; /** Offset 0x0D6B - HECI Timeouts 0: Disable, 1: Enable (Default) timeout check for HECI @@ -2955,7 +2983,7 @@ /** Offset 0x0D73 - Reserved **/ - UINT8 Reserved76[100]; + UINT8 Reserved77[100]; /** Offset 0x0DD7 - Avx2 Voltage Guardband Scaling Factor AVX2 Voltage Guardband Scale factor applied to AVX2 workloads. Range is 0-200 in @@ -2978,7 +3006,7 @@ /** Offset 0x0DDA - Reserved **/ - UINT8 Reserved77[2]; + UINT8 Reserved78[2]; /** Offset 0x0DDC - SerialIoUartDebugRxPinMux - FSPM Select RX pin muxing for SerialIo UART used for debug @@ -3004,7 +3032,7 @@ /** Offset 0x0DEC - Reserved **/ - UINT8 Reserved78[188]; + UINT8 Reserved79[188]; } FSP_M_CONFIG; /** Fsp M UPD Configuration -- To view, visit https://review.coreboot.org/c/coreboot/+/75761?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I477ab7e4c07156759962bd2eab9dff28a0a3f006 Gerrit-Change-Number: 75761 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Jay Patel <jay2.patel(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kilari Raasi <kilari.raasi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-MessageType: merged

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[XS] Change in coreboot[master]: drivers/intel/fsp2_0: Correct FSP performance timestamp unit
by Ronak Kanabar (Code Review) 14 Jun '23

14 Jun '23

Attention is currently required from: Andrey Petrov, Himanshu Sahdev, Pratikkumar V Prajapati, Subrata Banik, Wonkyu Kim. Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75816?usp=email ) Change subject: drivers/intel/fsp2_0: Correct FSP performance timestamp unit ...................................................................... Patch Set 2: (1 comment) File src/drivers/intel/fsp2_0/fsp_timestamp.c: https://review.coreboot.org/c/coreboot/+/75816/comment/93e693ae_38b46bc9 : PS2, Line 56: TIMESTAMP_MS > isn't it getting converted here and L:47 to MS before printing? https://review.coreboot.org/c/coreboot/+/62942 Check test prints in original patch it is in microseconds. I have observed same output. We are dividing by 1000 but data is still in microseconds. I confirmed with FSP team data is in nano second, so we need to divide by 10^6 to make it in ms. I thought better to change unit to us. I will change macro name as well. +--------------------------------------------------+ |------ FSP Performance Timestamp Table Dump ------| +--------------------------------------------------+ | Perf-ID Timestamp(ms) String/GUID | +--------------------------------------------------+ 0 460253 SEC/52c05b14-0b98-496c-bc3b04b50211d680 50 460263 PEI/52c05b14-0b98-496c-bc3b04b50211d680 40 460274 PreMem/52c05b14-0b98-496c-bc3b04b50211d680 -- To view, visit https://review.coreboot.org/c/coreboot/+/75816?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4aec4f63beddbd7ce6e8e3fc1b53a45da2ee0b00 Gerrit-Change-Number: 75816 Gerrit-PatchSet: 2 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Comment-Date: Wed, 14 Jun 2023 07:24:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/cmd/blk/cse: Hook get CSE RW version into `.final`
by Subrata Banik (Code Review) 14 Jun '23

14 Jun '23

Attention is currently required from: Dinesh Gehlot, Kapil Porwal. Subrata Banik has uploaded a new patch set (#3) to the change originally created by Dinesh Gehlot. ( https://review.coreboot.org/c/coreboot/+/75749?usp=email ) The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/cmd/blk/cse: Hook get CSE RW version into `.final` ...................................................................... soc/intel/cmd/blk/cse: Hook get CSE RW version into `.final` This patch calls get CSE RW version function from .final hook if the platform has required config (`SOC_INTEL_CSE_LITE_SKU`) selected. BUG=b:280722061 TEST=Able to build and boot google/rex. > cbmem -c | grep "CSE RW Firmware Version:" [DEBUG] CSE version: 18.0.0.1682 Signed-off-by: Dinesh Gehlot <digehlot(a)google.com> Change-Id: Ifdb82c180b64fbb4575932427be54f544e1c98d4 --- M src/soc/intel/common/block/cse/cse.c 1 file changed, 17 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/75749/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/75749?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifdb82c180b64fbb4575932427be54f544e1c98d4 Gerrit-Change-Number: 75749 Gerrit-PatchSet: 3 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/intel/cmd/blk/cse: Hook get CSE RW version into `.final`
by Subrata Banik (Code Review) 14 Jun '23

14 Jun '23

Attention is currently required from: Dinesh Gehlot, Kapil Porwal. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75749?usp=email ) Change subject: soc/intel/cmd/blk/cse: Hook get CSE RW version into `.final` ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/75749/comment/69a6929f_b2e6b51c : PS2, Line 16: CSE version > it inconsistent with the search string. Please update. can u please review patchset 2. I have added that already ? File src/soc/intel/common/block/cse/cse.c: https://review.coreboot.org/c/coreboot/+/75749/comment/5fb6848c_f3bd12fe : PS1, Line 1437: memory > don't need to repeat memory again `CBMEM` itself has MEM in it Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/75749?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifdb82c180b64fbb4575932427be54f544e1c98d4 Gerrit-Change-Number: 75749 Gerrit-PatchSet: 2 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Comment-Date: Wed, 14 Jun 2023 07:22:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/cmn/cse: Rename `cse_store_rw_fw_ver` helper fn
by Subrata Banik (Code Review) 14 Jun '23

14 Jun '23

Attention is currently required from: Dinesh Gehlot, Eric Lai, Kapil Porwal, Tarun Tuli. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75768?usp=email ) Change subject: soc/intel/cmn/cse: Rename `cse_store_rw_fw_ver` helper fn ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/common/block/cse/cse_lite.c: https://review.coreboot.org/c/coreboot/+/75768/comment/5a0f20f1_a2670865 : PS1, Line 1306: /* Store the CSE RW Firmware Version into CBMEM */ : cse_store_rw_fw_version(); > This looks more than just renaming a function as we have moved the code block from line 1312 to 1307 hence, updated the comment section as well to specify this function is to store the CSE RW FW version. Irrespective of this function being renamed or not, the additional comment being added due to decoupling -- To view, visit https://review.coreboot.org/c/coreboot/+/75768?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iba85807b7d9e6f067b5b628c6fa062fab5c485e0 Gerrit-Change-Number: 75768 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Wed, 14 Jun 2023 07:20:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/dedede/var/dibbi: Update power limits
by ChiaLing (Code Review) 14 Jun '23

14 Jun '23

Attention is currently required from: Reka Norman, Sumeet R Pawnikar, Zhuohao Lee. ChiaLing has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75681?usp=email ) Change subject: mb/google/dedede/var/dibbi: Update power limits ...................................................................... Patch Set 9: (1 comment) File src/mainboard/google/dedede/variants/dibbi/ramstage.c: https://review.coreboot.org/c/coreboot/+/75681/comment/80e8e0d7_d468f9bc : PS7, Line 29: 31 > From the bug, I thought we're not setting PsysPl1 for dibbi? Yes, you are right. I remove them in new one. -- To view, visit https://review.coreboot.org/c/coreboot/+/75681?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieaff856b762b546f3e99acb7ba2ce15791193da6 Gerrit-Change-Number: 75681 Gerrit-PatchSet: 9 Gerrit-Owner: ChiaLing <chia-ling.hou(a)intel.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Ryan Lin <ryan.lin(a)intel.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Comment-Date: Wed, 14 Jun 2023 07:07:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Reka Norman <rekanorman(a)chromium.org> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/dedede: Support variant specific power limits
by ChiaLing (Code Review) 14 Jun '23

14 Jun '23

Attention is currently required from: Paul Menzel, Reka Norman, Ryan Lin, Subrata Banik, Sumeet R Pawnikar, Zhuohao Lee. ChiaLing has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75680?usp=email ) Change subject: mb/google/dedede: Support variant specific power limits ...................................................................... Patch Set 8: (2 comments) Patchset: PS6: > Build is failing again. Done File src/mainboard/google/dedede/variants/baseboard/ramstage.c: https://review.coreboot.org/c/coreboot/+/75680/comment/a7c27128_a711c167 : PS6, Line 76: soc_config->tdp_pl4 = 0; > I don't think you need to zero this? Yes, you are right. I also remove psyspl1 setting at here. -- To view, visit https://review.coreboot.org/c/coreboot/+/75680?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I583c930379233322c41027805369f81d02000ee7 Gerrit-Change-Number: 75680 Gerrit-PatchSet: 8 Gerrit-Owner: ChiaLing <chia-ling.hou(a)intel.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Ryan Lin <ryan.lin(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Ryan Lin <ryan.lin(a)intel.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Comment-Date: Wed, 14 Jun 2023 07:07:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Reka Norman <rekanorman(a)chromium.org> Gerrit-MessageType: comment

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[L] Change in coreboot[master]: soc/intel/jasperlake: Add per-SKU power limits
by ChiaLing (Code Review) 14 Jun '23

14 Jun '23

Attention is currently required from: Paul Menzel, Reka Norman, Ryan Lin, Subrata Banik, Sumeet R Pawnikar, Zhuohao Lee. ChiaLing has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75679?usp=email ) Change subject: soc/intel/jasperlake: Add per-SKU power limits ...................................................................... Patch Set 10: (1 comment) File src/mainboard/google/dedede/variants/blipper/overridetree.cb: https://review.coreboot.org/c/coreboot/+/75679/comment/749a54d1_ddf14942 : PS5, Line 62: register "power_limits_config" = "{ : .tdp_pl1_override = 6, : .tdp_pl2_override = 20, : }" > I just want to make sure we're not changing the settings on existing dedede devices. […] I think setting PL4 in overridetree is a good way! I update baseboard.cb and set it in dibbi overridetree. -- To view, visit https://review.coreboot.org/c/coreboot/+/75679?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic086e32a2692f4f5f9b661585b216fa207fc56fd Gerrit-Change-Number: 75679 Gerrit-PatchSet: 10 Gerrit-Owner: ChiaLing <chia-ling.hou(a)intel.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Ryan Lin <ryan.lin(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Ryan Lin <ryan.lin(a)intel.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Comment-Date: Wed, 14 Jun 2023 07:06:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Reka Norman <rekanorman(a)chromium.org> Comment-In-Reply-To: ChiaLing <chia-ling.hou(a)intel.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: drivers/intel/fsp2_0: Correct FSP performance timestamp unit
by Sridhar Siricilla (Code Review) 14 Jun '23

14 Jun '23

Attention is currently required from: Andrey Petrov, Pratikkumar V Prajapati, Ronak Kanabar, Subrata Banik, Wonkyu Kim. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75816?usp=email ) Change subject: drivers/intel/fsp2_0: Correct FSP performance timestamp unit ...................................................................... Patch Set 2: -Code-Review -- To view, visit https://review.coreboot.org/c/coreboot/+/75816?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4aec4f63beddbd7ce6e8e3fc1b53a45da2ee0b00 Gerrit-Change-Number: 75816 Gerrit-PatchSet: 2 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Comment-Date: Wed, 14 Jun 2023 07:01:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/nissa/var/joxer: Disable storage devices based on fw_config
by Derek Huang (Code Review) 14 Jun '23

14 Jun '23

Attention is currently required from: Felix Held, Henry Sun, Mark Hsieh, Paul Menzel, Reka Norman, Sam McNally, Shou-Chieh Hsu, Tarun Tuli. Derek Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75743?usp=email ) Change subject: mb/google/nissa/var/joxer: Disable storage devices based on fw_config ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75743?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6920d88dfec86676ff6733146f748e06d4085c49 Gerrit-Change-Number: 75743 Gerrit-PatchSet: 5 Gerrit-Owner: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Zoey Wu <zoey_wu(a)wistron.corp-partner.google.com> Gerrit-Attention: Sam McNally <sammc(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 14 Jun 2023 06:42:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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