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Change subject: mb/google/myst: Add additional memory configurations
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Patch Set 2: Code-Review+2
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Change subject: google/zork: Convert baseboard directory layout
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Change subject: soc/amd/block/ivrs: Add NULL check for IVRS
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Change subject: mb/google/brya/var/taeko: Enable CsPiStartHighinEct
......................................................................
Patch Set 1: Code-Review+1
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/75825/comment/94b2622e_4dfa68fd :
PS1, Line 12: TEST=Pass MRC Cache test with toolkit 1000 times
warp line here.
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Change subject: mb/google/rex/var/screebo: rp2 change to rp1 and rp3
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
Can you please rewording the comment.
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Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75811?usp=email )
(
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
)Change subject: soc/intel/cmn/cse: Read ISH FW version if avilable in CSE partition
......................................................................
soc/intel/cmn/cse: Read ISH FW version if avilable in CSE partition
This patch reduces the redundant config check to understand if an ISH FW
partition is available and to fetch the ISH FW version.
The goal is to fetch the ISH FW version if the ISH FW belongs to the CSE
firmware partition table.
Change-Id: I689a71377e7aea0fa3bc1835f355708c33c2caea
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75811
Reviewed-by: Kapil Porwal <kapilporwal(a)google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/soc/intel/common/block/cse/cse_lite.c
1 file changed, 1 insertion(+), 2 deletions(-)
Approvals:
build bot (Jenkins): Verified
Kapil Porwal: Looks good to me, approved
diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c
index 97f114c..dd3f173 100644
--- a/src/soc/intel/common/block/cse/cse_lite.c
+++ b/src/soc/intel/common/block/cse/cse_lite.c
@@ -1309,8 +1309,7 @@
* Store the ISH RW Firmware Version into CBMEM if ISH partition
* is available
*/
- if (CONFIG(SOC_INTEL_STORE_ISH_FW_VERSION) &&
- soc_is_ish_partition_enabled())
+ if (soc_is_ish_partition_enabled())
store_ish_version();
}
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Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75749?usp=email )
(
7 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
)Change subject: soc/intel/cmd/blk/cse: Hook get CSE RW version into `.final`
......................................................................
soc/intel/cmd/blk/cse: Hook get CSE RW version into `.final`
This patch calls get CSE RW version function from .final hook if
the platform has required config (`SOC_INTEL_CSE_LITE_SKU`) selected.
BUG=b:280722061
TEST=Able to build and boot google/rex.
> cbmem -c | grep "CSE RW Firmware Version:"
[DEBUG] CSE RW Firmware Version: 18.0.0.1682
Signed-off-by: Dinesh Gehlot <digehlot(a)google.com>
Change-Id: Ifdb82c180b64fbb4575932427be54f544e1c98d4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75749
Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com>
Reviewed-by: Kapil Porwal <kapilporwal(a)google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/soc/intel/common/block/cse/cse.c
1 file changed, 17 insertions(+), 1 deletion(-)
Approvals:
Nick Vaccaro: Looks good to me, approved
build bot (Jenkins): Verified
Kapil Porwal: Looks good to me, approved
diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c
index 990e106..ea956a7 100644
--- a/src/soc/intel/common/block/cse/cse.c
+++ b/src/soc/intel/common/block/cse/cse.c
@@ -1418,12 +1418,28 @@
cse_final_end_of_firmware();
}
+static void intel_cse_get_rw_version(void)
+{
+ struct cse_fw_partition_info *version = cbmem_find(CBMEM_ID_CSE_PARTITION_VERSION);
+ if (version == NULL)
+ return;
+
+ printk(BIOS_DEBUG, "CSE RW Firmware Version: %d.%d.%d.%d\n",
+ version->cur_cse_fw_version.major,
+ version->cur_cse_fw_version.minor,
+ version->cur_cse_fw_version.hotfix,
+ version->cur_cse_fw_version.build);
+}
+
/*
* `cse_final` function is native implementation of equivalent events performed by
- * each FSP NotifyPhase() API invocations.
+ * each FSP NotifyPhase() API invocations. It also displays CSE firmware version
+ * if stored in CBMEM region.
*/
static void cse_final(struct device *dev)
{
+ if (CONFIG(SOC_INTEL_CSE_LITE_SKU))
+ intel_cse_get_rw_version();
/*
* SoC user can have two options for sending EOP:
* 1. Choose to send EOP late
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Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75768?usp=email )
(
4 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
)Change subject: soc/intel/cmn/cse: Always save CSE RW version to CBMEM
......................................................................
soc/intel/cmn/cse: Always save CSE RW version to CBMEM
This patch renames `cse_store_rw_fw_version` function that store
currently running CSE RW FW version inside CBMEM.
Additionally, perform the CSE RW FW storing operation unconditionally.
TEST=Able to build and boot google/marasov.
Change-Id: Iba85807b7d9e6f067b5b628c6fa062fab5c485e0
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75768
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Kangheui Won <khwon(a)chromium.org>
Reviewed-by: Kapil Porwal <kapilporwal(a)google.com>
---
M src/soc/intel/common/block/cse/cse_lite.c
1 file changed, 5 insertions(+), 5 deletions(-)
Approvals:
Kapil Porwal: Looks good to me, approved
build bot (Jenkins): Verified
Kangheui Won: Looks good to me, but someone else must approve
diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c
index 7063ecb..97f114c 100644
--- a/src/soc/intel/common/block/cse/cse_lite.c
+++ b/src/soc/intel/common/block/cse/cse_lite.c
@@ -1175,7 +1175,7 @@
* Helper function that stores current CSE firmware version to CBMEM memory,
* except during recovery mode.
*/
-static void store_cse_rw_fw_version(void)
+static void cse_store_rw_fw_version(void)
{
if (vboot_recovery_mode_enabled())
return;
@@ -1303,15 +1303,15 @@
if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE))
cse_fw_sync();
+ /* Store the CSE RW Firmware Version into CBMEM */
+ cse_store_rw_fw_version();
/*
- * Store the CSE/ISH RW Firmware Version into CBMEM if ISH partition
+ * Store the ISH RW Firmware Version into CBMEM if ISH partition
* is available
*/
if (CONFIG(SOC_INTEL_STORE_ISH_FW_VERSION) &&
- soc_is_ish_partition_enabled()) {
- store_cse_rw_fw_version();
+ soc_is_ish_partition_enabled())
store_ish_version();
- }
}
BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_EXIT, ramstage_cse_misc_ops, NULL);
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