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Change subject: meteorlake: Rename `SOC_INTEL_METEORLAKE_U_H` as per latest EDS
......................................................................
Patch Set 2: Code-Review+2
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Change subject: mb/google/brya: Add support for variant_memcfg_init()
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> Yes, they have submitted another change(CL:4623327).
so you can do the same. :p
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Change subject: mb/google/brya: Add support for variant_memcfg_init()
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> I saw lcfc already drop their change https://review.coreboot. […]
Yes, they have submitted another change(CL:4623327).
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Change subject: arch/x86/smbios: Add a config string for BIOS Vendor in SMBIOS Type 0
......................................................................
Patch Set 4:
(1 comment)
File src/Kconfig:
https://review.coreboot.org/c/coreboot/+/75737/comment/c782302a_cc199605 :
PS3, Line 896: if !SMBIOS_PROVIDED_BY_MOBO
> This only applies to fields that current mainboard code overrides, […]
Done
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Hello Angel Pons, Arthur Heymans, Eric Lai, Felix Held, Jeff Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Martin Roth, Nill Ge, Subrata Banik, Ziang Wang, build bot (Jenkins), niehaitao(a)bytedance.com,
I'd like you to reexamine a change. Please visit
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The following approvals got outdated and were removed:
Code-Review+1 by Eric Lai, Code-Review+2 by Lean Sheng Tan, Verified+1 by build bot (Jenkins)
Change subject: arch/x86/smbios: Add a config string for BIOS Vendor in SMBIOS Type 0
......................................................................
arch/x86/smbios: Add a config string for BIOS Vendor in SMBIOS Type 0
BIOS Vendor in SMBIOS Type 0 would be who built the firmware so create a
config string with default "coreboot" to make it changeable. Vendors
could update it by adding a Kconfig in the site-local directory.
Change-Id: I6dfcca338ffc48b150c966b9aefcefe928704d24
Signed-off-by: Yiwei Tang <tangyiwei.2022(a)bytedance.com>
---
M src/Kconfig
M src/arch/x86/smbios.c
2 files changed, 8 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/75737/4
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Change subject: mb/bytedance: Add 2 SPR sockets server board bd_egs
......................................................................
Patch Set 12:
(2 comments)
File src/mainboard/bytedance/bd_egs/Kconfig:
https://review.coreboot.org/c/coreboot/+/75722/comment/f28d3a72_08c298c6 :
PS10, Line 32: default "\\_SB.C%03d"
> The `acpigen` code should already add a `\\_SB.` prefix. And it's […]
Done
File src/mainboard/bytedance/bd_egs/gpio.h:
https://review.coreboot.org/c/coreboot/+/75722/comment/084eb907_3ea4878b :
PS8, Line 18: PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own))
> These macros look the same as PAD_CFG_NF_OWNERSHIP() […]
Done
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Hello Derek Huang, Tarun Tuli, YH Lin, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: mb/google/brya/var/vell: update FW_config to sync config.star
......................................................................
mb/google/brya/var/vell: update FW_config to sync config.star
We have found inconsistencies in turn of FW_CONFIG settings/definitions,
so sync setting to vell config.star
BUG=b:282189358
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot
Change-Id: I676b719ecc711a6f59e76465a3566bf63924d90f
Signed-off-by: Shon Wang <shon.wang(a)quanta.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/vell/overridetree.cb
1 file changed, 16 insertions(+), 28 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/75913/4
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Change subject: mb/bytedance: Add 2 SPR sockets server board bd_egs
......................................................................
mb/bytedance: Add 2 SPR sockets server board bd_egs
Bytedance bd_egs is a dual socket MB with Intel Sapphire Rapids
Scalable Processor chipset.
It's utilising:
- 2 SPR sockets
- Max 32 DIMMs
- 33x CPU PCIe slots
- AST2600 for VGA and BMC remote management
Test:
The board boots to Linux 5.10 with all 192 cores available.
All PCIe devices and DIMMS are working.
# sudo dmesg --level alert,crit,err,warn
[ 46.636896] netlink: 'consul': attribute type 1 has an invalid length.
Change-Id: I091bc78e39cd76b3c6b9a10a1fcf58e9d671ef5d
Co-authored-by: Jinfeng Li <lijinfeng01(a)ieisystem.com>
Co-authored-by: Long Cao <caolong01(a)inspur.com>
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Co-authored-by: Chenyu Lan <lanchenyu(a)inspur.com>
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Co-authored-by: Kehong Chen <kehong.chen(a)intel.com>
Co-authored-by: Ziang Wang <ziang.wang(a)intel.com>
Co-authored-by: Dong Wei <weidong.wd(a)bytedance.com>
Co-authored-by: Chenchen Li <lichenchen.carl(a)bytedance.com>
Signed-off-by: Yiwei Tang <tangyiwei.2022(a)bytedance.com>
Reviewed-by: Haitao Nie <niehaitao(a)bytedance.com>
Reviewed-by: Shijian Ge <geshijian(a)bytedance.com>
---
A src/mainboard/bytedance/Kconfig
A src/mainboard/bytedance/Kconfig.name
A src/mainboard/bytedance/bd_egs/Kconfig
A src/mainboard/bytedance/bd_egs/Kconfig.name
A src/mainboard/bytedance/bd_egs/Makefile.inc
A src/mainboard/bytedance/bd_egs/acpi/platform.asl
A src/mainboard/bytedance/bd_egs/board.fmd
A src/mainboard/bytedance/bd_egs/board_info.txt
A src/mainboard/bytedance/bd_egs/bootblock.c
A src/mainboard/bytedance/bd_egs/devicetree.cb
A src/mainboard/bytedance/bd_egs/dsdt.asl
A src/mainboard/bytedance/bd_egs/gpio.c
A src/mainboard/bytedance/bd_egs/gpio.h
A src/mainboard/bytedance/bd_egs/include/sprsp_bd_iio.h
A src/mainboard/bytedance/bd_egs/ramstage.c
A src/mainboard/bytedance/bd_egs/romstage.c
16 files changed, 760 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/75722/12
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Hello Derek Huang, Tarun Tuli, YH Lin, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: mb/google/brya/var/vell: update FW_config to sync config.star
......................................................................
mb/google/brya/var/vell: update FW_config to sync config.star
We have found inconsistencies in turn of FW_CONFIG settings/definitions,
so sync setting to vell config.star
BUG=b:282189358
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot
Change-Id: I676b719ecc711a6f59e76465a3566bf63924d90f
Signed-off-by: Shon Wang <shon.wang(a)quanta.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/vell/overridetree.cb
1 file changed, 12 insertions(+), 32 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/75913/3
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Hello Arthur Heymans, Christian Walter, David Hendricks, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Nico Huber, Nill Ge, Patrick Rudolph, Paul Menzel, build bot (Jenkins), niehaitao(a)bytedance.com,
I'd like you to reexamine a change. Please visit
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Change subject: mb/bytedance: Add 2 SPR sockets server board bd_egs
......................................................................
mb/bytedance: Add 2 SPR sockets server board bd_egs
Bytedance bd_egs is a dual socket MB with Intel Sapphire Rapids
Scalable Processor chipset.
It's utilising:
- 2 SPR sockets
- Max 32 DIMMs
- 33x CPU PCIe slots
- AST2600 for VGA and BMC remote management
Test:
The board boots to Linux 5.10 with all 192 cores available.
All PCIe devices and DIMMS are working.
# sudo dmesg --level alert,crit,err,warn
[ 46.636896] netlink: 'consul': attribute type 1 has an invalid length.
Change-Id: I091bc78e39cd76b3c6b9a10a1fcf58e9d671ef5d
Co-authored-by: Jinfeng Li <lijinfeng01(a)ieisystem.com>
Co-authored-by: Long Cao <caolong01(a)inspur.com>
Co-authored-by: Hao Wang <wanghao11(a)inspur.com>
Co-authored-by: Chenyu Lan <lanchenyu(a)inspur.com>
Co-authored-by: Lay Kong <lay.kong(a)intel.com>
Co-authored-by: Kehong Chen <kehong.chen(a)intel.com>
Co-authored-by: Ziang Wang <ziang.wang(a)intel.com>
Co-authored-by: Dong Wei <weidong.wd(a)bytedance.com>
Co-authored-by: Chenchen Li <lichenchen.carl(a)bytedance.com>
Signed-off-by: Yiwei Tang <tangyiwei.2022(a)bytedance.com>
Reviewed-by: Haitao Nie<niehaitao(a)bytedance.com>
Reviewed-by: Shijian Ge<geshijian(a)bytedance.com>
---
A src/mainboard/bytedance/Kconfig
A src/mainboard/bytedance/Kconfig.name
A src/mainboard/bytedance/bd_egs/Kconfig
A src/mainboard/bytedance/bd_egs/Kconfig.name
A src/mainboard/bytedance/bd_egs/Makefile.inc
A src/mainboard/bytedance/bd_egs/acpi/platform.asl
A src/mainboard/bytedance/bd_egs/board.fmd
A src/mainboard/bytedance/bd_egs/board_info.txt
A src/mainboard/bytedance/bd_egs/bootblock.c
A src/mainboard/bytedance/bd_egs/devicetree.cb
A src/mainboard/bytedance/bd_egs/dsdt.asl
A src/mainboard/bytedance/bd_egs/gpio.c
A src/mainboard/bytedance/bd_egs/gpio.h
A src/mainboard/bytedance/bd_egs/include/sprsp_bd_iio.h
A src/mainboard/bytedance/bd_egs/ramstage.c
A src/mainboard/bytedance/bd_egs/romstage.c
16 files changed, 760 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/75722/11
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