coreboot-gerrit April 2023

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[M] Change in coreboot[master]: soc/intel/meteoerlake: set power limits dynamically
by Subrata Banik (Code Review) 19 Apr '23

19 Apr '23

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[M] Change in coreboot[master]: soc/intel/meteoerlake: set power limits dynamically
by Subrata Banik (Code Review) 19 Apr '23

19 Apr '23

Attention is currently required from: Tarun Tuli, Sumeet R Pawnikar, Eric Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74380 ) Change subject: soc/intel/meteoerlake: set power limits dynamically ...................................................................... Patch Set 3: (4 comments) File src/soc/intel/meteorlake/chip.h: https://review.coreboot.org/c/coreboot/+/74380/comment/666a1fab_8bd561e6 PS2, Line 33: static const struct > As of now it's only for systemagent.c file. in that case can we move this into systemagent.c itself and use as a local data structure ? File src/soc/intel/meteorlake/systemagent.c: https://review.coreboot.org/c/coreboot/+/74380/comment/945e8d49_62849981 PS3, Line 147: configure_tdp do we expect someone will call this function outside soc_systemagent_init() ? if no, then please make it static ? https://review.coreboot.org/c/coreboot/+/74380/comment/b74ecfba_a088617c PS3, Line 170: /* Choose power limits configuration based on the CPU SA PCI ID and : * CPU TDP value. */ can u please use ``` /* * */ ``` https://review.coreboot.org/c/coreboot/+/74380/comment/21053984_e60a63ee PS3, Line 194: Ramstage ramstage? -- To view, visit https://review.coreboot.org/c/coreboot/+/74380 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20c9bc21dfa79696b07c460dbcedb4fa51838bdb Gerrit-Change-Number: 74380 Gerrit-PatchSet: 3 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Wed, 19 Apr 2023 05:48:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/dedede: Create boxy variant
by Kevin3 Yang (Code Review) 19 Apr '23

19 Apr '23

Kevin3 Yang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74535 ) Change subject: mb/google/dedede: Create boxy variant ...................................................................... mb/google/dedede: Create boxy variant Create the boxy variant of the waddledee reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:277529068 BRANCH=None TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_BOXY Change-Id: If2e1ef9d2c02e0a3888815f22267de0658fa4820 Signed-off-by: kevin3.yang <kevin3.yang(a)lcfc.corp-partner.google.com> --- M src/mainboard/google/dedede/Kconfig M src/mainboard/google/dedede/Kconfig.name A src/mainboard/google/dedede/variants/boxy/include/variant/ec.h A src/mainboard/google/dedede/variants/boxy/include/variant/gpio.h A src/mainboard/google/dedede/variants/boxy/memory/Makefile.inc A src/mainboard/google/dedede/variants/boxy/memory/dram_id.generated.txt A src/mainboard/google/dedede/variants/boxy/memory/mem_parts_used.txt A src/mainboard/google/dedede/variants/boxy/overridetree.cb 8 files changed, 102 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/74535/1 diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index ca72da1..8d427d0 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -114,6 +114,7 @@ default "Gooey" if BOARD_GOOGLE_GOOEY default "Beadrix" if BOARD_GOOGLE_BEADRIX default "Shotzo" if BOARD_GOOGLE_SHOTZO + default "Boxy" if BOARD_GOOGLE_BOXY config MAX_CPUS int @@ -154,6 +155,7 @@ default "gooey" if BOARD_GOOGLE_GOOEY default "beadrix" if BOARD_GOOGLE_BEADRIX default "shotzo" if BOARD_GOOGLE_SHOTZO + default "Boxy" if BOARD_GOOGLE_BOXY endif #BOARD_GOOGLE_BASEBOARD_DEDEDE diff --git a/src/mainboard/google/dedede/Kconfig.name b/src/mainboard/google/dedede/Kconfig.name index eb69198..9123993 100644 --- a/src/mainboard/google/dedede/Kconfig.name +++ b/src/mainboard/google/dedede/Kconfig.name @@ -201,3 +201,8 @@ config BOARD_GOOGLE_SHOTZO bool "-> Shotzo" select BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50 + +config BOARD_GOOGLE_BOXY + bool "-> Boxy" + select BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50 + select BASEBOARD_DEDEDE_LAPTOP diff --git a/src/mainboard/google/dedede/variants/boxy/include/variant/ec.h b/src/mainboard/google/dedede/variants/boxy/include/variant/ec.h new file mode 100644 index 0000000..08870e0 --- /dev/null +++ b/src/mainboard/google/dedede/variants/boxy/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/dedede/variants/boxy/include/variant/gpio.h b/src/mainboard/google/dedede/variants/boxy/include/variant/gpio.h new file mode 100644 index 0000000..9078664 --- /dev/null +++ b/src/mainboard/google/dedede/variants/boxy/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include <baseboard/gpio.h> + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/dedede/variants/boxy/memory/Makefile.inc b/src/mainboard/google/dedede/variants/boxy/memory/Makefile.inc new file mode 100644 index 0000000..eace2e4 --- /dev/null +++ b/src/mainboard/google/dedede/variants/boxy/memory/Makefile.inc @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. + +SPD_SOURCES = placeholder diff --git a/src/mainboard/google/dedede/variants/boxy/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/boxy/memory/dram_id.generated.txt new file mode 100644 index 0000000..fa24790 --- /dev/null +++ b/src/mainboard/google/dedede/variants/boxy/memory/dram_id.generated.txt @@ -0,0 +1 @@ +DRAM Part Name ID to assign diff --git a/src/mainboard/google/dedede/variants/boxy/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/boxy/memory/mem_parts_used.txt new file mode 100644 index 0000000..9621137 --- /dev/null +++ b/src/mainboard/google/dedede/variants/boxy/memory/mem_parts_used.txt @@ -0,0 +1,11 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# part_id_gen tool from util/spd_tools. +# See util/spd_tools/README.md for more details and instructions. + +# Part Name diff --git a/src/mainboard/google/dedede/variants/boxy/overridetree.cb b/src/mainboard/google/dedede/variants/boxy/overridetree.cb new file mode 100644 index 0000000..404024b --- /dev/null +++ b/src/mainboard/google/dedede/variants/boxy/overridetree.cb @@ -0,0 +1,42 @@ +chip soc/intel/jasperlake + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | Trackpad | + #| I2C1 | Digitizer | + #| I2C2 | Touchscreen | + #| I2C3 | Camera | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + }, + }" + + device domain 0 on + device pci 15.0 on end + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/74535 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If2e1ef9d2c02e0a3888815f22267de0658fa4820 Gerrit-Change-Number: 74535 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin3 Yang <kevin3.yang(a)lcfc.corp-partner.google.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: mb/google/myst: Enable PCIe devices in devicetree
by Karthik Ramasubramanian (Code Review) 19 Apr '23

19 Apr '23

Attention is currently required from: Raul Rangel, Martin L Roth, Jon Murphy, Tim Van Patten, Felix Held. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74112 ) Change subject: mb/google/myst: Enable PCIe devices in devicetree ...................................................................... Patch Set 38: Code-Review+2 (1 comment) File src/mainboard/google/myst/port_descriptors.c: https://review.coreboot.org/c/coreboot/+/74112/comment/31e97fe6_b23b1156 PS36, Line 44: { /* SSD TODO(b/277815815): Enable PCIe GEN4 when supported */ > We do use the bridge, our option is BH799BB. go/bayhub-reference. […] A FW_config bit does not hurt to indicate whether it is a eMMC or NVME SKU. In Whiterun and Markarth, we used the state of CLK_REQ line to detect the SKU. Even though it is working now, I am also seeing some SSD devices not driving the CLK_REQ line to low as expected. From that standpoint, FW_CONFIG bit will provide a deterministic way of identifying the storage type even if the storage device is not behaving as expected. -- To view, visit https://review.coreboot.org/c/coreboot/+/74112 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icdad785bcb90de036095bcc4219c15f55f4277fe Gerrit-Change-Number: 74112 Gerrit-PatchSet: 38 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 19 Apr 2023 05:46:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Jon Murphy <jpmurphy(a)google.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/meteoerlake: set power limits dynamically
by Sumeet R Pawnikar (Code Review) 19 Apr '23

19 Apr '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Eric Lai. Hello build bot (Jenkins), Tarun Tuli, Subrata Banik, Kapil Porwal, Eric Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74380 to look at the new patch set (#3). Change subject: soc/intel/meteoerlake: set power limits dynamically ...................................................................... soc/intel/meteoerlake: set power limits dynamically Set power limit values dynamically based on Meteor Lake CPU TDP and PCI ID of SKU. BRANCH=None BUG=b:270664854 TEST=Built and verified power limit values for 15W SKU on Rex board Change-Id: I20c9bc21dfa79696b07c460dbcedb4fa51838bdb Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/soc/intel/common/block/include/intelblocks/systemagent.h M src/soc/intel/meteorlake/chip.h M src/soc/intel/meteorlake/chipset.cb M src/soc/intel/meteorlake/systemagent.c 4 files changed, 79 insertions(+), 44 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/74380/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/74380 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20c9bc21dfa79696b07c460dbcedb4fa51838bdb Gerrit-Change-Number: 74380 Gerrit-PatchSet: 3 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: soc/intel/meteoerlake: set power limits dynamically
by Sumeet R Pawnikar (Code Review) 19 Apr '23

19 Apr '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Eric Lai. Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74380 ) Change subject: soc/intel/meteoerlake: set power limits dynamically ...................................................................... Patch Set 2: (5 comments) File src/soc/intel/meteorlake/chip.h: https://review.coreboot.org/c/coreboot/+/74380/comment/bc9300ee_37180bbf PS2, Line 33: static const struct > wondering if u have more consumers of this data structure beyond systemagent. […] As of now it's only for systemagent.c file. File src/soc/intel/meteorlake/systemagent.c: https://review.coreboot.org/c/coreboot/+/74380/comment/7fce6765_bdec0d61 PS2, Line 152: soc_systemagent_init > i would have refactored this code as below […] Done https://review.coreboot.org/c/coreboot/+/74380/comment/cafa50fc_7346e749 PS2, Line 168: 0xFFFF > shouldn't we skip the below operations if ID is 0xFFFF? what is the point of running into the `for` […] Ack https://review.coreboot.org/c/coreboot/+/74380/comment/7fdd7a99_3879fdde PS2, Line 183: if (i == ARRAY_SIZE(cpuid_to_mtl)) { > can u use a bool to know if config_tdp is successful ? Let me modify the code accordingly and submit next version. https://review.coreboot.org/c/coreboot/+/74380/comment/514145f8_732618fb PS2, Line 188: printk(BIOS_DEBUG, "Configured power limits for SA ID: 0x%4x\n", sa_pci_id); > please move this line into line#178 to avoid a else case here. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/74380 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20c9bc21dfa79696b07c460dbcedb4fa51838bdb Gerrit-Change-Number: 74380 Gerrit-PatchSet: 2 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Wed, 19 Apr 2023 05:44:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google,intel,samsung: Use common poweroff()
by Kyösti Mälkki (Code Review) 19 Apr '23

19 Apr '23

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74515 ) Change subject: mb/google,intel,samsung: Use common poweroff() ...................................................................... mb/google,intel,samsung: Use common poweroff() Change-Id: I3881c152663a038833d8126d7f24f2a6688426d1 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/google/parrot/smihandler.c M src/mainboard/google/stout/smihandler.c M src/mainboard/samsung/lumpy/smihandler.c 3 files changed, 17 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/74515/1 diff --git a/src/mainboard/google/parrot/smihandler.c b/src/mainboard/google/parrot/smihandler.c index 05f14af..8d54dec 100644 --- a/src/mainboard/google/parrot/smihandler.c +++ b/src/mainboard/google/parrot/smihandler.c @@ -2,11 +2,10 @@ #include <console/console.h> #include <cpu/x86/smm.h> +#include <halt.h> #include <soc/nvs.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/me.h> -#include <southbridge/intel/common/pmutil.h> -#include <southbridge/intel/common/pmbase.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <ec/compal/ene932/ec.h> #include "ec.h" @@ -26,7 +25,7 @@ printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n"); /* Go to S5 */ - write_pmbase32(PM1_CNT, read_pmbase32(PM1_CNT) | (0xf << 10)); + poweroff(); break; } @@ -42,7 +41,7 @@ printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n"); /* Go to S5 */ - write_pmbase32(PM1_CNT, read_pmbase32(PM1_CNT) | (0xf << 10)); + poweroff(); } } diff --git a/src/mainboard/google/stout/smihandler.c b/src/mainboard/google/stout/smihandler.c index f6adbf9..30637ab 100644 --- a/src/mainboard/google/stout/smihandler.c +++ b/src/mainboard/google/stout/smihandler.c @@ -3,10 +3,10 @@ #include <device/pci_ops.h> #include <console/console.h> #include <cpu/x86/smm.h> +#include <halt.h> #include <soc/nvs.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/me.h> -#include <southbridge/intel/common/pmbase.h> #include <northbridge/intel/sandybridge/sandybridge.h> /* Include EC functions */ @@ -21,7 +21,7 @@ case EC_SMI_LID_CLOSED: printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n"); /* Go to S5 */ - write_pmbase32(PM1_CNT, read_pmbase32(PM1_CNT) | (0xf << 10)); + poweroff(); break; } diff --git a/src/mainboard/samsung/lumpy/smihandler.c b/src/mainboard/samsung/lumpy/smihandler.c index 1c7d626..d6c8978 100644 --- a/src/mainboard/samsung/lumpy/smihandler.c +++ b/src/mainboard/samsung/lumpy/smihandler.c @@ -2,9 +2,9 @@ #include <console/console.h> #include <cpu/x86/smm.h> +#include <halt.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/me.h> -#include <southbridge/intel/common/pmbase.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <ec/smsc/mec1308/ec.h> #include "ec.h" @@ -20,7 +20,7 @@ printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n"); /* Go to S5 */ - write_pmbase32(PM1_CNT, read_pmbase32(PM1_CNT) | (0xf << 10)); + poweroff(); break; } -- To view, visit https://review.coreboot.org/c/coreboot/+/74515 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3881c152663a038833d8126d7f24f2a6688426d1 Gerrit-Change-Number: 74515 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: mb/google,intel: Use common ChromeEC code for lid shutdown
by Kyösti Mälkki (Code Review) 19 Apr '23

19 Apr '23

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74514 ) Change subject: mb/google,intel: Use common ChromeEC code for lid shutdown ...................................................................... mb/google,intel: Use common ChromeEC code for lid shutdown Change-Id: I4d34e5c094440dad4a6ab9adc67d3da6b71ac2bf Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/google/auron/smihandler.c M src/mainboard/google/cyan/smihandler.c M src/mainboard/google/link/smihandler.c M src/mainboard/google/rambi/smihandler.c M src/mainboard/google/slippy/smihandler.c M src/mainboard/intel/strago/smihandler.c M src/soc/intel/braswell/pmutil.c M src/soc/intel/broadwell/pch/pmutil.c M src/southbridge/intel/common/pmbase.c M src/southbridge/intel/lynxpoint/pmutil.c 10 files changed, 66 insertions(+), 177 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/74514/1 diff --git a/src/mainboard/google/auron/smihandler.c b/src/mainboard/google/auron/smihandler.c index 42ab937..237a2b3 100644 --- a/src/mainboard/google/auron/smihandler.c +++ b/src/mainboard/google/auron/smihandler.c @@ -1,11 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> -#include <arch/io.h> #include <console/console.h> #include <cpu/x86/smm.h> #include <soc/pm.h> -#include <elog.h> #include <ec/google/chromeec/ec.h> #include <ec/google/chromeec/smm.h> #include <southbridge/intel/lynxpoint/lp_gpio.h> @@ -14,37 +12,11 @@ #include "ec.h" #include <variant/onboard.h> -static u8 mainboard_smi_ec(void) -{ - u8 cmd = google_chromeec_get_event(); - u32 pm1_cnt; - - /* Log this event */ - if (cmd) - elog_gsmi_add_event_byte(ELOG_TYPE_EC_EVENT, cmd); - - switch (cmd) { - case EC_HOST_EVENT_LID_CLOSED: - printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n"); - - /* Go to S5 */ - pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); - pm1_cnt |= (0xf << 10); - outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT); - break; - } - - return cmd; -} - /* gpi_sts is GPIO 47:32 */ void mainboard_smi_gpi(u32 gpi_sts) { - if (gpi_sts & (1 << (EC_SMI_GPI - 32))) { - /* Process all pending events */ - while (mainboard_smi_ec() != 0) - ; - } + if (gpi_sts & (1 << (EC_SMI_GPI - 32))) + chromeec_smi_process_events(); } static void mainboard_disable_gpios(void) diff --git a/src/mainboard/google/cyan/smihandler.c b/src/mainboard/google/cyan/smihandler.c index 65daab4..8f06cf4 100644 --- a/src/mainboard/google/cyan/smihandler.c +++ b/src/mainboard/google/cyan/smihandler.c @@ -1,14 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> -#include <arch/io.h> #include <device/mmio.h> #include <console/console.h> #include <cpu/x86/smm.h> #include "ec.h" #include <ec/google/chromeec/ec.h> #include <ec/google/chromeec/smm.h> -#include <elog.h> #include <soc/nvs.h> #include <soc/pm.h> #include <soc/gpio.h> @@ -20,41 +18,14 @@ #define GPIO_SUS7_WAKE_MASK (1 << 12) #define GPIO_SUS1_WAKE_MASK (1 << 13) -static uint8_t mainboard_smi_ec(void) -{ - uint8_t cmd = google_chromeec_get_event(); - uint16_t pmbase = get_pmbase(); - uint32_t pm1_cnt; - - /* Log this event */ - if (cmd) - elog_gsmi_add_event_byte(ELOG_TYPE_EC_EVENT, cmd); - - switch (cmd) { - case EC_HOST_EVENT_LID_CLOSED: - printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n"); - - /* Go to S5 */ - pm1_cnt = inl(pmbase + PM1_CNT); - pm1_cnt |= SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT); - outl(pm1_cnt, pmbase + PM1_CNT); - break; - } - - return cmd; -} - /* * The entire 32-bit ALT_GPIO_SMI register is passed as a parameter. Note, that * this includes the enable bits in the lower 16 bits. */ void mainboard_smi_gpi(uint32_t alt_gpio_smi) { - if (alt_gpio_smi & (1 << EC_SMI_GPI)) { - /* Process all pending events */ - while (mainboard_smi_ec() != 0) - ; - } + if (alt_gpio_smi & (1 << EC_SMI_GPI)) + chromeec_smi_process_events(); } void mainboard_smi_sleep(uint8_t slp_typ) diff --git a/src/mainboard/google/link/smihandler.c b/src/mainboard/google/link/smihandler.c index 0570e2c..4a9dfb0 100644 --- a/src/mainboard/google/link/smihandler.c +++ b/src/mainboard/google/link/smihandler.c @@ -6,41 +6,17 @@ #include <soc/nvs.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/me.h> -#include <southbridge/intel/common/pmbase.h> #include <northbridge/intel/sandybridge/sandybridge.h> -#include <elog.h> /* Include EC functions */ #include <ec/google/chromeec/ec.h> #include <ec/google/chromeec/smm.h> #include "ec.h" -static u8 mainboard_smi_ec(void) -{ - u8 cmd = google_chromeec_get_event(); - - /* Log this event */ - if (cmd) - elog_gsmi_add_event_byte(ELOG_TYPE_EC_EVENT, cmd); - - switch (cmd) { - case EC_HOST_EVENT_LID_CLOSED: - printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n"); - - /* Go to S5 */ - write_pmbase32(PM1_CNT, read_pmbase32(PM1_CNT) | (0xf << 10)); - break; - } - - return cmd; -} - void mainboard_smi_gpi(u32 gpi_sts) { - if (gpi_sts & (1 << EC_SMI_GPI)) { - /* Process all pending events */ - while (mainboard_smi_ec() != 0); - } + if (gpi_sts & (1 << EC_SMI_GPI)) + chromeec_smi_process_events(); } void mainboard_smi_sleep(u8 slp_typ) diff --git a/src/mainboard/google/rambi/smihandler.c b/src/mainboard/google/rambi/smihandler.c index 29dc8b2..3eb1d1d 100644 --- a/src/mainboard/google/rambi/smihandler.c +++ b/src/mainboard/google/rambi/smihandler.c @@ -1,10 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> -#include <arch/io.h> #include <console/console.h> #include <cpu/x86/smm.h> -#include <elog.h> #include <ec/google/chromeec/ec.h> #include <ec/google/chromeec/smm.h> @@ -16,38 +14,12 @@ /* The wake gpio is SUS_GPIO[0]. */ #define WAKE_GPIO_EN SUS_GPIO_EN0 -static uint8_t mainboard_smi_ec(void) -{ - uint8_t cmd = google_chromeec_get_event(); - uint16_t pmbase = get_pmbase(); - uint32_t pm1_cnt; - - /* Log this event */ - if (cmd) - elog_gsmi_add_event_byte(ELOG_TYPE_EC_EVENT, cmd); - - switch (cmd) { - case EC_HOST_EVENT_LID_CLOSED: - printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n"); - - /* Go to S5 */ - pm1_cnt = inl(pmbase + PM1_CNT); - pm1_cnt |= SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT); - outl(pm1_cnt, pmbase + PM1_CNT); - break; - } - - return cmd; -} - /* The entire 32-bit ALT_GPIO_SMI register is passed as a parameter. Note, that * this includes the enable bits in the lower 16 bits. */ void mainboard_smi_gpi(uint32_t alt_gpio_smi) { - if (alt_gpio_smi & (1 << EC_SMI_GPI)) { - /* Process all pending events */ - while (mainboard_smi_ec() != 0); - } + if (alt_gpio_smi & (1 << EC_SMI_GPI)) + chromeec_smi_process_events(); } void mainboard_smi_sleep(uint8_t slp_typ) diff --git a/src/mainboard/google/slippy/smihandler.c b/src/mainboard/google/slippy/smihandler.c index f02ee40..71e97af 100644 --- a/src/mainboard/google/slippy/smihandler.c +++ b/src/mainboard/google/slippy/smihandler.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> -#include <arch/io.h> #include <console/console.h> #include <cpu/x86/smm.h> #include <soc/nvs.h> @@ -10,7 +9,6 @@ #include <southbridge/intel/lynxpoint/me.h> #include <northbridge/intel/haswell/haswell.h> #include <cpu/intel/haswell/haswell.h> -#include <elog.h> /* Include EC functions */ #include <ec/google/chromeec/ec.h> @@ -23,36 +21,11 @@ #define GPIO_WLAN_DISABLE_L 46 #define GPIO_LTE_DISABLE_L 59 -static u8 mainboard_smi_ec(void) -{ - u8 cmd = google_chromeec_get_event(); - u32 pm1_cnt; - - /* Log this event */ - if (cmd) - elog_gsmi_add_event_byte(ELOG_TYPE_EC_EVENT, cmd); - - switch (cmd) { - case EC_HOST_EVENT_LID_CLOSED: - printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n"); - - /* Go to S5 */ - pm1_cnt = inl(get_pmbase() + PM1_CNT); - pm1_cnt |= (0xf << 10); - outl(pm1_cnt, get_pmbase() + PM1_CNT); - break; - } - - return cmd; -} - /* gpi_sts is GPIO 47:32 */ void mainboard_smi_gpi(u32 gpi_sts) { - if (gpi_sts & (1 << (EC_SMI_GPI - 32))) { - /* Process all pending events */ - while (mainboard_smi_ec() != 0); - } + if (gpi_sts & (1 << (EC_SMI_GPI - 32))) + chromeec_smi_process_events(); } void mainboard_smi_sleep(u8 slp_typ) diff --git a/src/mainboard/intel/strago/smihandler.c b/src/mainboard/intel/strago/smihandler.c index f8f7c57..a625b62 100644 --- a/src/mainboard/intel/strago/smihandler.c +++ b/src/mainboard/intel/strago/smihandler.c @@ -1,14 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> -#include <arch/io.h> #include <console/console.h> #include <cpu/x86/smm.h> #include "ec.h" #include <ec/google/chromeec/ec.h> #include <ec/google/chromeec/smm.h> -#include <elog.h> #include <soc/nvs.h> #include <soc/pm.h> @@ -19,41 +17,14 @@ /* The wake gpio is SUS_GPIO[0]. */ #define WAKE_GPIO_EN SUS_GPIO_EN0 -static uint8_t mainboard_smi_ec(void) -{ - uint8_t cmd = google_chromeec_get_event(); - uint16_t pmbase = get_pmbase(); - uint32_t pm1_cnt; - - /* Log this event */ - if (cmd) - elog_gsmi_add_event_byte(ELOG_TYPE_EC_EVENT, cmd); - - switch (cmd) { - case EC_HOST_EVENT_LID_CLOSED: - printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n"); - - /* Go to S5 */ - pm1_cnt = inl(pmbase + PM1_CNT); - pm1_cnt |= SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT); - outl(pm1_cnt, pmbase + PM1_CNT); - break; - } - - return cmd; -} - /* * The entire 32-bit ALT_GPIO_SMI register is passed as a parameter. Note, that * this includes the enable bits in the lower 16 bits. */ void mainboard_smi_gpi(uint32_t alt_gpio_smi) { - if (alt_gpio_smi & (1 << EC_SMI_GPI)) { - /* Process all pending events */ - while (mainboard_smi_ec() != 0) - ; - } + if (alt_gpio_smi & (1 << EC_SMI_GPI)) + chromeec_smi_process_events(); } void mainboard_smi_sleep(uint8_t slp_typ) diff --git a/src/soc/intel/braswell/pmutil.c b/src/soc/intel/braswell/pmutil.c index a880183..3efcc7b 100644 --- a/src/soc/intel/braswell/pmutil.c +++ b/src/soc/intel/braswell/pmutil.c @@ -10,6 +10,7 @@ #include <device/mmio.h> #include <device/pci.h> #include <device/pci_ops.h> +#include <halt.h> #include <console/console.h> #include <soc/iomap.h> #include <soc/lpc.h> @@ -356,3 +357,13 @@ return acpi_sleep_from_pm1(inl(ACPI_BASE_ADDRESS + PM1_CNT)) == ACPI_S3; } + +void poweroff(void) +{ + uint32_t pm1_cnt; + + /* Go to S5 */ + pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); + pm1_cnt |= (0xf << 10); + outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT); +} diff --git a/src/soc/intel/broadwell/pch/pmutil.c b/src/soc/intel/broadwell/pch/pmutil.c index 4ba30b4..e310416e 100644 --- a/src/soc/intel/broadwell/pch/pmutil.c +++ b/src/soc/intel/broadwell/pch/pmutil.c @@ -11,6 +11,7 @@ #include <device/pci_ops.h> #include <device/device.h> #include <device/pci.h> +#include <halt.h> #include <console/console.h> #include <soc/iomap.h> #include <soc/lpc.h> @@ -421,6 +422,16 @@ return acpi_sleep_from_pm1(inl(get_pmbase() + PM1_CNT)) == ACPI_S3; } +void poweroff(void) +{ + uint32_t pm1_cnt; + + /* Go to S5 */ + pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); + pm1_cnt |= (0xf << 10); + outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT); +} + /* STM Support */ uint16_t get_pmbase(void) { diff --git a/src/southbridge/intel/common/pmbase.c b/src/southbridge/intel/common/pmbase.c index 2fddfc9..8a30c08 100644 --- a/src/southbridge/intel/common/pmbase.c +++ b/src/southbridge/intel/common/pmbase.c @@ -6,6 +6,7 @@ #include <bootmode.h> #include <device/pci_ops.h> #include <device/pci_type.h> +#include <halt.h> #include <stdint.h> #include "pmbase.h" @@ -92,3 +93,13 @@ return acpi_get_sleep_type() == ACPI_S3; } + +void poweroff(void) +{ + uint32_t pm1_cnt; + + /* Go to S5 */ + pm1_cnt = read_pmbase32(PM1_CNT); + pm1_cnt |= (0xf << 10); + write_pmbase32(PM1_CNT, pm1_cnt); +} diff --git a/src/southbridge/intel/lynxpoint/pmutil.c b/src/southbridge/intel/lynxpoint/pmutil.c index d67fb6c..16ac0c4 100644 --- a/src/southbridge/intel/lynxpoint/pmutil.c +++ b/src/southbridge/intel/lynxpoint/pmutil.c @@ -9,6 +9,7 @@ #include <device/device.h> #include <device/pci.h> #include <console/console.h> +#include <halt.h> #include <security/vboot/vbnv.h> #include <security/vboot/vboot_common.h> #include <southbridge/intel/common/rtc.h> @@ -76,6 +77,16 @@ outl(pm1_cnt, get_pmbase() + PM1_CNT); } +void poweroff(void) +{ + uint32_t pm1_cnt; + + /* Go to S5 */ + pm1_cnt = inl(get_pmbase() + PM1_CNT); + pm1_cnt |= (0xf << 10); + outl(pm1_cnt, get_pmbase() + PM1_CNT); +} + /* * PM1 */ -- To view, visit https://review.coreboot.org/c/coreboot/+/74514 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d34e5c094440dad4a6ab9adc67d3da6b71ac2bf Gerrit-Change-Number: 74514 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[master]: mb/google,intel: Use common ChromeEC code for SMI APMC
by Kyösti Mälkki (Code Review) 19 Apr '23

19 Apr '23

Kyösti Mälkki has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/74513 ) Change subject: mb/google,intel: Use common ChromeEC code for SMI APMC ...................................................................... mb/google,intel: Use common ChromeEC code for SMI APMC Change-Id: If4b7c2b94e0fec84831740336ccdbea0922ffbfe Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/google/auron/smihandler.c M src/mainboard/google/cyan/smihandler.c M src/mainboard/google/link/smihandler.c M src/mainboard/google/rambi/smihandler.c M src/mainboard/google/slippy/smihandler.c M src/mainboard/intel/strago/smihandler.c 6 files changed, 22 insertions(+), 96 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/74513/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74513 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4b7c2b94e0fec84831740336ccdbea0922ffbfe Gerrit-Change-Number: 74513 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

[M] Change in coreboot[master]: mb/google,intel: Use common ChromeEC code for SMI APMC
by Kyösti Mälkki (Code Review) 19 Apr '23

19 Apr '23

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74513 ) Change subject: mb/google,intel: Use common ChromeEC code for SMI APMC ...................................................................... mb/google,intel: Use common ChromeEC code for SMI APMC Change-Id: If4b7c2b94e0fec84831740336ccdbea0922ffbfe Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/google/auron/smihandler.c M src/mainboard/google/cyan/smihandler.c M src/mainboard/google/link/smihandler.c M src/mainboard/google/rambi/smihandler.c M src/mainboard/google/slippy/smihandler.c M src/mainboard/intel/strago/smihandler.c 6 files changed, 22 insertions(+), 96 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/74513/1 diff --git a/src/mainboard/google/auron/smihandler.c b/src/mainboard/google/auron/smihandler.c index 6fa95e8..42ab937 100644 --- a/src/mainboard/google/auron/smihandler.c +++ b/src/mainboard/google/auron/smihandler.c @@ -7,6 +7,7 @@ #include <soc/pm.h> #include <elog.h> #include <ec/google/chromeec/ec.h> +#include <ec/google/chromeec/smm.h> #include <southbridge/intel/lynxpoint/lp_gpio.h> #include <soc/iomap.h> #include <soc/nvs.h> @@ -103,21 +104,6 @@ int mainboard_smi_apmc(u8 apmc) { - switch (apmc) { - case APM_CNT_ACPI_ENABLE: - google_chromeec_set_smi_mask(0); - /* Clear all pending events */ - while (google_chromeec_get_event() != EC_HOST_EVENT_NONE) - ; - google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS); - break; - case APM_CNT_ACPI_DISABLE: - google_chromeec_set_sci_mask(0); - /* Clear all pending events */ - while (google_chromeec_get_event() != EC_HOST_EVENT_NONE) - ; - google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS); - break; - } + chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, MAINBOARD_EC_SMI_EVENTS); return 0; } diff --git a/src/mainboard/google/cyan/smihandler.c b/src/mainboard/google/cyan/smihandler.c index 7394b78..65daab4 100644 --- a/src/mainboard/google/cyan/smihandler.c +++ b/src/mainboard/google/cyan/smihandler.c @@ -7,6 +7,7 @@ #include <cpu/x86/smm.h> #include "ec.h" #include <ec/google/chromeec/ec.h> +#include <ec/google/chromeec/smm.h> #include <elog.h> #include <soc/nvs.h> #include <soc/pm.h> @@ -115,21 +116,6 @@ int mainboard_smi_apmc(uint8_t apmc) { - switch (apmc) { - case APM_CNT_ACPI_ENABLE: - google_chromeec_set_smi_mask(0); - /* Clear all pending events */ - while (google_chromeec_get_event() != EC_HOST_EVENT_NONE) - ; - google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS); - break; - case APM_CNT_ACPI_DISABLE: - google_chromeec_set_sci_mask(0); - /* Clear all pending events */ - while (google_chromeec_get_event() != EC_HOST_EVENT_NONE) - ; - google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS); - break; - } + chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, MAINBOARD_EC_SMI_EVENTS); return 0; } diff --git a/src/mainboard/google/link/smihandler.c b/src/mainboard/google/link/smihandler.c index 2f42b7d..fb596b6 100644 --- a/src/mainboard/google/link/smihandler.c +++ b/src/mainboard/google/link/smihandler.c @@ -12,6 +12,7 @@ /* Include EC functions */ #include <ec/google/chromeec/ec.h> +#include <ec/google/chromeec/smm.h> #include "ec.h" static u8 mainboard_smi_ec(void) @@ -78,21 +79,6 @@ int mainboard_smi_apmc(u8 apmc) { - switch (apmc) { - case APM_CNT_ACPI_ENABLE: - google_chromeec_set_smi_mask(0); - /* Clear all pending events */ - while (google_chromeec_get_event() != EC_HOST_EVENT_NONE) - ; - google_chromeec_set_sci_mask(LINK_EC_SCI_EVENTS); - break; - case APM_CNT_ACPI_DISABLE: - google_chromeec_set_sci_mask(0); - /* Clear all pending events */ - while (google_chromeec_get_event() != EC_HOST_EVENT_NONE) - ; - google_chromeec_set_smi_mask(LINK_EC_SMI_EVENTS); - break; - } + chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, MAINBOARD_EC_SMI_EVENTS); return 0; } diff --git a/src/mainboard/google/rambi/smihandler.c b/src/mainboard/google/rambi/smihandler.c index 358a92f..29dc8b2 100644 --- a/src/mainboard/google/rambi/smihandler.c +++ b/src/mainboard/google/rambi/smihandler.c @@ -7,6 +7,7 @@ #include <elog.h> #include <ec/google/chromeec/ec.h> +#include <ec/google/chromeec/smm.h> #include "ec.h" #include <soc/nvs.h> @@ -90,21 +91,6 @@ int mainboard_smi_apmc(uint8_t apmc) { - switch (apmc) { - case APM_CNT_ACPI_ENABLE: - google_chromeec_set_smi_mask(0); - /* Clear all pending events */ - while (google_chromeec_get_event() != EC_HOST_EVENT_NONE) - ; - google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS); - break; - case APM_CNT_ACPI_DISABLE: - google_chromeec_set_sci_mask(0); - /* Clear all pending events */ - while (google_chromeec_get_event() != EC_HOST_EVENT_NONE) - ; - google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS); - break; - } + chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, MAINBOARD_EC_SMI_EVENTS); return 0; } diff --git a/src/mainboard/google/slippy/smihandler.c b/src/mainboard/google/slippy/smihandler.c index 16a1b18..f02ee40 100644 --- a/src/mainboard/google/slippy/smihandler.c +++ b/src/mainboard/google/slippy/smihandler.c @@ -14,6 +14,7 @@ /* Include EC functions */ #include <ec/google/chromeec/ec.h> +#include <ec/google/chromeec/smm.h> #include "ec.h" /* Codec enable: GPIO45 */ @@ -106,21 +107,6 @@ int mainboard_smi_apmc(u8 apmc) { - switch (apmc) { - case APM_CNT_ACPI_ENABLE: - google_chromeec_set_smi_mask(0); - /* Clear all pending events */ - while (google_chromeec_get_event() != EC_HOST_EVENT_NONE) - ; - google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS); - break; - case APM_CNT_ACPI_DISABLE: - google_chromeec_set_sci_mask(0); - /* Clear all pending events */ - while (google_chromeec_get_event() != EC_HOST_EVENT_NONE) - ; - google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS); - break; - } + chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, MAINBOARD_EC_SMI_EVENTS); return 0; } diff --git a/src/mainboard/intel/strago/smihandler.c b/src/mainboard/intel/strago/smihandler.c index c660e5a..f8f7c57 100644 --- a/src/mainboard/intel/strago/smihandler.c +++ b/src/mainboard/intel/strago/smihandler.c @@ -7,6 +7,7 @@ #include "ec.h" #include <ec/google/chromeec/ec.h> +#include <ec/google/chromeec/smm.h> #include <elog.h> #include <soc/nvs.h> @@ -100,21 +101,6 @@ int mainboard_smi_apmc(uint8_t apmc) { - switch (apmc) { - case APM_CNT_ACPI_ENABLE: - google_chromeec_set_smi_mask(0); - /* Clear all pending events */ - while (google_chromeec_get_event() != EC_HOST_EVENT_NONE) - ; - google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS); - break; - case APM_CNT_ACPI_DISABLE: - google_chromeec_set_sci_mask(0); - /* Clear all pending events */ - while (google_chromeec_get_event() != EC_HOST_EVENT_NONE) - ; - google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS); - break; - } + chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, MAINBOARD_EC_SMI_EVENTS); return 0; } -- To view, visit https://review.coreboot.org/c/coreboot/+/74513 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4b7c2b94e0fec84831740336ccdbea0922ffbfe Gerrit-Change-Number: 74513 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit April 2023