coreboot-gerrit April 2023

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[S] Change in coreboot[master]: mb/prodrive/atlas: Enable/disable sleep states based on EC
by Arthur Heymans (Code Review) 25 Apr '23

25 Apr '23

Attention is currently required from: Lance Zhao, Tim Wawrzynczak, Christian Walter, Angel Pons, Arthur Heymans, Lean Sheng Tan. Hello Lance Zhao, build bot (Jenkins), Tim Wawrzynczak, Christian Walter, Angel Pons, Lean Sheng Tan, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74421 to look at the new patch set (#3). Change subject: mb/prodrive/atlas: Enable/disable sleep states based on EC ...................................................................... mb/prodrive/atlas: Enable/disable sleep states based on EC With the profile ATLAS_PROF_REALTIME_PERFORMANCE it is desired to not have the option to be able to sleep, the reason being that windows goes to sleep after 30min of inactivity. Change-Id: I424db7e712a705c628aa3a10a486d3313404987a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/prodrive/atlas/Kconfig M src/mainboard/prodrive/atlas/mainboard.c 2 files changed, 25 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/74421/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/74421 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I424db7e712a705c628aa3a10a486d3313404987a Gerrit-Change-Number: 74421 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/amd/mendocino: Add FSP parameter for eDP power sequence adjustment
by build bot (Jenkins) (Code Review) 25 Apr '23

25 Apr '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74758 ) Change subject: soc/amd/mendocino: Add FSP parameter for eDP power sequence adjustment ...................................................................... Patch Set 1: (1 comment) File src/soc/amd/mendocino/fsp_m_params.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174922): https://review.coreboot.org/c/coreboot/+/74758/comment/c54fcba8_192974b1 PS1, Line 174: mcfg->pwr_down_bloff_to_varybloff = config-> pwr_down_bloff_to_varybloff; spaces prohibited around that '->' (ctx:VxW) -- To view, visit https://review.coreboot.org/c/coreboot/+/74758 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdf50db12d982b45edca205e8f4612deb702453d Gerrit-Change-Number: 74758 Gerrit-PatchSet: 1 Gerrit-Owner: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 25 Apr 2023 14:31:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/skyrim/var/winterhold: adjust the eDP panel power sequence
by Chris Wang (Code Review) 25 Apr '23

25 Apr '23

Attention is currently required from: Jason Nien, Martin Roth. Chris Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74759 ) Change subject: mb/google/skyrim/var/winterhold: adjust the eDP panel power sequence ...................................................................... mb/google/skyrim/var/winterhold: adjust the eDP panel power sequence set pwr_down_bloff_to_varybloff to 0x2, which means fw will delay 8ms between backlight off to vary blacklgiht off. BUG=b:271704149 BRANCH=none TEST=Build; Verify the UPD was passed to system integrated table. Signed-off-by: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Change-Id: Ifefd47a86e53d574098ae2e5bd2f41ae79353385 --- M src/mainboard/google/skyrim/variants/winterhold/overridetree.cb 1 file changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/74759/1 diff --git a/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb b/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb index 4297f90..1606f2b 100644 --- a/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb +++ b/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb @@ -114,6 +114,7 @@ # The unit is set to one per 4ms register "pwr_on_vary_bl_to_blon" = "0x1c" + register "pwr_down_bloff_to_varybloff" = "0x2" device ref gpp_bridge_1 on # Required so the NVMe gets placed into D3 when entering S0i3. -- To view, visit https://review.coreboot.org/c/coreboot/+/74759 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifefd47a86e53d574098ae2e5bd2f41ae79353385 Gerrit-Change-Number: 74759 Gerrit-PatchSet: 1 Gerrit-Owner: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/amd/mendocino: Add FSP parameter for eDP power sequence adjustment
by Chris Wang (Code Review) 25 Apr '23

25 Apr '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held. Chris Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74758 ) Change subject: soc/amd/mendocino: Add FSP parameter for eDP power sequence adjustment ...................................................................... soc/amd/mendocino: Add FSP parameter for eDP power sequence adjustment Add UPD parameter for eDP power sequence adjust. The pwr_down_bloff_to_varybloff is set one unit per 4ms. BUG=b:271704149 TEST=Build; Verify the UPD was pass to system integrated table. Signed-off-by: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Change-Id: Ibdf50db12d982b45edca205e8f4612deb702453d --- M src/soc/amd/mendocino/chip.h M src/soc/amd/mendocino/fsp_m_params.c 2 files changed, 21 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/74758/1 diff --git a/src/soc/amd/mendocino/chip.h b/src/soc/amd/mendocino/chip.h index 774ce5e..366bdd07 100644 --- a/src/soc/amd/mendocino/chip.h +++ b/src/soc/amd/mendocino/chip.h @@ -180,6 +180,9 @@ /* Set for eDP power sequence adjustment timing from varybl to blon. The unit is set to one per 4ms*/ uint8_t pwr_on_vary_bl_to_blon; + /* Set for eDP power sequence adjustment timing from bloff to varybloff. The unit is set to + one per 4ms*/ + uint8_t pwr_down_bloff_to_varybloff; }; diff --git a/src/soc/amd/mendocino/fsp_m_params.c b/src/soc/amd/mendocino/fsp_m_params.c index 453ce69..e3253c9 100644 --- a/src/soc/amd/mendocino/fsp_m_params.c +++ b/src/soc/amd/mendocino/fsp_m_params.c @@ -171,6 +171,7 @@ mcfg->dxio_tx_vboost_enable = config->dxio_tx_vboost_enable; mcfg->pwr_on_vary_bl_to_blon = config->pwr_on_vary_bl_to_blon; + mcfg->pwr_down_bloff_to_varybloff = config-> pwr_down_bloff_to_varybloff; fsp_fill_pcie_ddi_descriptors(mcfg); fsp_assign_ioapic_upds(mcfg); -- To view, visit https://review.coreboot.org/c/coreboot/+/74758 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdf50db12d982b45edca205e8f4612deb702453d Gerrit-Change-Number: 74758 Gerrit-PatchSet: 1 Gerrit-Owner: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: vc/amd/fsp/mendocino/FspmUpd: Update Update UPD structure for MDN-FSP
by Chris Wang (Code Review) 25 Apr '23

25 Apr '23

Chris Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74757 ) Change subject: vc/amd/fsp/mendocino/FspmUpd: Update Update UPD structure for MDN-FSP ...................................................................... vc/amd/fsp/mendocino/FspmUpd: Update Update UPD structure for MDN-FSP Update UPD structure to align with MDN-FSP. BUG=b:271704149 BRANCH=none Test=Build/Boot to ChromeOS Signed-off-by: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Change-Id: Id410c40a65c0fd4b9b73cf36dc1f08eba0a3e44c --- M src/vendorcode/amd/fsp/mendocino/FspmUpd.h 1 file changed, 19 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/74757/1 diff --git a/src/vendorcode/amd/fsp/mendocino/FspmUpd.h b/src/vendorcode/amd/fsp/mendocino/FspmUpd.h index 391c64b..933a1d6 100644 --- a/src/vendorcode/amd/fsp/mendocino/FspmUpd.h +++ b/src/vendorcode/amd/fsp/mendocino/FspmUpd.h @@ -101,8 +101,9 @@ /** Offset 0x04E1**/ uint32_t vrm_maximum_current_limit_mA; /** Offset 0x04E5**/ uint32_t vrm_soc_current_limit_mA; /** Offset 0x04E9**/ uint8_t fch_usb_3_port_force_gen1; - /** Offset 0x04E9**/ uint8_t pwr_on_vary_bl_to_blon; - /** Offset 0x04EA**/ uint8_t UnusedUpdSpace2[277]; + /** Offset 0x04EA**/ uint8_t pwr_on_vary_bl_to_blon; + /** Offset 0x04EB**/ uint8_t pwr_down_bloff_to_varybloff; + /** Offset 0x04EC**/ uint8_t UnusedUpdSpace2[276]; /** Offset 0x0600**/ uint16_t UpdTerminator; } FSP_M_CONFIG; -- To view, visit https://review.coreboot.org/c/coreboot/+/74757 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id410c40a65c0fd4b9b73cf36dc1f08eba0a3e44c Gerrit-Change-Number: 74757 Gerrit-PatchSet: 1 Gerrit-Owner: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: acpi/acpi.c: Reduce scope of some functions
by Jan Samek (Code Review) 25 Apr '23

25 Apr '23

Attention is currently required from: Lance Zhao, Martin L Roth, Subrata Banik, Tim Wawrzynczak, Maximilian Brune, Arthur Heymans, Werner Zeh. Jan Samek has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74756 ) Change subject: acpi/acpi.c: Reduce scope of some functions ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/74756 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f8282f308506a68b14ce3101f11078cb13709f2 Gerrit-Change-Number: 74756 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Tue, 25 Apr 2023 14:24:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: acpi/acpi.c: Reduce scope of some functions
by Lean Sheng Tan (Code Review) 25 Apr '23

25 Apr '23

Attention is currently required from: Lance Zhao, Martin L Roth, Subrata Banik, Tim Wawrzynczak, Maximilian Brune, Arthur Heymans, Werner Zeh, Jan Samek. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74756 ) Change subject: acpi/acpi.c: Reduce scope of some functions ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: can you elaborate more on the commit message? it is too vague. -- To view, visit https://review.coreboot.org/c/coreboot/+/74756 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f8282f308506a68b14ce3101f11078cb13709f2 Gerrit-Change-Number: 74756 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Jan Samek <jan.samek(a)siemens.com> Gerrit-Comment-Date: Tue, 25 Apr 2023 14:18:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: util/cbmem: Add REG_NEWLINE flag to fix matching pattern
by Konrad Adamczyk (Code Review) 25 Apr '23

25 Apr '23

Konrad Adamczyk has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74742 ) Change subject: util/cbmem: Add REG_NEWLINE flag to fix matching pattern ...................................................................... util/cbmem: Add REG_NEWLINE flag to fix matching pattern Match-any-character operators (eg. ".*") shall not match newline characters for BANNER_REGEX, since given regular expression matches newline explicitly. Add REG_NEWLINE flag to `regcomp` call. BUG=b:278718871 TEST=Boot firmware on skyrim, reboot. Run `cbmem -2`. `cbmem -2` returns second-to-last boot log. Change-Id: I9e924349ead0fa7eea8b9ad5161138a4c4946ade Signed-off-by: Konrad Adamczyk <konrada(a)google.com> --- M util/cbmem/cbmem.c 1 file changed, 22 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/74742/1 diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index c0b39ea..060f88c 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -1001,7 +1001,7 @@ for (size_t i = 0; !cursor && i < ARRAY_SIZE(regex); i++) { regex_t re; regmatch_t match; - int res = regcomp(&re, regex[i], REG_EXTENDED); + int res = regcomp(&re, regex[i], REG_EXTENDED | REG_NEWLINE); assert(res == 0); /* Keep looking for matches so we find the last one. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/74742 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e924349ead0fa7eea8b9ad5161138a4c4946ade Gerrit-Change-Number: 74742 Gerrit-PatchSet: 1 Gerrit-Owner: Konrad Adamczyk <konrada(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: acpi/acpi.c: Reduce scope of some functions
by Arthur Heymans (Code Review) 25 Apr '23

25 Apr '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74756 ) Change subject: acpi/acpi.c: Reduce scope of some functions ...................................................................... acpi/acpi.c: Reduce scope of some functions These functions are only used in one compilation unit. Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: I6f8282f308506a68b14ce3101f11078cb13709f2 --- M src/acpi/acpi.c M src/include/acpi/acpi.h 2 files changed, 21 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/74756/1 diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index 492d043..14e8850 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -288,7 +288,7 @@ return current; } -void acpi_create_madt(acpi_madt_t *madt) +static void acpi_create_madt(acpi_madt_t *madt) { acpi_header_t *header = &(madt->header); unsigned long current = (unsigned long)madt + sizeof(acpi_madt_t); @@ -333,7 +333,7 @@ } /* MCFG is defined in the PCI Firmware Specification 3.0. */ -void acpi_create_mcfg(acpi_mcfg_t *mcfg) +static void acpi_create_mcfg(acpi_mcfg_t *mcfg) { acpi_header_t *header = &(mcfg->header); unsigned long current = (unsigned long)mcfg + sizeof(acpi_mcfg_t); @@ -517,7 +517,7 @@ acpigen_pop_len(); } -void acpi_create_ssdt_generator(acpi_header_t *ssdt, const char *oem_table_id) +static void acpi_create_ssdt_generator(acpi_header_t *ssdt, const char *oem_table_id) { unsigned long current = (unsigned long)ssdt + sizeof(acpi_header_t); @@ -989,7 +989,7 @@ } /* http://www.intel.com/hardwaredesign/hpetspec_1.pdf */ -void acpi_create_hpet(acpi_hpet_t *hpet) +static void acpi_create_hpet(acpi_hpet_t *hpet) { acpi_header_t *header = &(hpet->header); acpi_addr_t *addr = &(hpet->addr); @@ -1330,7 +1330,7 @@ return current; } -void acpi_create_dbg2(acpi_dbg2_header_t *dbg2, +static void acpi_create_dbg2(acpi_dbg2_header_t *dbg2, int port_type, int port_subtype, acpi_addr_t *address, uint32_t address_size, const char *device_path) @@ -1451,7 +1451,7 @@ return current; } -void acpi_create_facs(acpi_facs_t *facs) +static void acpi_create_facs(acpi_facs_t *facs) { memset((void *)facs, 0, sizeof(acpi_facs_t)); @@ -1628,7 +1628,7 @@ } /* ACPI 3.0b */ -void acpi_write_bert(acpi_bert_t *bert, uintptr_t region, size_t length) +static void acpi_write_bert(acpi_bert_t *bert, uintptr_t region, size_t length) { acpi_header_t *header = &(bert->header); @@ -1656,7 +1656,7 @@ __weak void soc_fill_fadt(acpi_fadt_t *fadt) { } __weak void mainboard_fill_fadt(acpi_fadt_t *fadt) { } -void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) +static void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) { acpi_header_t *header = &(fadt->header); @@ -1701,7 +1701,7 @@ acpi_checksum((void *)fadt, header->length); } -void acpi_create_lpit(acpi_lpit_t *lpit) +static void acpi_create_lpit(acpi_lpit_t *lpit) { acpi_header_t *header = &(lpit->header); unsigned long current = (unsigned long)lpit + sizeof(acpi_lpit_t); diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index 77f73ae..58db58c 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -1308,9 +1308,6 @@ unsigned long write_acpi_tables(unsigned long addr); unsigned long acpi_fill_madt(unsigned long current); unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t *ivrs, unsigned long current); -void acpi_create_ssdt_generator(acpi_header_t *ssdt, const char *oem_table_id); -void acpi_write_bert(acpi_bert_t *bert, uintptr_t region, size_t length); -void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt); void acpi_fill_fadt(acpi_fadt_t *fadt); void arch_fill_fadt(acpi_fadt_t *fadt); @@ -1342,8 +1339,6 @@ int acpi_create_madt_irqoverride(acpi_madt_irqoverride_t *irqoverride, u8 bus, u8 source, u32 gsirq, u16 flags); -void acpi_create_madt(acpi_madt_t *madt); - unsigned long acpi_create_madt_one_lapic(unsigned long current, u32 cpu, u32 apic); unsigned long acpi_create_madt_lapics_with_nmis(unsigned long current); @@ -1401,22 +1396,12 @@ unsigned long (*acpi_fill_crat)(struct acpi_crat_header *crat_struct, unsigned long current)); -void acpi_create_hpet(acpi_hpet_t *hpet); unsigned long acpi_write_hpet(const struct device *device, unsigned long start, acpi_rsdp_t *rsdp); /* cpu/intel/speedstep/acpi.c */ void generate_cpu_entries(const struct device *device); -void acpi_create_mcfg(acpi_mcfg_t *mcfg); - -void acpi_create_facs(acpi_facs_t *facs); - -void acpi_create_dbg2(acpi_dbg2_header_t *dbg2_header, - int port_type, int port_subtype, - acpi_addr_t *address, uint32_t address_size, - const char *device_path); - unsigned long acpi_write_dbg2_pci_uart(acpi_rsdp_t *rsdp, unsigned long current, const struct device *dev, uint8_t access_size); void acpi_create_dmar(acpi_dmar_t *dmar, enum dmar_flags flags, @@ -1455,7 +1440,6 @@ unsigned long acpi_create_hest_error_source(acpi_hest_t *hest, acpi_hest_esd_t *esd, u16 type, void *data, u16 len); -void acpi_create_lpit(acpi_lpit_t *lpit); unsigned long acpi_create_lpi_desc_ncst(acpi_lpi_desc_ncst_t *lpi_desc, uint16_t uid); /* chipsets that select ACPI_BERT must implement this function */ -- To view, visit https://review.coreboot.org/c/coreboot/+/74756 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f8282f308506a68b14ce3101f11078cb13709f2 Gerrit-Change-Number: 74756 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/facebook/fbg1701/board_mboot.h: Remove config from mb_log_list
by Frans Hendriks (Code Review) 25 Apr '23

25 Apr '23

Attention is currently required from: Erik van den Bogaert, Paul Menzel. Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74750 ) Change subject: mb/facebook/fbg1701/board_mboot.h: Remove config from mb_log_list ...................................................................... Patch Set 4: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/74750/comment/4feebf8e_9edef2af PS3, Line 7: list > log list? Done https://review.coreboot.org/c/coreboot/+/74750/comment/a2a2587c_90804aa1 PS3, Line 7: src/ > Please remove. Done https://review.coreboot.org/c/coreboot/+/74750/comment/c09f5dd7_4cde91fe PS3, Line 12: and add it to verified items > Where is it added? Add nr of patchset where it is added -- To view, visit https://review.coreboot.org/c/coreboot/+/74750 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iacf023bc8b9c2ebc66137c4ea683589751a30d2f Gerrit-Change-Number: 74750 Gerrit-PatchSet: 4 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 25 Apr 2023 14:05:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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