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Hello Eric Lai, Nick Vaccaro, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: mb/google/nissa/var/quandiso: Update P-sensor tuning
......................................................................
mb/google/nissa/var/quandiso: Update P-sensor tuning
Update proximity sensor tuning value from SX9324ICSTRT schematic.
BUG=b:314550601
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot and verify p-sensor
watch 'cat /sys/bus/iio/devices/iio:device*/*raw'
Change-Id: I5fc3bc5876594f2df79d628bd986113d37087c3d
Signed-off-by: Robert Chen <robert.chen(a)quanta.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/quandiso/overridetree.cb
1 file changed, 9 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/79724/2
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Change subject: soc/intel/xeon_sp: Redesign resource allocation
......................................................................
Patch Set 13:
(3 comments)
File src/device/pci_device.c:
https://review.coreboot.org/c/coreboot/+/78327/comment/67a38818_862c1596 :
PS13, Line 611: res->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE | IORESOURCE_PREFETCH;
> If we take 1), actually we could use the get_host_bridge_resource API to create domains (proven in G […]
Done
File src/soc/intel/xeon_sp/chip_common.c:
https://review.coreboot.org/c/coreboot/+/78327/comment/4efbe35d_a8270cd5 :
PS12, Line 89: iio_ioat_domain_scan_bus
> > Here, our intention is just to use opensource code to show an example, for any downstream SPR cust […]
Done
File src/soc/intel/xeon_sp/chip_common.c:
https://review.coreboot.org/c/coreboot/+/78327/comment/8ba3d109_f538cb64 :
PS13, Line 108: host_bridge_resource_t hr;
> here we do the host bridge into query and bus scan.
Done
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Change subject: soc/intel/xeon_sp: Redesign resource allocation
......................................................................
Patch Set 13:
(1 comment)
Patchset:
PS13:
> If everybody agrees I could take this over and push a version that […]
Okay for me, please move ahead and we could help to test and revise.
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Change subject: soc/intel/xeon_sp: SoC independent domain and host bridge resource interface
......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/xeon_sp/include/soc/chip_common.h:
https://review.coreboot.org/c/coreboot/+/79656/comment/9c9e7c0d_c819f0f3 :
PS2, Line 42: domain_resource_t *domain_res);
> Done
Sure, let us go ahead with soc_create_ioat_domains()
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Change subject: soc/intel/xeon_sp: SoC independent domain and host bridge resource interface
......................................................................
Patch Set 2:
(2 comments)
Patchset:
PS2:
> Hi Nico, I'm happy to have the deep comments from you. […]
Done
File src/soc/intel/xeon_sp/include/soc/chip_common.h:
https://review.coreboot.org/c/coreboot/+/79656/comment/35ed265a_ea5171cf :
PS2, Line 42: domain_resource_t *domain_res);
> > This is a good question. Here, the concept of domain is a actually a wrapper for STACK_RES. […]
Done
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Change subject: soc/intel/xeon_sp: SoC independent domain and host bridge resource interface
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Patch Set 2:
(1 comment)
Patchset:
PS2:
> Thanks, Shuo, for your answers so far. I think I understand better now […]
Hi Nico, I'm happy to have the deep comments from you. The discussion is quite meaningful and worthwhile.
First of all, I agree with you that xeon_sp should reuse coreboot generic utils whenever possible. If there are opportunity and needs to do such improvements, we are willing to help.
While in the meantime, I think it should be flexible on how a new SoC leverages the generic utils, a.k.a. the SoC codes could choose the simplest path to integrate as long as the design is decent, no matter by reusing generic utils or by creating its own utils. coreboot by nature allows for such design pattern and hence it proves to be a open, simple but powerful architecture. This is especially important when incubating new SoC supports at downstream.
Hence, when we doing generic util accommodation for xeon_sp at upstream, we hope that the flexibility above could be kept as well. This is all what I would like to raise around this discussion, all other aspects are pretty good. I highly look forward to good collaboration now and in future :)
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Change subject: mb/google/rex/var/screebo: Update DTT settings for thermal control
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Patch Set 2: Code-Review+2
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Change subject: Update vboot submodule to upstream main
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Patch Set 1: Code-Review+2
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