coreboot-gerrit December 2023

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[XS] Change in coreboot[main]: mb/hp/snb_ivb_laptops: Add VBT for Elitebook 8460p
by Riku Viitanen (Code Review) 23 Dec '23

23 Dec '23

Attention is currently required from: Riku Viitanen. Hello Arthur Heymans, Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79625?usp=email to look at the new patch set (#2). Change subject: mb/hp/snb_ivb_laptops: Add VBT for Elitebook 8460p ...................................................................... mb/hp/snb_ivb_laptops: Add VBT for Elitebook 8460p Extracted from a system running OEM BIOS version F.42. intelvbttool --inlegacy --outvbt data.vbt Change-Id: I6e499eb7ff8edb6556f8211d2fb8246cba5f5276 Signed-off-by: Riku Viitanen <riku.viitanen(a)protonmail.com> --- M src/mainboard/hp/snb_ivb_laptops/Kconfig A src/mainboard/hp/snb_ivb_laptops/variants/8460p/data.vbt 2 files changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/79625/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79625?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6e499eb7ff8edb6556f8211d2fb8246cba5f5276 Gerrit-Change-Number: 79625 Gerrit-PatchSet: 2 Gerrit-Owner: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: mb/hp/snb_ivb_laptops: Add VBT for Elitebook 8460p
by Paul Menzel (Code Review) 23 Dec '23

23 Dec '23

Attention is currently required from: Riku Viitanen. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79625?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: mb/hp/snb_ivb_laptops: Add VBT for Elitebook 8460p ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/79625/comment/814bcbbb_7143b0cf : PS1, Line 9: OEM BIOS Please add the version. -- To view, visit https://review.coreboot.org/c/coreboot/+/79625?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6e499eb7ff8edb6556f8211d2fb8246cba5f5276 Gerrit-Change-Number: 79625 Gerrit-PatchSet: 1 Gerrit-Owner: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Comment-Date: Sat, 23 Dec 2023 08:59:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: .gitreview: Update default branch from master to main
by Felix Singer (Code Review) 23 Dec '23

23 Dec '23

Attention is currently required from: Arthur Heymans, Martin Roth, Paul Menzel. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79743?usp=email ) Change subject: .gitreview: Update default branch from master to main ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/79743/comment/8a0ff3e1_a4918b02 : PS1, Line 7: Update .gitreview > Maybe: […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/79743?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I58001819079bc880e8cde1c3a6756ff6c8a1c016 Gerrit-Change-Number: 79743 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Sat, 23 Dec 2023 03:17:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: sb/intel/bd82x6x: Honor POST code Kconfig option
by Felix Singer (Code Review) 23 Dec '23

23 Dec '23

Attention is currently required from: Keith Hui. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79725?usp=email ) Change subject: sb/intel/bd82x6x: Honor POST code Kconfig option ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79725?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I455d7aff27154d6821e262a21248e8c7306e2d61 Gerrit-Change-Number: 79725 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Comment-Date: Sat, 23 Dec 2023 03:17:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[main]: [WIP] mb/hp/snb_ivb_laptops: Add EliteBook 8570p
by Riku Viitanen (Code Review) 22 Dec '23

22 Dec '23

Riku Viitanen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79744?usp=email ) Change subject: [WIP] mb/hp/snb_ivb_laptops: Add EliteBook 8570p ...................................................................... [WIP] mb/hp/snb_ivb_laptops: Add EliteBook 8570p Change-Id: Ida585702263ea2a19b3047999022c60bdca82d8f Signed-off-by: Riku Viitanen <riku.viitanen(a)protonmail.com> --- M src/mainboard/hp/snb_ivb_laptops/Kconfig M src/mainboard/hp/snb_ivb_laptops/Kconfig.name A src/mainboard/hp/snb_ivb_laptops/variants/8570p/board_info.txt A src/mainboard/hp/snb_ivb_laptops/variants/8570p/early_init.c A src/mainboard/hp/snb_ivb_laptops/variants/8570p/gma-mainboard.ads A src/mainboard/hp/snb_ivb_laptops/variants/8570p/gpio.c A src/mainboard/hp/snb_ivb_laptops/variants/8570p/hda_verb.c A src/mainboard/hp/snb_ivb_laptops/variants/8570p/overridetree.cb 8 files changed, 399 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/79744/1 diff --git a/src/mainboard/hp/snb_ivb_laptops/Kconfig b/src/mainboard/hp/snb_ivb_laptops/Kconfig index f0bd55f..c39173a 100644 --- a/src/mainboard/hp/snb_ivb_laptops/Kconfig +++ b/src/mainboard/hp/snb_ivb_laptops/Kconfig @@ -69,6 +69,15 @@ select SOUTHBRIDGE_INTEL_C216 select SUPERIO_SMSC_LPC47N217 +config BOARD_HP_8570P + select BOARD_HP_SNB_IVB_LAPTOPS_COMMON + select BOARD_ROMSIZE_KB_16384 + select GFX_GMA_PANEL_1_ON_LVDS + select INTEL_INT15 + select MAINBOARD_HAS_LIBGFXINIT + select SOUTHBRIDGE_INTEL_C216 + select SUPERIO_SMSC_LPC47N217 + config BOARD_HP_8770W select BOARD_HP_SNB_IVB_LAPTOPS_COMMON select BOARD_ROMSIZE_KB_16384 @@ -118,6 +127,7 @@ default "2760p" if BOARD_HP_2760P default "8460p" if BOARD_HP_8460P default "8470p" if BOARD_HP_8470P + default "8570p" if BOARD_HP_8570P default "8770w" if BOARD_HP_8770W default "folio_9470m" if BOARD_HP_FOLIO_9470M default "probook_6360b" if BOARD_HP_PROBOOK_6360B @@ -130,6 +140,7 @@ default "EliteBook 2760p" if BOARD_HP_2760P default "EliteBook 8460p" if BOARD_HP_8460P default "EliteBook 8470p" if BOARD_HP_8470P + default "EliteBook 8570p" if BOARD_HP_8570P default "EliteBook 8770w" if BOARD_HP_8770W default "EliteBook Folio 9470m" if BOARD_HP_FOLIO_9470M default "ProBook 6360b" if BOARD_HP_PROBOOK_6360B @@ -149,6 +160,6 @@ default 1 if BOARD_HP_2560P || BOARD_HP_2760P || BOARD_HP_8460P default 2 if BOARD_HP_2570P || BOARD_HP_8470P || BOARD_HP_8770W default 1 if BOARD_HP_PROBOOK_6360B # FIXME: check this - default 2 if BOARD_HP_REVOLVE_810_G1 # FIXME: check this + default 2 if BOARD_HP_8570P || BOARD_HP_REVOLVE_810_G1 # FIXME: check this endif diff --git a/src/mainboard/hp/snb_ivb_laptops/Kconfig.name b/src/mainboard/hp/snb_ivb_laptops/Kconfig.name index f72e0f6..2eaa85c 100644 --- a/src/mainboard/hp/snb_ivb_laptops/Kconfig.name +++ b/src/mainboard/hp/snb_ivb_laptops/Kconfig.name @@ -18,6 +18,9 @@ config BOARD_HP_8470P bool "EliteBook 8470p" +config BOARD_HP_8570P + bool "EliteBook 8570p" + config BOARD_HP_8770W bool "EliteBook 8770w" diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8570p/board_info.txt b/src/mainboard/hp/snb_ivb_laptops/variants/8570p/board_info.txt new file mode 100644 index 0000000..1d0ca8b --- /dev/null +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8570p/board_info.txt @@ -0,0 +1,7 @@ +Category: laptop +Board URL: https://support.hp.com/us-en/product/HP-EliteBook-8470p-Notebook-PC/5212907 +ROM protocol: SPI +ROM package: SOIC-16 +ROM socketed: n +Flashrom support: n +Release year: 2012 diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8570p/early_init.c b/src/mainboard/hp/snb_ivb_laptops/variants/8570p/early_init.c new file mode 100644 index 0000000..b2a7fb5 --- /dev/null +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8570p/early_init.c @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <superio/smsc/lpc47n217/lpc47n217.h> +#include <ec/hp/kbc1126/ec.h> + +#define SERIAL_DEV PNP_DEV(0x4e, LPC47N217_SP1) + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 1, 0 }, + { 1, 1, 0 }, + { 1, 1, 1 }, + { 1, 1, 1 }, + { 1, 0, 2 }, + { 1, 0, 2 }, + { 0, 0, 3 }, + { 1, 1, 3 }, + { 1, 1, 4 }, + { 1, 1, 4 }, + { 1, 1, 5 }, + { 1, 1, 5 }, + { 0, 1, 6 }, + { 1, 1, 6 }, +}; + +void bootblock_mainboard_early_init(void) +{ + lpc47n217_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + kbc1126_enter_conf(); + kbc1126_mailbox_init(); + kbc1126_kbc_init(); + kbc1126_ec_init(); + kbc1126_pm1_init(); + kbc1126_exit_conf(); +} diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8570p/gma-mainboard.ads b/src/mainboard/hp/snb_ivb_laptops/variants/8570p/gma-mainboard.ads new file mode 100644 index 0000000..3df1e37 --- /dev/null +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8570p/gma-mainboard.ads @@ -0,0 +1,22 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + Analog, + LVDS, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8570p/gpio.c b/src/mainboard/hp/snb_ivb_laptops/variants/8570p/gpio.c new file mode 100644 index 0000000..7536cbf --- /dev/null +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8570p/gpio.c @@ -0,0 +1,226 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_OUTPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_OUTPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_OUTPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_LOW, + .gpio2 = GPIO_LEVEL_LOW, + .gpio11 = GPIO_LEVEL_LOW, + .gpio17 = GPIO_LEVEL_HIGH, + .gpio22 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_HIGH, + .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, + .gpio30 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio3 = GPIO_INVERT, + .gpio6 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, + .gpio10 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_GPIO, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_OUTPUT, + .gpio37 = GPIO_DIR_OUTPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_INPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_OUTPUT, + .gpio60 = GPIO_DIR_OUTPUT, + .gpio61 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio33 = GPIO_LEVEL_LOW, + .gpio35 = GPIO_LEVEL_LOW, + .gpio36 = GPIO_LEVEL_LOW, + .gpio37 = GPIO_LEVEL_LOW, + .gpio49 = GPIO_LEVEL_LOW, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio57 = GPIO_LEVEL_HIGH, + .gpio60 = GPIO_LEVEL_HIGH, + .gpio61 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_GPIO, + .gpio74 = GPIO_MODE_GPIO, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_OUTPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_OUTPUT, + .gpio71 = GPIO_DIR_OUTPUT, + .gpio72 = GPIO_DIR_OUTPUT, + .gpio73 = GPIO_DIR_OUTPUT, + .gpio74 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio68 = GPIO_LEVEL_HIGH, + .gpio70 = GPIO_LEVEL_HIGH, + .gpio71 = GPIO_LEVEL_HIGH, + .gpio72 = GPIO_LEVEL_LOW, + .gpio73 = GPIO_LEVEL_HIGH, + .gpio74 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8570p/hda_verb.c b/src/mainboard/hp/snb_ivb_laptops/variants/8570p/hda_verb.c new file mode 100644 index 0000000..16a1288 --- /dev/null +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8570p/hda_verb.c @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x111d7605, /* Codec Vendor / Device ID: IDT */ + 0x103c17bc, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x103c17bc), + AZALIA_PIN_CFG(0, 0x0a, 0x21011030), + AZALIA_PIN_CFG(0, 0x0b, 0x0421101f), + AZALIA_PIN_CFG(0, 0x0c, 0x04a11020), + AZALIA_PIN_CFG(0, 0x0d, 0x90170110), + AZALIA_PIN_CFG(0, 0x0e, 0x40f000f0), + AZALIA_PIN_CFG(0, 0x0f, 0x2181102e), + AZALIA_PIN_CFG(0, 0x10, 0x40f000f0), + AZALIA_PIN_CFG(0, 0x11, 0xd5a30140), + AZALIA_PIN_CFG(0, 0x1f, 0x40f000f0), + AZALIA_PIN_CFG(0, 0x20, 0x40f000f0), + + 0x80862806, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(3, 0x80860101), + AZALIA_PIN_CFG(3, 0x05, 0x18560010), + AZALIA_PIN_CFG(3, 0x06, 0x18560020), + AZALIA_PIN_CFG(3, 0x07, 0x18560030), + +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8570p/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/8570p/overridetree.cb new file mode 100644 index 0000000..c66c364 --- /dev/null +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8570p/overridetree.cb @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +chip northbridge/intel/sandybridge + register "gpu_cpu_backlight" = "0x00000d9c" + register "gpu_panel_port_select" = "0" + register "gpu_pch_backlight" = "0x0d9c0d9c" + + device domain 0 on + subsystemid 0x103c 0x17a7 inherit + + device ref igd on end + device ref peg10 on end + + chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH + register "docking_supported" = "0" + register "gen1_dec" = "0x007c0201" + register "gen2_dec" = "0x000c0101" + register "gen3_dec" = "0x00fcfe01" + register "gen4_dec" = "0x000402e9" + register "gpi6_routing" = "2" + register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" + register "sata_port_map" = "0x3b" + register "superspeed_capable_ports" = "0x0000000f" + register "xhci_overcurrent_mapping" = "0x00000c03" + register "xhci_switchable_ports" = "0x0000000f" + + device ref xhci on end # USB 3.0 Controller + device ref me_kt on end + device ref pcie_rp1 on end # PCIe Port #1 + device ref pcie_rp2 on end # PCIe Port #2 + device ref pcie_rp3 on end # PCIe Port #3 + device ref pcie_rp4 on end # PCIe Port #4 + device ref pcie_rp5 off end # PCIe Port #5 + device ref pcie_rp6 off end # PCIe Port #6 + device ref pcie_rp7 off end # PCIe Port #7 + device ref pcie_rp8 off end # PCIe Port #8 + + device ref lpc on + chip ec/hp/kbc1126 + register "ec_data_port" = "0x62" + register "ec_cmd_port" = "0x66" + register "ec_ctrl_reg" = "0x81" + register "ec_fan_ctrl_value" = "0x6b" + device pnp ff.1 off end + end + chip superio/smsc/lpc47n217 + device pnp 4e.3 on # Parallel + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 4e.4 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.5 off end # COM2 + end + end + end + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/79744?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ida585702263ea2a19b3047999022c60bdca82d8f Gerrit-Change-Number: 79744 Gerrit-PatchSet: 1 Gerrit-Owner: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-MessageType: newchange

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[L] Change in coreboot[main]: soc/intel/xeon_sp: Redesign resource allocation
by Nico Huber (Code Review) 22 Dec '23

22 Dec '23

Attention is currently required from: Annie Chen, Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Felix Held, Jincheng Li, Lean Sheng Tan, Nill Ge, Patrick Rudolph, Paul Menzel, Shuo Liu, TangYiwei, Tim Chu. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78327?usp=email ) Change subject: soc/intel/xeon_sp: Redesign resource allocation ...................................................................... Patch Set 14: (3 comments) Patchset: PS13: > Okay for me, please move ahead and we could help to test and revise. Well, it should compile :D This also needs the above-4G allocation for a final test. When testing, please keep an eye on Linux' own resource allocations. If we did it right now, Linux shouldn't have to re-allocate anything. File src/soc/intel/xeon_sp/spr/ioat.c: https://review.coreboot.org/c/coreboot/+/78327/comment/5a2f7e6a_7e26aa44 : PS14, Line 73: const unsigned int domain_base = MAX_SOCKET * MAX_LOGIC_IIO_STACK; I decided to simply add the bus number on top of this. We could also always use the bus base (for all IIO stacks), as Shuo suggested. It should be unique as long as we have a single PCI segment group (and when that changes, we can simply add an offset). WDYT? https://review.coreboot.org/c/coreboot/+/78327/comment/422e427c_f6e18558 : PS14, Line 112: mem64_base, mem64_limit); Doing all this at once instead of using .scan_bus and .read_resources turned out to be much easier given the static information. I wonder if we shouldn't always do this when we have pre-defined resources. It also avoids having to look the STACK_RES up again. -- To view, visit https://review.coreboot.org/c/coreboot/+/78327?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idb29c24b71a18e2e092f9d4953d106e6ca0a5fe1 Gerrit-Change-Number: 78327 Gerrit-PatchSet: 14 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Annie Chen <chen.annieet(a)inventec.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nill Ge <geshijian(a)bytedance.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Jincheng Li <jincheng.li(a)intel.com> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Annie Chen <chen.annieet(a)inventec.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nill Ge <geshijian(a)bytedance.com> Gerrit-Attention: TangYiwei Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 22 Dec 2023 20:59:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com> Gerrit-MessageType: comment

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[L] Change in coreboot[main]: soc/intel/xeon_sp: Redesign resource allocation
by Nico Huber (Code Review) 22 Dec '23

22 Dec '23

Attention is currently required from: Annie Chen, Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Felix Held, Jincheng Li, Lean Sheng Tan, Nico Huber, Nill Ge, Patrick Rudolph, Paul Menzel, TangYiwei, Tim Chu. Nico Huber has uploaded a new patch set (#14) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/78327?usp=email ) Change subject: soc/intel/xeon_sp: Redesign resource allocation ...................................................................... soc/intel/xeon_sp: Redesign resource allocation The xeon_sp code worked around the coreboot allocator rather than using it. Now the allocator is able to deal with the multiple IIOs so this is not necessary anymore. Instead do the following: - Parse the FSP HOB information about IIO into coreboot PCI domains - Use existing scan_bus and read_resource - Handle DINO stacks with multiple domains in soc-specific code Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Signed-off-by: Nico Huber <nico.h(a)gmx.de> Change-Id: Idb29c24b71a18e2e092f9d4953d106e6ca0a5fe1 --- M src/soc/intel/xeon_sp/Kconfig M src/soc/intel/xeon_sp/acpi.c M src/soc/intel/xeon_sp/chip_common.c M src/soc/intel/xeon_sp/cpx/chip.c M src/soc/intel/xeon_sp/cpx/soc_util.c M src/soc/intel/xeon_sp/include/soc/chip_common.h M src/soc/intel/xeon_sp/include/soc/util.h M src/soc/intel/xeon_sp/memmap.c M src/soc/intel/xeon_sp/skx/chip.c M src/soc/intel/xeon_sp/skx/soc_util.c M src/soc/intel/xeon_sp/spr/Kconfig M src/soc/intel/xeon_sp/spr/Makefile.inc M src/soc/intel/xeon_sp/spr/chip.c A src/soc/intel/xeon_sp/spr/ioat.c M src/soc/intel/xeon_sp/spr/soc_util.c M src/soc/intel/xeon_sp/util.c 16 files changed, 242 insertions(+), 531 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/78327/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/78327?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idb29c24b71a18e2e092f9d4953d106e6ca0a5fe1 Gerrit-Change-Number: 78327 Gerrit-PatchSet: 14 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Annie Chen <chen.annieet(a)inventec.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nill Ge <geshijian(a)bytedance.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Jincheng Li <jincheng.li(a)intel.com> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Annie Chen <chen.annieet(a)inventec.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nill Ge <geshijian(a)bytedance.com> Gerrit-Attention: TangYiwei Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: .gitreview: Update default branch from master to main
by Felix Singer (Code Review) 22 Dec '23

22 Dec '23

Attention is currently required from: Arthur Heymans, Martin Roth. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79743?usp=email ) Change subject: .gitreview: Update default branch from master to main ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79743?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I58001819079bc880e8cde1c3a6756ff6c8a1c016 Gerrit-Change-Number: 79743 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Fri, 22 Dec 2023 18:32:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: Update vboot submodule to upstream main
by Jérémy Compostella (Code Review) 22 Dec '23

22 Dec '23

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Julius Werner, Matt DeVillier. Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79685?usp=email ) Change subject: Update vboot submodule to upstream main ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/79685?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia6e535f4e49045e24ab005ccd7dcbbcf250f96ac Gerrit-Change-Number: 79685 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 22 Dec 2023 16:51:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: Documentation: Add Protectli to ships-with-coreboot hw list
by Filip Lewiński (Code Review) 22 Dec '23

22 Dec '23

Attention is currently required from: Filip Lewiński, Krystian Hebel, Maciej Pijanowski, Michał Kopeć, Michał Żygowski, Paul Menzel. Hello Krystian Hebel, Michał Kopeć, Michał Żygowski, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79215?usp=email to look at the new patch set (#6). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: Documentation: Add Protectli to ships-with-coreboot hw list ...................................................................... Documentation: Add Protectli to ships-with-coreboot hw list Change-Id: Iff642f5122e7132d96177f2ed1680ece42aac095 Signed-off-by: Filip Lewiński <filip.lewinski(a)3mdeb.com> --- M Documentation/distributions.md 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/79215/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/79215?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iff642f5122e7132d96177f2ed1680ece42aac095 Gerrit-Change-Number: 79215 Gerrit-PatchSet: 6 Gerrit-Owner: Filip Lewiński Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <miczyg94(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Filip Lewiński Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Michał Żygowski <miczyg94(a)gmail.com> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-MessageType: newpatchset

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