coreboot-gerrit December 2023

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[main]: mainboard/amd/birman: Add Birmanplus board variant support for Phoeni...
by Anand Vaikar (Code Review) 01 Dec '23

01 Dec '23

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Paul Menzel. Anand Vaikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79283?usp=email ) Change subject: mainboard/amd/birman: Add Birmanplus board variant support for Phoenix SOC ...................................................................... Patch Set 6: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/79283/comment/86c9a4ab_227dbf3f : PS5, Line 7: src/mainboard/amd/birman : Add > Please remove the space before the colon. Done https://review.coreboot.org/c/coreboot/+/79283/comment/42dd30ba_dc208f79 : PS5, Line 7: src/mainboard/amd/birman : Add a new board variant for Phoenix SOC > Please mention the new variant. Done https://review.coreboot.org/c/coreboot/+/79283/comment/881c5c78_e50eeec3 : PS5, Line 7: src/ > Please remove `src`. Done https://review.coreboot.org/c/coreboot/+/79283/comment/fdca0bc1_cf0ffeb3 : PS5, Line 12: TEST : > TEST= Done -- To view, visit https://review.coreboot.org/c/coreboot/+/79283?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I40f196d8a662d19e424511febca24edb88d686dd Gerrit-Change-Number: 79283 Gerrit-PatchSet: 6 Gerrit-Owner: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 01 Dec 2023 01:56:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: mainboard/amd/birman: Add Birmanplus board variant support for Phoeni...
by Anand Vaikar (Code Review) 01 Dec '23

01 Dec '23

Attention is currently required from: Anand Vaikar, Felix Held, Fred Reitberger, Jason Glenesk. Hello Felix Held, Fred Reitberger, Jason Glenesk, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79283?usp=email to look at the new patch set (#6). Change subject: mainboard/amd/birman: Add Birmanplus board variant support for Phoenix SOC ...................................................................... mainboard/amd/birman: Add Birmanplus board variant support for Phoenix SOC 1) Include the Port descriptor changes for Birmanplus platform 2) Add the Birmanplus specific config options TEST=Build and boot Phoenix Birmanplus platform. Change-Id: I40f196d8a662d19e424511febca24edb88d686dd Signed-off-by: Anand Vaikar <a.vaikar2021(a)gmail.com> --- M src/mainboard/amd/birman/Kconfig M src/mainboard/amd/birman/Kconfig.name M src/mainboard/amd/birman/Makefile.inc A src/mainboard/amd/birman/variants/birmanplus/port_descriptors.c 4 files changed, 239 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/79283/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/79283?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I40f196d8a662d19e424511febca24edb88d686dd Gerrit-Change-Number: 79283 Gerrit-PatchSet: 6 Gerrit-Owner: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: soc/mediatek/mt8188: devapc: Allow APU to access BND_NORTH_APB2_S
by jason-ch chen (Code Review) 01 Dec '23

01 Dec '23

Attention is currently required from: Hung-Te Lin, Paul Menzel. jason-ch chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79348?usp=email ) Change subject: soc/mediatek/mt8188: devapc: Allow APU to access BND_NORTH_APB2_S ...................................................................... Patch Set 2: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/79348/comment/28e98094_81e74aff : PS1, Line 9: Update BND_NORTH_APB2_S's domain 5 permission to allow the access from : APU. > Why? Otherwise no graphics is shown? Please elaborate on the problem. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/79348?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I967b138dc5517e54da7fbf94b9e502e478c991b5 Gerrit-Change-Number: 79348 Gerrit-PatchSet: 2 Gerrit-Owner: jason-ch chen <Jason-ch.Chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: jason-ch chen <Jason-ch.Chen(a)mediatek.com> Gerrit-CC: Nina-CM Wu <nina-cm.wu(a)mediatek.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 01 Dec 2023 01:46:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/mediatek/mt8188: devapc: Allow APU to access BND_NORTH_APB2_S
by jason-ch chen (Code Review) 01 Dec '23

01 Dec '23

Attention is currently required from: Hung-Te Lin, jason-ch chen. Hello Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79348?usp=email to look at the new patch set (#2). Change subject: soc/mediatek/mt8188: devapc: Allow APU to access BND_NORTH_APB2_S ...................................................................... soc/mediatek/mt8188: devapc: Allow APU to access BND_NORTH_APB2_S Update BND_NORTH_APB2_S's domain 5 permission to allow the access from APU. The APU requires certain information saved in BND_NORTH_APB2_S for voltage tuning. If this information cannot be retrieved, the APU may operate at a high frequency with low voltage. Consequently, the APU may not function as expected. Change-Id: I967b138dc5517e54da7fbf94b9e502e478c991b5 Signed-off-by: Nina Wu <nina-cm.wu(a)mediatek.com> Signed-off-by: Jason Chen <Jason-ch.Chen(a)mediatek.com> --- M src/soc/mediatek/mt8188/devapc.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/79348/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79348?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I967b138dc5517e54da7fbf94b9e502e478c991b5 Gerrit-Change-Number: 79348 Gerrit-PatchSet: 2 Gerrit-Owner: jason-ch chen <Jason-ch.Chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: jason-ch chen <Jason-ch.Chen(a)mediatek.com> Gerrit-CC: Nina-CM Wu <nina-cm.wu(a)mediatek.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: jason-ch chen <Jason-ch.Chen(a)mediatek.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: mb/google/rex/variants/deku: Complete USB configuration
by Eran Mitrani (Code Review) 01 Dec '23

01 Dec '23

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Subrata Banik, Tarun. Eran Mitrani has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79356?usp=email ) Change subject: mb/google/rex/variants/deku: Complete USB configuration ...................................................................... mb/google/rex/variants/deku: Complete USB configuration +-------------+----------------+------------+ | USB 2.0 | Connector Type | OC Mapping | +-------------+----------------+------------+ | 1 | Type-C | OC_0 | +-------------+----------------+------------+ | 2 | Type-C | OC_0 | +-------------+----------------+------------+ | 3 | Type-C | OC-0 | +-------------+----------------+------------+ | 4 | Type-A | OC_3 | +-------------+----------------+------------+ | 5 | Type-C | OC_0 | +-------------+----------------+------------+ | 6 | Type-A | OC_3 | +-------------+----------------+------------+ | 7 | Type-A | OC_3 | +-------------+----------------+------------+ | 8 | Type-A | OC_3 | +-------------+----------------+------------+ | 9 | Type-A | OC_3 | +-------------+----------------+------------+ | 10 | BT | NA | +-------------+----------------+------------+ +---------------------+-------------------+------------+ | USB 3.2 Gen 2x1 | Connector Details | OC Mapping | +---------------------+-------------------+------------+ | 1 | Type-A | OC_3 | +---------------------+-------------------+------------+ | 2 | Type-A | OC_3 | +---------------------+-------------------+------------+ +------+-------------------+------------+ | TCPx | Connector Details | OC Mapping | +------+-------------------+------------+ | 1 | Type C port 0 | OC_0 | +------+-------------------+------------+ | 2 | Type C port 1 | OC_0 | +------+-------------------+------------+ | 3 | Type C port 2 | OC_0 | +------+-------------------+------------+ | 4 | Type C port 3 | OC_0 | +------+-------------------+------------+ BUG=b:305793886 TEST=util/abuild/abuild -p none -t google/rex -x -a -b deku Signed-off-by: Eran Mitrani <mitrani(a)google.com> Change-Id: I90d3d984af6d40efb4553cf5675617700161d2d7 --- M src/mainboard/google/rex/variants/deku/overridetree.cb 1 file changed, 191 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/79356/1 diff --git a/src/mainboard/google/rex/variants/deku/overridetree.cb b/src/mainboard/google/rex/variants/deku/overridetree.cb index 1163292..86a015cf 100644 --- a/src/mainboard/google/rex/variants/deku/overridetree.cb +++ b/src/mainboard/google/rex/variants/deku/overridetree.cb @@ -98,6 +98,158 @@ .flags = PCIE_RP_LTR | PCIE_RP_AER, }" end # PCIE11 SSD card + device ref tbt_pcie_rp0 on end + device ref tbt_pcie_rp1 on end + device ref tbt_pcie_rp2 on end + device ref tbt_pcie_rp3 on end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(FRONT, CENTER, ACPI_PLD_GROUP(1, 1))" + device ref tcss_usb3_port0 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(2, 1))" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C2"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, CENTER, ACPI_PLD_GROUP(3, 1))" + device ref tcss_usb3_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C3"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(FRONT, LEFT, ACPI_PLD_GROUP(4, 1))" + device ref tcss_usb3_port2 on end + end + end + end + end + device ref tcss_dma0 on + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B22)" + use tcss_usb3_port0 as dfp[0].typec_port + device generic 0 on end + end + chip drivers/intel/usb4/retimer + register "dfp[1].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B22)" + use tcss_usb3_port1 as dfp[1].typec_port + device generic 0 on end + end + end + device ref tcss_dma1 on + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B22)" + use tcss_usb3_port2 as dfp[0].typec_port + device generic 0 on end + end + chip drivers/intel/usb4/retimer + register "dfp[1].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B22)" + use tcss_usb3_port3 as dfp[0].typec_port + device generic 0 on end + end + end + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + # FIXME - location need to be corrected once we have the final design + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(FRONT, CENTER, ACPI_PLD_GROUP(1, 1))" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(2, 1))" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C2"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, LEFT, ACPI_PLD_GROUP(3, 1))" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C3"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, LEFT, ACPI_PLD_GROUP(4, 1))" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(5, 1))" + device ref usb2_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, CENTER, ACPI_PLD_GROUP(5, 2))" + device ref usb2_port7 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A2"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, LEFT, ACPI_PLD_GROUP(5, 3))" + device ref usb2_port8 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A3"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(5, 4))" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A4"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(5, 4))" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B01)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(5, 1))" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, CENTER, ACPI_PLD_GROUP(5, 2))" + device ref usb3_port2 on end + end + end + end + end device ref i2c4 on chip drivers/i2c/tpm register "hid" = ""GOOG0005"" @@ -105,6 +257,44 @@ device i2c 50 on end end end + device ref soc_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + use conn2 as mux_conn[2] + use conn3 as mux_conn[3] + device pnp 0c09.0 on end + end + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + #USB2_C0 + use usb2_port2 as usb2_port + use tcss_usb3_port0 as usb3_port + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + #USB2_C1 + use usb2_port3 as usb2_port + use tcss_usb3_port2 as usb3_port + device generic 1 alias conn1 on end + end + chip drivers/intel/pmc_mux/conn + #USB2_C2 + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 2 alias conn2 on end + end + chip drivers/intel/pmc_mux/conn + #USB2_C3 + use usb2_port5 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 3 alias conn3 on end + end + end + end + end end - end -- To view, visit https://review.coreboot.org/c/coreboot/+/79356?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I90d3d984af6d40efb4553cf5675617700161d2d7 Gerrit-Change-Number: 79356 Gerrit-PatchSet: 1 Gerrit-Owner: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: mb/google/rex/variants/deku: Add basic DTT
by Eran Mitrani (Code Review) 01 Dec '23

01 Dec '23

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Subrata Banik, Tarun. Hello Dinesh Gehlot, Kapil Porwal, Subrata Banik, Tarun, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79353?usp=email to look at the new patch set (#3). Change subject: mb/google/rex/variants/deku: Add basic DTT ...................................................................... mb/google/rex/variants/deku: Add basic DTT Add default Intel DPTF. BUG=b:305793886 TEST=util/abuild/abuild -p none -t google/rex -x -a -b deku Signed-off-by: Eran Mitrani <mitrani(a)google.com> Change-Id: Id681754fc8e7b418de35f66df097cadd4aad7448 Signed-off-by: Eran Mitrani <mitrani(a)google.com> --- M src/mainboard/google/rex/variants/deku/overridetree.cb 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/79353/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/79353?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id681754fc8e7b418de35f66df097cadd4aad7448 Gerrit-Change-Number: 79353 Gerrit-PatchSet: 3 Gerrit-Owner: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: mb/google/rex/var/deku: Enable LAN0, LAN1
by Eran Mitrani (Code Review) 01 Dec '23

01 Dec '23

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Kapil Porwal, Subrata Banik, Tarun. Hello Dinesh Gehlot, Kapil Porwal, Paul Menzel, Subrata Banik, Tarun, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79292?usp=email to look at the new patch set (#10). Change subject: mb/google/rex/var/deku: Enable LAN0, LAN1 ...................................................................... mb/google/rex/var/deku: Enable LAN0, LAN1 google/deku is a Chromebox featuring two LAN ports. Add overridetree.cb entry to configure the LAN0 LAN1 devices. BUG=b:305793886 TEST=Built FW image correctly. Signed-off-by: Eran Mitrani <mitrani(a)google.com> Change-Id: I8980dabc7f9fc731a2b60c599e1e48c9b11dabb4 Signed-off-by: Eran Mitrani <mitrani(a)google.com> --- M src/mainboard/google/rex/variants/deku/gpio.c M src/mainboard/google/rex/variants/deku/overridetree.cb 2 files changed, 32 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/79292/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/79292?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8980dabc7f9fc731a2b60c599e1e48c9b11dabb4 Gerrit-Change-Number: 79292 Gerrit-PatchSet: 10 Gerrit-Owner: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[main]: soc/intel/xeon_sp: Redesign resource allocation
by Shuo Liu (Code Review) 01 Dec '23

01 Dec '23

Attention is currently required from: Arthur Heymans, Christian Walter, David Hendricks, Felix Held, Nill Ge, Patrick Rudolph, TangYiwei, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78327?usp=email ) Change subject: soc/intel/xeon_sp: Redesign resource allocation ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/xeon_sp/spr/chip.c: https://review.coreboot.org/c/coreboot/+/78327/comment/b9264756_22e3c52e : PS2, Line 51: noop_set_resources in our setting, pci_domain_set_resources is needed here. -- To view, visit https://review.coreboot.org/c/coreboot/+/78327?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idb29c24b71a18e2e092f9d4953d106e6ca0a5fe1 Gerrit-Change-Number: 78327 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Nill Ge <geshijian(a)bytedance.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nill Ge <geshijian(a)bytedance.com> Gerrit-Attention: TangYiwei Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 01 Dec 2023 01:26:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[main]: soc/intel/xeon_sp: Redesign resource allocation
by Shuo Liu (Code Review) 01 Dec '23

01 Dec '23

Attention is currently required from: Arthur Heymans, Christian Walter, David Hendricks, Felix Held, Nill Ge, Patrick Rudolph, TangYiwei, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78327?usp=email ) Change subject: soc/intel/xeon_sp: Redesign resource allocation ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: Hi, Arthur, we evaluated this CR and like the change. Here is some thoughts to sync with you and the loop. 1) We will move GNR codes based on this new design. Both GNR codes and your changes are based on multi-domain design, and hence theoretically they naturally and mutually fit. But GNR codes is based on FSP2.4 new IIO interface while SPR and previous gen are based on FSP2.3 or earlier, hence we need to seek some adoption logics to make the common codes to support both. For this, we could have separate discussion. 2) We evaluated this change on our SPR test machine and found that PCI resource setting is needed, otherwise, some legacy IO access (RTC, et al) might be mistakenly taken by BMC video device without BAR programed. This issue might not occur on every machine, but as a robustness enhancement, we suggest to take care in this CR as well. -- To view, visit https://review.coreboot.org/c/coreboot/+/78327?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idb29c24b71a18e2e092f9d4953d106e6ca0a5fe1 Gerrit-Change-Number: 78327 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Nill Ge <geshijian(a)bytedance.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nill Ge <geshijian(a)bytedance.com> Gerrit-Attention: TangYiwei Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 01 Dec 2023 01:24:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: libpayload: Fix the stack and data labels
by Yu-Ping Wu (Code Review) 01 Dec '23

01 Dec '23

Attention is currently required from: Julius Werner, Paul Menzel, Yi Chou. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79144?usp=email ) Change subject: libpayload: Fix the stack and data labels ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79144?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I589040f4db60b35813ea9f4ba9503244bd7def00 Gerrit-Change-Number: 79144 Gerrit-PatchSet: 8 Gerrit-Owner: Yi Chou <yich(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yi Chou <yich(a)google.com> Gerrit-Comment-Date: Fri, 01 Dec 2023 00:33:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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