Change in coreboot[master]: WIP: add WIP it8987e src/ec/hp/it8987e port and WIP src/mainboard/hp/...
by Matt Parnell (Code Review) 07 Aug '23
by Matt Parnell (Code Review) 07 Aug '23
07 Aug '23
Matt Parnell has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34946 )
Change subject: WIP: add WIP it8987e src/ec/hp/it8987e port and WIP src/mainboard/hp/spectre_x360_13t_ae000 port
......................................................................
WIP: add WIP it8987e src/ec/hp/it8987e port and WIP src/mainboard/hp/spectre_x360_13t_ae000 port
Change-Id: Ie744cdccd3d110b4137e0b017b3f8497d23c0497
---
A src/ec/hp/it8987e/Kconfig
A src/ec/hp/it8987e/Makefile.inc
A src/ec/hp/it8987e/acpi/ac.asl
A src/ec/hp/it8987e/acpi/battery.asl
A src/ec/hp/it8987e/acpi/ec.asl
A src/ec/hp/it8987e/acpi/kb.asl
A src/ec/hp/it8987e/acpi/superio.asl
A src/ec/hp/it8987e/acpi/tpm.asl
A src/ec/hp/it8987e/chip.h
A src/ec/hp/it8987e/ec.c
A src/ec/hp/it8987e/ec.h
A src/mainboard/hp/spectre_x360_13t_ae000/Kconfig
A src/mainboard/hp/spectre_x360_13t_ae000/Kconfig.name
A src/mainboard/hp/spectre_x360_13t_ae000/Makefile.inc
A src/mainboard/hp/spectre_x360_13t_ae000/acpi/ac.asl
A src/mainboard/hp/spectre_x360_13t_ae000/acpi/battery.asl
A src/mainboard/hp/spectre_x360_13t_ae000/acpi/ec.asl
A src/mainboard/hp/spectre_x360_13t_ae000/acpi/kb.asl
A src/mainboard/hp/spectre_x360_13t_ae000/acpi/mainboard.asl
A src/mainboard/hp/spectre_x360_13t_ae000/acpi/superio.asl
A src/mainboard/hp/spectre_x360_13t_ae000/acpi/tpm.asl
A src/mainboard/hp/spectre_x360_13t_ae000/acpi_tables.c
A src/mainboard/hp/spectre_x360_13t_ae000/board_info.txt
A src/mainboard/hp/spectre_x360_13t_ae000/devicetree.cb
A src/mainboard/hp/spectre_x360_13t_ae000/dsdt.asl
A src/mainboard/hp/spectre_x360_13t_ae000/gpio.h
A src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.c
A src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.h
A src/mainboard/hp/spectre_x360_13t_ae000/mainboard.c
A src/mainboard/hp/spectre_x360_13t_ae000/ramstage.c
A src/mainboard/hp/spectre_x360_13t_ae000/romstage.c
31 files changed, 5,065 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/34946/1
diff --git a/src/ec/hp/it8987e/Kconfig b/src/ec/hp/it8987e/Kconfig
new file mode 100644
index 0000000..54f7896
--- /dev/null
+++ b/src/ec/hp/it8987e/Kconfig
@@ -0,0 +1,4 @@
+config EC_HP_IT8987E
+ bool
+ help
+ Interface to QUANTA/HP IT8987E Embedded Controller.
diff --git a/src/ec/hp/it8987e/Makefile.inc b/src/ec/hp/it8987e/Makefile.inc
new file mode 100644
index 0000000..db11205
--- /dev/null
+++ b/src/ec/hp/it8987e/Makefile.inc
@@ -0,0 +1,8 @@
+ifeq ($(CONFIG_EC_HP_IT8987E),y)
+
+romstage-y += ec.c
+ramstage-y += ec.c
+smm-y += ec.c
+smm-y += ../../../lib/delay.c
+
+endif
diff --git a/src/ec/hp/it8987e/acpi/ac.asl b/src/ec/hp/it8987e/acpi/ac.asl
new file mode 100644
index 0000000..bb4b4fe
--- /dev/null
+++ b/src/ec/hp/it8987e/acpi/ac.asl
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+// Scope (EC0)
+
+Device (AC)
+{
+ Name (_HID, "ACPI0003")
+ Name (_PCL, Package () { \_SB })
+
+ Method (_PSR, 0, NotSerialized) // _PSR: Power Source
+ {
+ If ((^^PCI0.LPCB.EC0.ECOK == One))
+ {
+ Local0 = ^^PCI0.LPCB.EC0.SW2S
+ }
+ Else
+ {
+ Local0 = One
+ }
+
+ Return (Local0)
+ }
+
+ Method (_STA)
+ {
+ Return (0x0F)
+ }
+}
diff --git a/src/ec/hp/it8987e/acpi/battery.asl b/src/ec/hp/it8987e/acpi/battery.asl
new file mode 100644
index 0000000..75efd92
--- /dev/null
+++ b/src/ec/hp/it8987e/acpi/battery.asl
@@ -0,0 +1,252 @@
+/*
+* This file is part of the coreboot project.
+*
+* Copyright (C) 2013 Google Inc.
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as
+* published by the Free Software Foundation; version 2 of
+* the License.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*/
+
+Device (BAT0)
+{
+ Name (FRST, One)
+ Name (_HID, EisaId ("PNP0C0A") /* Control Method Battery */) // _HID: Hardware ID
+ Name (_UID, One) // _UID: Unique ID
+ Name (_PCL, Package (0x01) // _PCL: Power Consumer List
+ {
+ _SB
+ })
+ Name (PBIF, Package (0x0D)
+ {
+ One,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ One,
+ 0xFFFFFFFF,
+ 0xFA,
+ 0x96,
+ 0x0A,
+ 0x19,
+ "BAT0",
+ " ",
+ " ",
+ " "
+ })
+ Name (PBST, Package (0x04)
+ {
+ Zero,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0x2710
+ })
+ Name (BAST, Zero)
+ Name (B1ST, 0x0F)
+ Name (B1WT, Zero)
+ Name (FABL, 0xFFFFFFFF)
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ If ((^^PCI0.LPCB.EC0.ECOK == One))
+ {
+ If (^^PCI0.LPCB.EC0.MBTS)
+ {
+ B1ST = 0x1F
+ }
+ Else
+ {
+ B1ST = 0x0F
+ }
+ }
+ Else
+ {
+ B1ST = 0x0F
+ }
+
+ Return (B1ST) /* \_SB_.BAT0.B1ST */
+ }
+
+ Method (_BIF, 0, NotSerialized) // _BIF: Battery Information
+ {
+ If ((^^PCI0.LPCB.EC0.ECOK == One))
+ {
+ If (^^PCI0.LPCB.EC0.MBTS)
+ {
+ UPBI ()
+ }
+ Else
+ {
+ IVBI ()
+ }
+ }
+ Else
+ {
+ IVBI ()
+ }
+
+ Return (PBIF) /* \_SB_.BAT0.PBIF */
+ }
+
+ Method (_BST, 0, NotSerialized) // _BST: Battery Status
+ {
+ If ((^^PCI0.LPCB.EC0.ECOK == One))
+ {
+ If (^^PCI0.LPCB.EC0.MBTS)
+ {
+ UPBS ()
+ }
+ Else
+ {
+ IVBS ()
+ }
+ }
+ Else
+ {
+ IVBS ()
+ }
+
+ Return (PBST) /* \_SB_.BAT0.PBST */
+ }
+
+ Method (UPBI, 0, NotSerialized)
+ {
+ Local5 = ^^PCI0.LPCB.EC0.BFCC /* \_SB_.PCI0.LPCB.EC0_.BFCC */
+ If ((Local5 && !(Local5 & 0x8000)))
+ {
+ Local5 >>= 0x05
+ Local5 <<= 0x05
+ PBIF [One] = Local5
+ PBIF [0x02] = Local5
+ Local2 = (Local5 / 0x64)
+ Local2 += One
+ If ((^^PCI0.LPCB.EC0.BADC < 0x0C80))
+ {
+ Local4 = (Local2 * 0x0E)
+ PBIF [0x05] = (Local4 + 0x02)
+ Local4 = (Local2 * 0x09)
+ PBIF [0x06] = (Local4 + 0x02)
+ Local4 = (Local2 * 0x0B)
+ }
+ ElseIf ((SMA4 == One))
+ {
+ Local4 = (Local2 * 0x0A)
+ PBIF [0x05] = (Local4 + 0x02)
+ Local4 = (Local2 * 0x05)
+ PBIF [0x06] = (Local4 + 0x02)
+ Local4 = (Local2 * 0x08)
+ }
+ Else
+ {
+ Local4 = (Local2 * 0x0C)
+ PBIF [0x05] = (Local4 + 0x02)
+ Local4 = (Local2 * 0x07)
+ PBIF [0x06] = (Local4 + 0x02)
+ Local4 = (Local2 * 0x0A)
+ }
+
+ FABL = (Local4 + 0x02)
+ }
+
+ Local0 = ^^PCI0.LPCB.EC0.BVLB /* \_SB_.PCI0.LPCB.EC0_.BVLB */
+ Local1 = ^^PCI0.LPCB.EC0.BVHB /* \_SB_.PCI0.LPCB.EC0_.BVHB */
+ Local1 <<= 0x08
+ Local0 |= Local1
+ PBIF [0x04] = Local0
+ Sleep (0x32)
+ PBIF [0x0B] = "LION"
+ PBIF [0x09] = "Primary"
+ UPUM ()
+ PBIF [Zero] = One
+ }
+
+ Method (UPUM, 0, NotSerialized)
+ {
+ Local0 = Buffer (0x0A)
+ {
+ /* 0000 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........
+ /* 0008 */ 0x00, 0x00 // ..
+ }
+ Local6 = Buffer (0x05)
+ {
+ 0x36, 0x35, 0x35, 0x33, 0x35 // 65535
+ }
+ Local7 = Buffer (0x05)
+ {
+ 0x31, 0x32, 0x33, 0x32, 0x31 // 12321
+ }
+ PBIF [0x0C] = "HP"
+ }
+
+ Method (UPBS, 0, NotSerialized)
+ {
+ If ((BRTM == One))
+ {
+ Local0 = ^^PCI0.LPCB.EC0.MCUR /* \_SB_.PCI0.LPCB.EC0_.MCUR */
+ If ((Local0 & 0x8000))
+ {
+ If ((Local0 == 0xFFFF))
+ {
+ PBST [One] = 0xFFFFFFFF
+ }
+ Else
+ {
+ Local1 = ~Local0
+ Local1++
+ Local3 = (Local1 & 0xFFFF)
+ PBST [One] = Local3
+ }
+ }
+ Else
+ {
+ PBST [One] = Local0
+ }
+ }
+ Else
+ {
+ PBST [One] = 0xFFFFFFFF
+ }
+
+ Local5 = ^^PCI0.LPCB.EC0.MBRM /* \_SB_.PCI0.LPCB.EC0_.MBRM */
+ If (!(Local5 & 0x8000))
+ {
+ Local5 >>= 0x05
+ Local5 <<= 0x05
+ If ((Local5 != DerefOf (PBST [0x02])))
+ {
+ PBST [0x02] = Local5
+ }
+ }
+
+ If ((!^^PCI0.LPCB.EC0.SW2S && (^^PCI0.LPCB.EC0.BACR == One)))
+ {
+ PBST [0x02] = FABL /* \_SB_.BAT0.FABL */
+ }
+
+ PBST [0x03] = ^^PCI0.LPCB.EC0.MBCV /* \_SB_.PCI0.LPCB.EC0_.MBCV */
+ PBST [Zero] = ^^PCI0.LPCB.EC0.MBST /* \_SB_.PCI0.LPCB.EC0_.MBST */
+ }
+
+ Method (IVBI, 0, NotSerialized)
+ {
+ PBIF [One] = 0xFFFFFFFF
+ PBIF [0x02] = 0xFFFFFFFF
+ PBIF [0x04] = 0xFFFFFFFF
+ PBIF [0x09] = "Bad"
+ PBIF [0x0A] = "Bad"
+ PBIF [0x0B] = "Bad"
+ PBIF [0x0C] = "Bad"
+ }
+
+ Method (IVBS, 0, NotSerialized)
+ {
+ PBST [Zero] = Zero
+ PBST [One] = 0xFFFFFFFF
+ PBST [0x02] = 0xFFFFFFFF
+ PBST [0x03] = 0x2710
+ }
+}
diff --git a/src/ec/hp/it8987e/acpi/ec.asl b/src/ec/hp/it8987e/acpi/ec.asl
new file mode 100644
index 0000000..0692ced
--- /dev/null
+++ b/src/ec/hp/it8987e/acpi/ec.asl
@@ -0,0 +1,1201 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * The mainboard must define a PNOT method to handle power
+ * state notifications and Notify CPU device objects to
+ * re-evaluate their _PPC and _CST tables.
+ */
+
+Device (EC0)
+{
+ Name (_HID, EisaId ("PNP0C09") /* Embedded Controller Device */) // _HID: Hardware ID
+ Name (_UID, One) // _UID: Unique ID
+ Name (PHOT, One)
+ Name (ECAV, Zero)
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Name (BFFR, ResourceTemplate ()
+ {
+ IO (Decode16,
+ 0x0062, // Range Minimum
+ 0x0062, // Range Maximum
+ 0x00, // Alignment
+ 0x01, // Length
+ )
+ IO (Decode16,
+ 0x0066, // Range Minimum
+ 0x0066, // Range Maximum
+ 0x00, // Alignment
+ 0x01, // Length
+ )
+ })
+ Return (BFFR) /* \_SB_.PCI0.LPCB.EC0_._CRS.BFFR */
+ }
+
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ ^^^GFX0.CLID = 0x03
+ Return (0x0F)
+ }
+
+ OperationRegion (ERAM, EmbeddedControl, Zero, 0xFF)
+ Field (ERAM, ByteAcc, NoLock, Preserve)
+ {
+ SMPR, 8,
+ SMST, 8,
+ SMAD, 8,
+ SMCM, 8,
+ SMD0, 256,
+ BCNT, 8,
+ SMAA, 8,
+ Offset (0x40),
+ SW2S, 1,
+ , 2,
+ ACCC, 1,
+ TRPM, 1,
+ Offset (0x41),
+ W7OS, 1,
+ QWOS, 1,
+ , 1,
+ SUSE, 1,
+ RFLG, 1,
+ Offset (0x43),
+ , 1,
+ , 1,
+ ACPS, 1,
+ ACKY, 1,
+ GFXT, 1,
+ Offset (0x44),
+ , 7,
+ DSMB, 1,
+ Offset (0x47),
+ TNT2, 8,
+ TNT3, 8,
+ Offset (0x4C),
+ STRM, 8,
+ Offset (0x4E),
+ LIDE, 1,
+ Offset (0x4F),
+ ACID, 8,
+ , 2,
+ PTHM, 1,
+ , 1,
+ BSEV, 1,
+ DPTL, 1,
+ Offset (0x52),
+ ECLS, 1,
+ Offset (0x55),
+ EC45, 8,
+ Offset (0x58),
+ RTMP, 8,
+ TNT1, 8,
+ Offset (0x5F),
+ , 1,
+ Offset (0x61),
+ SHPM, 8,
+ Offset (0x67),
+ , 1,
+ , 1,
+ GC6R, 1,
+ IGC6, 1,
+ , 2,
+ PVSE, 1,
+ PVSS, 1,
+ , 3,
+ PLGS, 1,
+ , 3,
+ TPDF, 1,
+ , 4,
+ BCTF, 1,
+ BMNF, 1,
+ BTVD, 1,
+ BF10, 1,
+ Offset (0x6C),
+ GWKR, 8,
+ Offset (0x70),
+ BADC, 16,
+ BFCC, 16,
+ BVLB, 8,
+ BVHB, 8,
+ BDVO, 8,
+ Offset (0x7F),
+ ECTB, 1,
+ Offset (0x82),
+ MBST, 8,
+ MCUR, 16,
+ MBRM, 16,
+ MBCV, 16,
+ Offset (0x8B),
+ LEDM, 3,
+ Offset (0x8D),
+ , 5,
+ MBFC, 1,
+ Offset (0x92),
+ SPSV, 8,
+ Offset (0x94),
+ GSSU, 1,
+ GSMS, 1,
+ Offset (0x95),
+ MMST, 4,
+ DMST, 4,
+ Offset (0xA0),
+ QBHK, 8,
+ Offset (0xA2),
+ QBBB, 8,
+ Offset (0xA4),
+ MBTS, 1,
+ , 6,
+ BACR, 1,
+ Offset (0xA6),
+ MBDC, 8,
+ Offset (0xA8),
+ ENWD, 1,
+ TMPR, 1,
+ Offset (0xAA),
+ , 1,
+ SMSZ, 1,
+ , 5,
+ RCDS, 1,
+ Offset (0xAD),
+ SADP, 8,
+ Offset (0xB2),
+ RPM1, 8,
+ RPM2, 8,
+ Offset (0xBA),
+ CLOW, 8,
+ CMAX, 8,
+ Offset (0xC1),
+ DPPC, 8,
+ Offset (0xC6),
+ , 1,
+ CVTS, 1,
+ Offset (0xCE),
+ NVDX, 8,
+ ECDX, 8,
+ EBPL, 1,
+ Offset (0xD2),
+ , 7,
+ DLYE, 1,
+ Offset (0xD4),
+ PSHD, 8,
+ PSLD, 8,
+ DBPL, 8,
+ STSP, 8,
+ Offset (0xDA),
+ PSIN, 8,
+ PSKB, 1,
+ PSTP, 1,
+ , 1,
+ PWOL, 1,
+ RTCE, 1,
+ Offset (0xE0),
+ DLYT, 8,
+ DLY2, 8,
+ Offset (0xE6),
+ SFHK, 8,
+ Offset (0xE9),
+ DTMT, 8,
+ PL12, 8,
+ ETMT, 8,
+ Offset (0xF2),
+ ZPDD, 1,
+ , 6,
+ ENPA, 1,
+ Offset (0xF4),
+ SFAN, 8,
+ Offset (0xF9),
+ , 7,
+ FTHM, 1
+ }
+
+ Name (ECOK, Zero)
+ Name (BATO, Zero)
+ Name (BATN, Zero)
+ Name (BATF, 0xC0)
+ Name (TMEE, Zero)
+ Name (TMDE, Zero)
+ Method (_REG, 2, NotSerialized) // _REG: Region Availability
+ {
+ If (((Arg0 == 0x03) && (Arg1 == One)))
+ {
+ ECOK = One
+ GBAS ()
+ ECMI ()
+ }
+ }
+
+ Method (_GPE, 0, NotSerialized) // _GPE: General Purpose Events
+ {
+ Local0 = GGPE (0x02020017)
+ Return (Local0)
+ }
+
+ Method (BPOL, 1, NotSerialized)
+ {
+ DBPL = Arg0
+ EBPL = One
+ }
+
+ Method (BPOM, 0, NotSerialized)
+ {
+ DBPL = Zero
+ EBPL = Zero
+ }
+
+ Method (GBAS, 0, NotSerialized)
+ {
+ If ((ECOK == One))
+ {
+ BATF = Zero
+ Local0 = MBTS /* \_SB_.PCI0.LPCB.EC0_.MBTS */
+ Local1 = SW2S /* \_SB_.PCI0.LPCB.EC0_.SW2S */
+ Local0 <<= 0x06
+ Local1 <<= One
+ If (((BATO & 0x40) != Local0))
+ {
+ BATF |= 0x40
+ }
+
+ If (((BATO & 0x02) != Local1))
+ {
+ BATF |= 0x02
+ }
+
+ BATO = Zero
+ BATO = (Local0 | Local1)
+ }
+ }
+
+ Method (_Q09, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ BPOM ()
+ GBAS ()
+ Notify (BAT0, 0x80) // Status Change
+ Notify (BAT0, 0x81) // Information Change
+ Notify (ADP1, 0x80) // Status Change
+ }
+
+ Method (_Q0D, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ Debug = "_Q0D : Switch Display (Fn+F4)"
+ ^^^GFX0.GHDS (Zero)
+ Sleep (0xC8)
+ }
+
+ Method (_Q10, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ Notify (^^^GFX0.DD1F, 0x87) // Device-Specific
+ }
+
+ Method (_Q11, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ Notify (^^^GFX0.DD1F, 0x86) // Device-Specific
+ }
+
+ Method (_Q15, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ Debug = "!!! Wireless Button pressed !!!"
+ If ((OSYS >= 0x07DC))
+ {
+ Notify (WLBT, 0x80) // Status Change
+ }
+ Else
+ {
+ If (BNLS)
+ {
+ BNLS = Zero
+ Local0 = One
+ }
+ Else
+ {
+ BNLS = One
+ Local0 = Zero
+ }
+
+ If ((^^^^WMID.WMIF == One))
+ {
+ If (((WWLS == One) & (WLDS == One)))
+ {
+ If (One)
+ {
+ SGOV (0x02070002, Local0)
+ }
+ Else
+ {
+ SGOV (0x01090008, Local0)
+ }
+ }
+
+ If (((WBTS == One) & (BTDS == One)))
+ {
+ If (One)
+ {
+ SGOV (0x0203000C, Local0)
+ }
+ Else
+ {
+ SGOV (0x0103000C, Local0)
+ }
+ }
+ }
+ Else
+ {
+ If ((WLDS == One))
+ {
+ If (One)
+ {
+ SGOV (0x02070002, Local0)
+ }
+ Else
+ {
+ SGOV (0x01090008, Local0)
+ }
+ }
+
+ If ((BTDS == One))
+ {
+ If (One)
+ {
+ SGOV (0x0203000C, Local0)
+ }
+ Else
+ {
+ SGOV (0x0103000C, Local0)
+ }
+ }
+ }
+ }
+ }
+
+ Method (_Q20, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ If ((ECOK == One))
+ {
+ GBAS ()
+ If ((0x40 & BATF))
+ {
+ Notify (BAT0, 0x81) // Information Change
+ }
+
+ Notify (BAT0, 0x80) // Status Change
+ If ((0x02 & BATF))
+ {
+ Notify (ADP1, 0x80) // Status Change
+ PWRS = SW2S /* \_SB_.PCI0.LPCB.EC0_.SW2S */
+ If (SW2S)
+ {
+ ^^^^WMID.GWEV (0x03, Zero)
+ }
+ }
+
+ PNOT ()
+ }
+ }
+
+ Method (_Q21, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ If ((ECOK == One))
+ {
+ If ((BCTF || BMNF))
+ {
+ ^^^^WMID.GWEV (0x12, One)
+ }
+ }
+ }
+
+ Method (_Q22, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ If ((ECOK == One))
+ {
+ BACR = Zero
+ Notify (BAT0, 0x80) // Status Change
+ }
+ }
+
+ Method (_Q2A, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ Notify (BAT0, 0x81) // Information Change
+ Notify (BAT0, 0x80) // Status Change
+ }
+
+ Method (_Q33, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ Local0 = ^^RTC.RTMN /* \_SB_.PCI0.LPCB.RTC_.RTMN */
+ FromBCD (Local0, Local0)
+ Local1 = ^^RTC.RTHR /* \_SB_.PCI0.LPCB.RTC_.RTHR */
+ FromBCD (Local1, Local1)
+ Local2 = ^^RTC.RTDY /* \_SB_.PCI0.LPCB.RTC_.RTDY */
+ Local3 = ^^RTC.RTSE /* \_SB_.PCI0.LPCB.RTC_.RTSE */
+ FromBCD (Local3, Local3)
+ If ((ECOK == One))
+ {
+ PSIN = 0xFF
+ Sleep (One)
+ PSLD = Local0
+ PSHD = Local1
+ PSIN = 0x1C
+ Sleep (One)
+ PSLD = Local2
+ PSHD = Local3
+ PSIN = 0x1D
+ }
+ }
+
+ Method (_Q34, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ If ((ECOK == One))
+ {
+ If ((ENWD == One))
+ {
+ TMPR = One
+ }
+ }
+ }
+
+ Method (_Q46, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ If ((ECOK == One))
+ {
+ If ((CVTS == One))
+ {
+ Local0 = 0x03
+ Local0 <<= 0x10
+ Local0 |= 0x03
+ ^^^^WFTE.WMDE (Zero, One, Local0)
+ Notify (VBPA, 0xCC) // Hardware-Specific
+ }
+
+ If ((CVTS == Zero))
+ {
+ Local0 = 0x02
+ Local0 <<= 0x10
+ Local0 |= 0x02
+ ^^^^WFTE.WMDE (Zero, One, Local0)
+ Notify (VBPA, 0xCD) // Hardware-Specific
+ }
+ }
+ }
+
+ Method (_Q49, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ If ((ECOK == One))
+ {
+ If ((PVSS == One))
+ {
+ If ((PVSE == One))
+ {
+ ^^^^WMID.GWEV (0x14, 0xFE)
+ }
+ Else
+ {
+ ^^^^WMID.GWEV (0x14, 0xFF)
+ }
+ }
+ }
+ }
+
+ Method (_Q4D, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ ^^^^WMID.GWEV (0x00020001, Zero)
+ }
+
+ Method (_Q6F, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ ^^^^WMID.GWEV (0x04, Zero)
+ }
+
+ Method (_Q70, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ SGOV (0x0204000A, Zero)
+ }
+
+ Method (_Q71, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ SGOV (0x0204000A, One)
+ }
+
+ Method (_Q80, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ Sleep (0x14)
+ Notify (\_TZ.TZ01, 0x80) // Thermal Status Change
+ }
+
+ Method (_Q82, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ Sleep (0x14)
+ Debug = "_Q82 : Temperature reachs for Turbo Mode OFF"
+ TMDE = One
+ Notify (\_TZ.TZ01, 0x80) // Thermal Status Change
+ }
+
+ Method (_Q83, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ Sleep (0x14)
+ Debug = "_Q83 : Temperature reachs for Turbo Mode ON"
+ TMEE = One
+ Notify (\_TZ.TZ01, 0x80) // Thermal Status Change
+ }
+
+ Method (_Q84, 0, Serialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ If ((PHOT == One))
+ {
+ PHOT = 0x02
+ }
+ }
+
+ Method (_Q85, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ Notify (B0D4, 0x90) // Device-Specific
+ }
+
+ Method (_Q86, 0, Serialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ If ((PHOT == One))
+ {
+ PHOT = 0x03
+ }
+ }
+
+ Method (_Q8A, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ If ((ECOK == One))
+ {
+ If (LIDE)
+ {
+ Debug = "_Q8A : LID Switch Event"
+ LIDE = Zero
+ Sleep (0x14)
+ Notify (LID0, 0x80) // Status Change
+ }
+ }
+ }
+
+ Method (_Q8E, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ If (CondRefOf (\_PR.PR00._PPC))
+ {
+ Local0 = \_PR.PR00._PPC ()
+ }
+
+ Local1 = (MPPP - One)
+ If ((Local0 < Local1))
+ {
+ Local0++
+ CPUS (Local0)
+ }
+
+ CLOW = Local0
+ }
+
+ Method (_Q8F, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ If (CondRefOf (\_PR.PR00._PPC))
+ {
+ Local0 = \_PR.PR00._PPC ()
+ }
+
+ If (Local0)
+ {
+ Local0--
+ CPUS (Local0)
+ }
+
+ CLOW = Local0
+ }
+
+ Method (_Q99, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ }
+
+ Method (_QA0, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ }
+
+ Method (_QA1, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ }
+
+ Method (_QE4, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ Local1 = Zero
+ Local0 = PKPS /* \PKPS */
+ If ((Local0 > 0x80))
+ {
+ Local0 -= 0x80
+ While ((Local0 > 0x06))
+ {
+ Local0 -= 0x10
+ Local1 += 0x06
+ }
+
+ Local1 += Local0
+ If (((Local1 >= 0x07) & (Local1 <= 0x0C)))
+ {
+ Local1 += 0x12
+ }
+ ElseIf (((Local1 >= 0x0D) & (Local1 <= 0x12)))
+ {
+ Local1 += 0x06
+ }
+ ElseIf (((Local1 >= 0x13) & (Local1 <= 0x18)))
+ {
+ Local1 -= 0x0C
+ }
+ ElseIf (((Local1 >= 0x19) & (Local1 <= 0x1E)))
+ {
+ Local1 -= 0x0C
+ }
+
+ Stall (0x05)
+ Local0 = Zero
+ Local3 = OFDA /* \OFDA */
+ While ((Local1 > One))
+ {
+ Local2 = DerefOf (Local3 [Local0])
+ Local0 += Local2
+ Local1 -= One
+ }
+
+ Stall (0x0F)
+ Local1 = DerefOf (Local3 [Local0])
+ Local2 = Zero
+ Stall (0x0F)
+ Name (KPFT, Buffer (0xA0){})
+ While ((Local2 < 0xA0))
+ {
+ If ((Local1 > Zero))
+ {
+ KPFT [Local2] = DerefOf (Local3 [Local0])
+ Local0++
+ Local1 -= One
+ }
+ Else
+ {
+ KPFT [Local2] = Zero
+ }
+
+ Local2++
+ Stall (0x05)
+ }
+
+ PKMC = KPFT /* \_SB_.PCI0.LPCB.EC0_._QE4.KPFT */
+ PKWD = One
+ }
+ }
+
+ Method (_QE5, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ ^^^^WMID.GWEV (0x12, PKPS)
+ }
+
+ Field (ERAM, ByteAcc, NoLock, Preserve)
+ {
+ Offset (0x04),
+ SMW0, 16
+ }
+
+ Field (ERAM, ByteAcc, NoLock, Preserve)
+ {
+ Offset (0x04),
+ SMB0, 8
+ }
+
+ Field (ERAM, ByteAcc, NoLock, Preserve)
+ {
+ Offset (0x04),
+ FLD0, 64
+ }
+
+ Field (ERAM, ByteAcc, NoLock, Preserve)
+ {
+ Offset (0x04),
+ FLD1, 128
+ }
+
+ Field (ERAM, ByteAcc, NoLock, Preserve)
+ {
+ Offset (0x04),
+ FLD2, 192
+ }
+
+ Field (ERAM, ByteAcc, NoLock, Preserve)
+ {
+ Offset (0x04),
+ FLD3, 256
+ }
+
+ Mutex (MUT0, 0x00)
+ Mutex (MUT1, 0x00)
+ Mutex (MUT2, 0x00)
+ Method (SMRD, 4, NotSerialized)
+ {
+ If (!ECOK)
+ {
+ Return (0xFF)
+ }
+
+ If ((Arg0 != 0x07))
+ {
+ If ((Arg0 != 0x09))
+ {
+ If ((Arg0 != 0x0B))
+ {
+ If ((Arg0 != 0x47))
+ {
+ If ((Arg0 != 0xC7))
+ {
+ Return (0x19)
+ }
+ }
+ }
+ }
+ }
+
+ Acquire (MUT0, 0xFFFF)
+ Local0 = 0x04
+ While ((Local0 > One))
+ {
+ SMST &= 0x40
+ SMCM = Arg2
+ SMAD = Arg1
+ SMPR = Arg0
+ Local3 = Zero
+ While (!Local1 = (SMST & 0xBF))
+ {
+ Sleep (0x02)
+ Local3++
+ If ((Local3 == 0x32))
+ {
+ SMST &= 0x40
+ SMCM = Arg2
+ SMAD = Arg1
+ SMPR = Arg0
+ Local3 = Zero
+ }
+ }
+
+ If ((Local1 == 0x80))
+ {
+ Local0 = Zero
+ }
+ Else
+ {
+ Local0--
+ }
+ }
+
+ If (Local0)
+ {
+ Local0 = (Local1 & 0x1F)
+ }
+ Else
+ {
+ If ((Arg0 == 0x07))
+ {
+ Arg3 = SMB0 /* \_SB_.PCI0.LPCB.EC0_.SMB0 */
+ }
+
+ If ((Arg0 == 0x47))
+ {
+ Arg3 = SMB0 /* \_SB_.PCI0.LPCB.EC0_.SMB0 */
+ }
+
+ If ((Arg0 == 0xC7))
+ {
+ Arg3 = SMB0 /* \_SB_.PCI0.LPCB.EC0_.SMB0 */
+ }
+
+ If ((Arg0 == 0x09))
+ {
+ Arg3 = SMW0 /* \_SB_.PCI0.LPCB.EC0_.SMW0 */
+ }
+
+ If ((Arg0 == 0x0B))
+ {
+ Local3 = BCNT /* \_SB_.PCI0.LPCB.EC0_.BCNT */
+ Local2 = 0x20
+ If ((Local3 > Local2))
+ {
+ Local3 = Local2
+ }
+
+ If ((Local3 < 0x11))
+ {
+ Local2 = FLD1 /* \_SB_.PCI0.LPCB.EC0_.FLD1 */
+ }
+ ElseIf ((Local3 < 0x19))
+ {
+ Local2 = FLD2 /* \_SB_.PCI0.LPCB.EC0_.FLD2 */
+ }
+ Else
+ {
+ Local2 = FLD3 /* \_SB_.PCI0.LPCB.EC0_.FLD3 */
+ }
+
+ Local3++
+ Local4 = Buffer (Local3){}
+ Local3--
+ Local5 = Zero
+ Name (OEMS, Buffer (0x46){})
+ ToBuffer (Local2, OEMS) /* \_SB_.PCI0.LPCB.EC0_.SMRD.OEMS */
+ While ((Local3 > Local5))
+ {
+ GBFE (OEMS, Local5, RefOf (Local6))
+ PBFE (Local4, Local5, Local6)
+ Local5++
+ }
+
+ PBFE (Local4, Local5, Zero)
+ Arg3 = Local4
+ }
+ }
+
+ Release (MUT0)
+ Return (Local0)
+ }
+
+ Method (SMWR, 4, NotSerialized)
+ {
+ If (!ECOK)
+ {
+ Return (0xFF)
+ }
+
+ If ((Arg0 != 0x06))
+ {
+ If ((Arg0 != 0x08))
+ {
+ If ((Arg0 != 0x0A))
+ {
+ If ((Arg0 != 0x46))
+ {
+ If ((Arg0 != 0xC6))
+ {
+ Return (0x19)
+ }
+ }
+ }
+ }
+ }
+
+ Acquire (MUT0, 0xFFFF)
+ Local0 = 0x04
+ While ((Local0 > One))
+ {
+ If ((Arg0 == 0x06))
+ {
+ SMB0 = Arg3
+ }
+
+ If ((Arg0 == 0x46))
+ {
+ SMB0 = Arg3
+ }
+
+ If ((Arg0 == 0xC6))
+ {
+ SMB0 = Arg3
+ }
+
+ If ((Arg0 == 0x08))
+ {
+ SMW0 = Arg3
+ }
+
+ If ((Arg0 == 0x0A))
+ {
+ SMD0 = Arg3
+ }
+
+ SMST &= 0x40
+ SMCM = Arg2
+ SMAD = Arg1
+ SMPR = Arg0
+ Local3 = Zero
+ While (!Local1 = (SMST & 0xBF))
+ {
+ Sleep (0x02)
+ Local3++
+ If ((Local3 == 0x32))
+ {
+ SMST &= 0x40
+ SMCM = Arg2
+ SMAD = Arg1
+ SMPR = Arg0
+ Local3 = Zero
+ }
+ }
+
+ If ((Local1 == 0x80))
+ {
+ Local0 = Zero
+ }
+ Else
+ {
+ Local0--
+ }
+ }
+
+ If (Local0)
+ {
+ Local0 = (Local1 & 0x1F)
+ }
+
+ Release (MUT0)
+ Return (Local0)
+ }
+
+ Method (GSHK, 0, Serialized)
+ {
+ If ((ECOK == One))
+ {
+ Local0 = SFHK /* \_SB_.PCI0.LPCB.EC0_.SFHK */
+ }
+
+ Return (Local0)
+ }
+
+ Method (SSHK, 1, Serialized)
+ {
+ If ((ECOK == One))
+ {
+ SFHK = Arg0
+ }
+ }
+
+ Method (CPUS, 1, NotSerialized)
+ {
+ If (CondRefOf (\_PR.PR00._PPC))
+ {
+ \_PR.CPPC = Arg0
+ }
+
+ If ((TCNT == 0x08))
+ {
+ Notify (\_PR.PR00, 0x80) // Performance Capability Change
+ Notify (\_PR.PR01, 0x80) // Performance Capability Change
+ Notify (\_PR.PR02, 0x80) // Performance Capability Change
+ Notify (\_PR.PR03, 0x80) // Performance Capability Change
+ Notify (\_PR.PR04, 0x80) // Performance Capability Change
+ Notify (\_PR.PR05, 0x80) // Performance Capability Change
+ Notify (\_PR.PR06, 0x80) // Performance Capability Change
+ Notify (\_PR.PR07, 0x80) // Performance Capability Change
+ }
+
+ If ((TCNT == 0x04))
+ {
+ Notify (\_PR.PR00, 0x80) // Performance Capability Change
+ Notify (\_PR.PR01, 0x80) // Performance Capability Change
+ Notify (\_PR.PR02, 0x80) // Performance Capability Change
+ Notify (\_PR.PR03, 0x80) // Performance Capability Change
+ }
+
+ If ((TCNT == 0x02))
+ {
+ Notify (\_PR.PR00, 0x80) // Performance Capability Change
+ Notify (\_PR.PR01, 0x80) // Performance Capability Change
+ }
+ Else
+ {
+ Notify (\_PR.PR00, 0x80) // Performance Capability Change
+ }
+ }
+
+ Method (ECMI, 0, NotSerialized)
+ {
+ If ((ECOK == One))
+ {
+ OSTD ()
+ CLOW = Zero
+ CMAX = (MPPP - One)
+ ACKY = FNKY /* \FNKY */
+ SASU ()
+ If ((SMA4 == One))
+ {
+ SMSZ = Zero
+ }
+ Else
+ {
+ SMSZ = One
+ }
+
+ ULID (Zero)
+ }
+ }
+
+ Method (SASU, 0, NotSerialized)
+ {
+ If ((ECOK == One))
+ {
+ If (CondRefOf (\_PR.PR00._PPC))
+ {
+ Local0 = \_PR.PR00._PPC ()
+ }
+
+ Local1 = (MPPP - One)
+ If (((SW2S == Zero) || ((SADP >= One) & (
+ SADP <= 0x02))))
+ {
+ Local0 = Zero
+ CPUS (Local0)
+ CLOW = Local0
+ }
+
+ If ((SADP == 0x03))
+ {
+ If ((Local0 < Local1))
+ {
+ Local0++
+ CPUS (Local0)
+ CLOW = Local0
+ }
+ }
+ }
+ }
+
+ Method (RPIO, 2, NotSerialized)
+ {
+ Local0 = Zero
+ If ((ECOK == One))
+ {
+ EI01 = Arg0
+ EI02 = Arg1
+ Local0 = EI03 /* \EI03 */
+ }
+
+ Return (Local0)
+ }
+
+ Method (WPIO, 3, NotSerialized)
+ {
+ If ((ECOK == One))
+ {
+ EI01 = Arg0
+ EI02 = Arg1
+ EI03 = Arg2
+ }
+ }
+
+ Method (ECMD, 3, NotSerialized)
+ {
+ If ((ECOK == One))
+ {
+ WPIO (Arg0, Arg1, Arg2)
+ While (EI03)
+ {
+ Stall (0xFF)
+ }
+
+ Local0 = RPIO (0xFB, Zero)
+ Return (Local0)
+ }
+ }
+
+ Method (CBCD, 0, NotSerialized)
+ {
+ If ((ECOK == One))
+ {
+ Local0 = MBDC /* \_SB_.PCI0.LPCB.EC0_.MBDC */
+ Local0 &= 0xE4
+ MBDC = Local0
+ }
+ }
+
+ Method (ULID, 1, NotSerialized)
+ {
+ If ((ECOK == One))
+ {
+ If ((ECLS == One))
+ {
+ Local0 = Zero
+ }
+ Else
+ {
+ Local0 = One
+ }
+
+ If (IGDS)
+ {
+ If ((Arg0 == One))
+ {
+ If ((Local0 != LIDS))
+ {
+ If (^^^GFX0.GLID (Local0))
+ {
+ If ((LIDS == Zero))
+ {
+ ^^^GFX0.CLID |= 0x80000000 /* External reference */
+ }
+
+ If ((LIDS == One))
+ {
+ ^^^GFX0.CLID |= 0x80000001 /* External reference */
+ }
+ }
+ }
+ }
+ }
+
+ LIDS = Local0
+ }
+ }
+
+ Method (OSTD, 0, NotSerialized)
+ {
+ If ((ECOK == One))
+ {
+ W7OS = Zero
+ SUSE = Zero
+ RFLG = Zero
+ If ((OSYS >= 0x07D0))
+ {
+ If ((OSYS >= 0x07D9))
+ {
+ W7OS = One
+ If ((OSKU == Zero))
+ {
+ W7OS = Zero
+ }
+ }
+ }
+ Else
+ {
+ If ((OSYS == 0x03E8))
+ {
+ RFLG = One
+ }
+
+ If ((OSYS == 0x03E9))
+ {
+ SUSE = One
+ }
+ }
+ }
+ Else
+ {
+ W7OS = Zero
+ SUSE = Zero
+ RFLG = Zero
+ }
+ }
+
+
+#include "ac.asl"
+#include "battery.asl"
+#include "kb.asl"
+#include "tpm.asl"
+}
diff --git a/src/ec/hp/it8987e/acpi/kb.asl b/src/ec/hp/it8987e/acpi/kb.asl
new file mode 100644
index 0000000..bc42897
--- /dev/null
+++ b/src/ec/hp/it8987e/acpi/kb.asl
@@ -0,0 +1,154 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Matt Parnell <mparnell(a)gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+// Scope is \_SB.PCI0.LPCB
+
+Device (PS2K)
+{
+ Name (_CID, EisaId ("PNP0303") /* IBM Enhanced Keyboard (101/102-key, PS/2 Mouse) */) // _CID: Compatible ID
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (0x0F)
+ }
+
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0060, // Range Minimum
+ 0x0060, // Range Maximum
+ 0x01, // Alignment
+ 0x01, // Length
+ )
+ IO (Decode16,
+ 0x0064, // Range Minimum
+ 0x0064, // Range Maximum
+ 0x01, // Alignment
+ 0x01, // Length
+ )
+ IRQ (Edge, ActiveHigh, Exclusive, )
+ {1}
+ })
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ StartDependentFn (0x00, 0x00)
+ {
+ FixedIO (
+ 0x0060, // Address
+ 0x01, // Length
+ )
+ FixedIO (
+ 0x0064, // Address
+ 0x01, // Length
+ )
+ IRQNoFlags ()
+ {1}
+ }
+ EndDependentFn ()
+ })
+
+ Method (_PRW, 0, NotSerialized) // _PRW: Power Resources for Wake
+ {
+ If (One)
+ {
+ Return (Package (0x02)
+ {
+ 0x3D,
+ 0x03
+ })
+ }
+ Else
+ {
+ Return (Package (0x02)
+ {
+ 0x1F,
+ 0x03
+ })
+ }
+ }
+
+ Method (_PSW, 1, NotSerialized) // _PSW: Power State Wake
+ {
+ KBWK = Arg0
+ }
+}
+
+Device (PS2M)
+{
+ Method (_HID, 0, NotSerialized) // _HID: Hardware ID
+ {
+ If ((CHID == 0x25))
+ {
+ Return ("*SYN326A")
+ }
+ Else
+ {
+ Return ("*SYN326A")
+ }
+ }
+
+ Method (_CID, 0, NotSerialized) // _CID: Compatible ID
+ {
+ Return (Package (0x03)
+ {
+ 0x001E2E4F,
+ 0x02002E4F,
+ 0x130FD041
+ })
+ }
+
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (0x0F)
+ }
+
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IRQ (Edge, ActiveHigh, Exclusive, )
+ {12}
+ })
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ StartDependentFn (0x00, 0x00)
+ {
+ IRQNoFlags ()
+ {12}
+ }
+ EndDependentFn ()
+ })
+ Method (_PRW, 0, NotSerialized) // _PRW: Power Resources for Wake
+ {
+ If (One)
+ {
+ Return (Package (0x02)
+ {
+ 0x3D,
+ 0x03
+ })
+ }
+ Else
+ {
+ Return (Package (0x02)
+ {
+ 0x1F,
+ 0x03
+ })
+ }
+ }
+
+ Method (_PSW, 1, NotSerialized) // _PSW: Power State Wake
+ {
+ TPWK = Arg0
+ }
+}
diff --git a/src/ec/hp/it8987e/acpi/superio.asl b/src/ec/hp/it8987e/acpi/superio.asl
new file mode 100644
index 0000000..e912e04
--- /dev/null
+++ b/src/ec/hp/it8987e/acpi/superio.asl
@@ -0,0 +1,87 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+// Scope is \_SB.PCI0.LPCB
+
+Device (SIO)
+{
+ Name (_HID, EisaId("PNP0A05"))
+ Name (_UID, 0)
+ Name (_ADR, 0)
+
+#ifdef SIO_EC_ENABLE_PS2K
+ Device (PS2K) // Keyboard
+ {
+ Name (_UID, 0)
+ Name (_ADR, 0)
+ Name (_HID, EISAID("PNP0303"))
+ Name (_CID, EISAID("PNP030B"))
+
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0F)
+ }
+
+ Name (_CRS, ResourceTemplate()
+ {
+ FixedIO (0x60, 0x01)
+ FixedIO (0x64, 0x01)
+ IRQNoFlags () {1}
+ })
+
+ Name (_PRS, ResourceTemplate()
+ {
+ StartDependentFn (0, 0)
+ {
+ FixedIO (0x60, 0x01)
+ FixedIO (0x64, 0x01)
+ IRQNoFlags () {1}
+ }
+ EndDependentFn ()
+ })
+ }
+#endif
+
+#ifdef SIO_ENABLE_PS2M
+ Device (PS2M) // Mouse
+ {
+ Name (_HID, EISAID("PNP0F13"))
+
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0F)
+ }
+
+ Name (_CRS, ResourceTemplate()
+ {
+ FixedIO (0x60, 0x01)
+ FixedIO (0x64, 0x01)
+ IRQNoFlags () {12}
+ })
+
+ Name (_PRS, ResourceTemplate()
+ {
+ StartDependentFn (0, 0)
+ {
+ FixedIO (0x60, 0x01)
+ FixedIO (0x64, 0x01)
+ IRQNoFlags () {12}
+ }
+ EndDependentFn ()
+ })
+ }
+#endif
+
+}
diff --git a/src/ec/hp/it8987e/acpi/tpm.asl b/src/ec/hp/it8987e/acpi/tpm.asl
new file mode 100644
index 0000000..d24d05f
--- /dev/null
+++ b/src/ec/hp/it8987e/acpi/tpm.asl
@@ -0,0 +1,446 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Matt Parnell <mparnell(a)gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Device (_SB.TPM)
+{
+ Method (_HID, 0, NotSerialized) // _HID: Hardware ID
+ {
+ If (TCMF)
+ {
+ Return (0x01013469)
+ }
+ ElseIf ((TTDP == Zero))
+ {
+ Return (0x310CD041)
+ }
+ Else
+ {
+ Return ("MSFT0101")
+ }
+ }
+
+ Method (_STR, 0, NotSerialized) // _STR: Description String
+ {
+ If ((TTDP == Zero))
+ {
+ Return (Unicode ("TPM 1.2 Device"))
+ }
+ Else
+ {
+ Return (Unicode ("TPM 2.0 Device"))
+ }
+ }
+
+ Name (_UID, One) // _UID: Unique ID
+ Name (CRST, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadOnly,
+ 0x00000000, // Address Base
+ 0x00001000, // Address Length
+ _Y31)
+ Memory32Fixed (ReadOnly,
+ 0xFED70000, // Address Base
+ 0x00001000, // Address Length
+ _Y32)
+ })
+ Name (CRSD, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite,
+ 0xFED40000, // Address Base
+ 0x00005000, // Address Length
+ _Y33)
+ })
+ Name (CRSI, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite,
+ 0xFED40000, // Address Base
+ 0x00005000, // Address Length
+ _Y34)
+ })
+ Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings
+ {
+ If ((AMDT == One))
+ {
+ CreateDWordField (CRST, \_SB.TPM._Y31._BAS, MTFB) // _BAS: Base Address
+ CreateDWordField (CRST, \_SB.TPM._Y31._LEN, LTFB) // _LEN: Length
+ MTFB = TPMB /* \TPMB */
+ LTFB = 0x1000
+ CreateDWordField (CRST, \_SB.TPM._Y32._BAS, MTFC) // _BAS: Base Address
+ CreateDWordField (CRST, \_SB.TPM._Y32._LEN, LTFC) // _LEN: Length
+ MTFC = TPMC /* \TPMC */
+ LTFC = 0x1000
+ Return (CRST) /* \_SB_.TPM_.CRST */
+ }
+ Else
+ {
+ If ((DTPT == One))
+ {
+ CreateDWordField (CRSD, \_SB.TPM._Y33._BAS, MTFE) // _BAS: Base Address
+ CreateDWordField (CRSD, \_SB.TPM._Y33._LEN, LTFE) // _LEN: Length
+ MTFE = 0xFED40000
+ LTFE = 0x0880
+ Return (CRSD) /* \_SB_.TPM_.CRSD */
+ }
+ ElseIf ((TTPF == One))
+ {
+ CreateDWordField (CRSI, \_SB.TPM._Y34._BAS, MTFD) // _BAS: Base Address
+ CreateDWordField (CRSI, \_SB.TPM._Y34._LEN, LTFD) // _LEN: Length
+ MTFD = 0xFED40000
+ LTFD = 0x5000
+ Return (CRSI) /* \_SB_.TPM_.CRSI */
+ }
+ ElseIf ((TTPF == Zero))
+ {
+ CreateDWordField (CRSI, \_SB.TPM._Y34._BAS, MTFF) // _BAS: Base Address
+ MTFF = TPMM /* \TPMM */
+ Return (CRSI) /* \_SB_.TPM_.CRSI */
+ }
+
+ MTFE = Zero
+ LTFE = Zero
+ Return (CRSI) /* \_SB_.TPM_.CRSI */
+ }
+
+ Return (CRSI) /* \_SB_.TPM_.CRSI */
+ }
+
+ OperationRegion (TMMB, SystemMemory, 0xFED40000, 0x5000)
+ Field (TMMB, ByteAcc, Lock, Preserve)
+ {
+ Offset (0x04),
+ LCST, 32,
+ Offset (0x40),
+ CREQ, 32,
+ CSTS, 32,
+ Offset (0x4C),
+ SCMD, 32
+ }
+
+ OperationRegion (CRBD, SystemMemory, TPMM, 0x48)
+ Field (CRBD, AnyAcc, NoLock, Preserve)
+ {
+ Offset (0x04),
+ HERR, 32,
+ Offset (0x40),
+ HCMD, 32,
+ HSTS, 32
+ }
+
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ If ((TTDP == Zero))
+ {
+ If (TPMF)
+ {
+ Return (0x0F)
+ }
+
+ Return (Zero)
+ }
+ ElseIf ((TTDP == One))
+ {
+ If (TPMF)
+ {
+ Return (0x0F)
+ }
+
+ Return (Zero)
+ }
+
+ Return (Zero)
+ }
+
+ Method (STRT, 3, Serialized)
+ {
+ OperationRegion (TPMR, SystemMemory, FTPM, 0x1000)
+ Field (TPMR, AnyAcc, NoLock, Preserve)
+ {
+ Offset (0x04),
+ FERR, 32,
+ Offset (0x0C),
+ BEGN, 32
+ }
+
+ Name (TIMR, Zero)
+ If ((ToInteger (Arg0) != Zero)){}
+ Switch (ToInteger (Arg1))
+ {
+ Case (Zero)
+ {
+ Return (Buffer (One)
+ {
+ 0x03 // .
+ })
+ }
+ Case (One)
+ {
+ TIMR = Zero
+ If ((AMDT == One))
+ {
+ While (((BEGN == One) && (TIMR < 0x0200)))
+ {
+ If ((BEGN == One))
+ {
+ Sleep (One)
+ TIMR++
+ }
+ }
+ }
+ ElseIf ((((HSTS & 0x02) | (HSTS & One)
+ ) == 0x03))
+ {
+ HCMD = One
+ }
+ Else
+ {
+ FERR = One
+ BEGN = Zero
+ }
+
+ Return (Zero)
+ }
+
+ }
+
+ Return (One)
+ }
+
+ Method (CRYF, 3, Serialized)
+ {
+ If ((ToInteger (Arg0) != One)){}
+ Switch (ToInteger (Arg1))
+ {
+ Case (Zero)
+ {
+ Return (Buffer (One)
+ {
+ 0x03 // .
+ })
+ }
+ Case (One)
+ {
+ Name (TPMV, Package (0x02)
+ {
+ One,
+ Package (0x02)
+ {
+ One,
+ 0x20
+ }
+ })
+ If ((_STA () == Zero))
+ {
+ Return (Package (0x01)
+ {
+ Zero
+ })
+ }
+
+ Return (TPMV) /* \_SB_.TPM_.CRYF.TPMV */
+ }
+
+ }
+
+ Return (Buffer (One)
+ {
+ 0x00 // .
+ })
+ }
+}
+
+
+
+Scope (_SB.TPM)
+{
+ OperationRegion (TSMI, SystemIO, SMIA, 0x02)
+ Field (TSMI, WordAcc, NoLock, Preserve)
+ {
+ SMI, 16
+ }
+
+ OperationRegion (ATNV, SystemMemory, PPIM, PPIL)
+ Field (ATNV, AnyAcc, NoLock, Preserve)
+ {
+ RQST, 32,
+ RCNT, 32,
+ ERRO, 32,
+ FLAG, 32,
+ MISC, 32,
+ OPTN, 32,
+ SRSP, 32
+ }
+
+ Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method
+ {
+ If ((Arg0 == ToUUID ("3dddfaa6-361b-4eb4-a424-8d10089d1653") /* Physical Presence Interface */))
+ {
+ Switch (ToInteger (Arg2))
+ {
+ Case (Zero)
+ {
+ Return (Buffer (0x02)
+ {
+ 0xFF, 0x01 // ..
+ })
+ }
+ Case (One)
+ {
+ If ((PPIV == Zero))
+ {
+ Return ("1.2")
+ }
+ Else
+ {
+ Return ("1.3")
+ }
+ }
+ Case (0x02)
+ {
+ RQST = DerefOf (Arg3 [Zero])
+ SRSP = Zero
+ FLAG = 0x02
+ TMF1 = OFST /* \OFST */
+ SRSP = Zero
+ SMI = TMF1 /* \TMF1 */
+ Return (SRSP) /* \_SB_.TPM_.SRSP */
+ }
+ Case (0x03)
+ {
+ Name (PPI1, Package (0x02)
+ {
+ Zero,
+ Zero
+ })
+ PPI1 [One] = RQST /* \_SB_.TPM_.RQST */
+ Return (PPI1) /* \_SB_.TPM_._DSM.PPI1 */
+ }
+ Case (0x04)
+ {
+ Return (TRST) /* \TRST */
+ }
+ Case (0x05)
+ {
+ Name (PPI2, Package (0x03)
+ {
+ Zero,
+ Zero,
+ Zero
+ })
+ SRSP = Zero
+ FLAG = 0x05
+ SMI = OFST /* \OFST */
+ PPI2 [One] = RCNT /* \_SB_.TPM_.RCNT */
+ PPI2 [0x02] = ERRO /* \_SB_.TPM_.ERRO */
+ Return (PPI2) /* \_SB_.TPM_._DSM.PPI2 */
+ }
+ Case (0x06)
+ {
+ Return (0x03)
+ }
+ Case (0x07)
+ {
+ RQST = DerefOf (Arg3 [Zero])
+ FLAG = 0x07
+ OPTN = Zero
+ If ((RQST == 0x17))
+ {
+ ToInteger (DerefOf (Arg3 [One]), OPTN) /* \_SB_.TPM_.OPTN */
+ }
+
+ TMF1 = OFST /* \OFST */
+ SRSP = Zero
+ SMI = TMF1 /* \TMF1 */
+ Return (SRSP) /* \_SB_.TPM_.SRSP */
+ }
+ Case (0x08)
+ {
+ RQST = DerefOf (Arg3 [Zero])
+ FLAG = 0x08
+ TMF1 = OFST /* \OFST */
+ SRSP = Zero
+ SMI = TMF1 /* \TMF1 */
+ Return (SRSP) /* \_SB_.TPM_.SRSP */
+ }
+ Default
+ {
+ }
+
+ }
+ }
+ ElseIf ((Arg0 == ToUUID ("376054ed-cc13-4675-901c-4756d7f2d45d")))
+ {
+ Switch (ToInteger (Arg2))
+ {
+ Case (Zero)
+ {
+ Return (Buffer (One)
+ {
+ 0x03 // .
+ })
+ }
+ Case (One)
+ {
+ RQST = DerefOf (Arg3 [Zero])
+ FLAG = 0x09
+ TMF1 = OFST /* \OFST */
+ SRSP = Zero
+ SMI = TMF1 /* \TMF1 */
+ Return (SRSP) /* \_SB_.TPM_.SRSP */
+ }
+ Default
+ {
+ }
+
+ }
+ }
+
+ If ((Arg0 == ToUUID ("cf8e16a5-c1e8-4e25-b712-4f54a96702c8")))
+ {
+ Return (CRYF (Arg1, Arg2, Arg3))
+ }
+
+ If ((Arg0 == ToUUID ("6bbf6cab-5463-4714-b7cd-f0203c0368d4")))
+ {
+ Return (STRT (Arg1, Arg2, Arg3))
+ }
+
+ Return (Buffer (One)
+ {
+ 0x00 // .
+ })
+ }
+
+ Method (TPTS, 1, Serialized)
+ {
+ Switch (ToInteger (Arg0))
+ {
+ Case (0x04)
+ {
+ RQST = Zero
+ FLAG = 0x09
+ SRSP = Zero
+ SMI = OFST /* \OFST */
+ }
+ Case (0x05)
+ {
+ RQST = Zero
+ FLAG = 0x09
+ SRSP = Zero
+ SMI = OFST /* \OFST */
+ }
+
+ }
+ }
+}
diff --git a/src/ec/hp/it8987e/chip.h b/src/ec/hp/it8987e/chip.h
new file mode 100644
index 0000000..1bc9949
--- /dev/null
+++ b/src/ec/hp/it8987e/chip.h
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _EC_HP_IT8987E_CHIP_H
+#define _EC_HP_IT8987E_CHIP_H
+
+#include <device/device.h>
+
+struct chip_operations;
+extern struct chip_operations ec_quanta_it8987e_ops;
+
+struct ec_quanta_it8987e_config {
+};
+
+#endif /* _EC_HP_IT8987E_CHIP_H */
diff --git a/src/ec/hp/it8987e/ec.c b/src/ec/hp/it8987e/ec.c
new file mode 100644
index 0000000..db6fe3c
--- /dev/null
+++ b/src/ec/hp/it8987e/ec.c
@@ -0,0 +1,182 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <delay.h>
+#include <device/device.h>
+#include <device/pnp.h>
+#include <pc80/keyboard.h>
+
+#include "ec.h"
+#include "chip.h"
+
+/* helper functions from drivers/pc80/keyboard.c */
+static int input_buffer_empty(u16 status_reg)
+{
+ u32 timeout;
+ for (timeout = KBC_TIMEOUT_IN_MS; timeout && (inb(status_reg) & KBD_IBF);
+ timeout--) {
+ udelay(1000);
+ }
+
+ if (!timeout) {
+ printk(BIOS_WARNING, "EC-IT8987E Unexpected input buffer full\n");
+ printk(BIOS_WARNING, " Status (0x%x): 0x%x\n", status_reg, inb(status_reg));
+ }
+ return !!timeout;
+}
+
+
+static int output_buffer_full(u16 status_reg)
+{
+ u32 timeout;
+ for (timeout = KBC_TIMEOUT_IN_MS; timeout && ((inb(status_reg)
+ & KBD_OBF) == 0); timeout--) {
+ udelay(1000);
+ }
+
+ if (!timeout) {
+ printk(BIOS_INFO, "EC-IT8987E output buffer result timeout\n");
+ printk(BIOS_INFO, " Status (0x%x): 0x%x\n", status_reg, inb(status_reg));
+ }
+ return !!timeout;
+}
+
+
+
+/* The IT8987E 60/64 EC registers are the same command/status IB/OB KBC pair.
+ * Check status from 64 port before each command.
+ *
+ * Ex. Get panel ID command C43/D77
+ * Check IBF empty. Then Write 0x43(CMD) to 0x64 Port
+ * Check IBF empty. Then Write 0x77(DATA) to 0x60 Port
+ * Check OBF set. Then Get Data(0x03:panel ID) from 0x60
+ * Different commands return may or may not respond and may have multiple
+ * bytes. Keep it simple for nor
+ */
+
+u8 ec_kbc_read_ob(void)
+{
+ if (!output_buffer_full(KBD_STATUS)) return 0;
+ return inb(KBD_DATA);
+}
+
+void ec_kbc_write_cmd(u8 cmd)
+{
+ if (!input_buffer_empty(KBD_STATUS)) return;
+ outb(cmd, KBD_COMMAND);
+}
+
+void ec_kbc_write_ib(u8 data)
+{
+ if (!input_buffer_empty(KBD_STATUS)) return;
+ outb(data, KBD_DATA);
+}
+
+
+/*
+ * These functions are for accessing the IT8987E device RAM space via 0x66/0x68
+ */
+
+u8 ec_read_ob(void)
+{
+ if (!output_buffer_full(EC_SC)) return 0;
+ return inb(EC_DATA);
+}
+
+void ec_write_cmd(u8 cmd)
+{
+ if (!input_buffer_empty(EC_SC)) return;
+ outb(cmd, EC_SC);
+}
+
+void ec_write_ib(u8 data)
+{
+ if (!input_buffer_empty(EC_SC)) return;
+ outb(data, EC_DATA);
+}
+
+u8 ec_read(u16 addr)
+{
+ ec_write_cmd(RD_EC);
+ ec_write_ib(addr);
+ return ec_read_ob();
+}
+
+void ec_write(u16 addr, u8 data)
+{
+ ec_write_cmd(WR_EC);
+ ec_write_ib(addr);
+ ec_write_ib(data);
+}
+
+#ifndef __PRE_RAM__
+
+u8 ec_it8987e_get_event(void)
+{
+ u8 cmd = 0;
+ u8 status = inb(EC_SC);
+ if (status & SCI_EVT) {
+ ec_write_cmd(QR_EC);
+ cmd = ec_read_ob();
+ } else if (status & SMI_EVT) {
+ ec_kbc_write_cmd(EC_KBD_SMI_EVENT);
+ cmd = ec_kbc_read_ob();
+ }
+ return cmd;
+}
+
+void ec_it8987e_enable_wake_events(void)
+{
+ /*
+ * Set the bit in ECRAM that will enable the Lid switch as a wake source
+ */
+ u8 reg8 = ec_read(EC_WAKE_SRC_ENABLE);
+ ec_write(EC_WAKE_SRC_ENABLE, reg8 | EC_LID_WAKE_ENABLE);
+}
+
+#ifndef __SMM__
+static void it8987e_init(struct device *dev)
+{
+ if (!dev->enabled)
+ return;
+
+ printk(BIOS_DEBUG, "Quanta IT8987E: Initializing keyboard.\n");
+ pc_keyboard_init(NO_AUX_DEVICE);
+}
+
+static struct device_operations ops = {
+ .init = it8987e_init,
+ .read_resources = DEVICE_NOOP,
+ .enable_resources = DEVICE_NOOP,
+};
+
+static struct pnp_info pnp_dev_info[] = {
+ { NULL, 0, 0, 0, }
+};
+
+static void enable_dev(struct device *dev)
+{
+ pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
+}
+
+struct chip_operations ec_quanta_it8987e_ops = {
+ CHIP_NAME("QUANTA IT8987E EC")
+ .enable_dev = enable_dev
+};
+#endif /* ! __SMM__ */
+#endif /* ! __PRE_RAM__ */
diff --git a/src/ec/hp/it8987e/ec.h b/src/ec/hp/it8987e/ec.h
new file mode 100644
index 0000000..f87b2c0
--- /dev/null
+++ b/src/ec/hp/it8987e/ec.h
@@ -0,0 +1,94 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Modified by Matt Parnell <mparnell(a)gmail.com> to support ITL 8987E
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * EC communication interface for QUANTA IT8987E Embedded Controller.
+ */
+
+#ifndef _EC_HP_IT8987E_EC_H
+#define _EC_HP_IT8987E_EC_H
+
+#define EC_IO 0x100 /* Mainboard specific. Could be Kconfig option */
+#define EC_IO_HIGH EC_IO + 1
+#define EC_IO_LOW EC_IO + 2
+#define EC_IO_DATA EC_IO + 3
+
+/* Wait 400ms for keyboard controller ansswers */
+#define KBC_TIMEOUT_IN_MS 400
+
+// 60h/64h Command Interface
+#define KBD_DATA 0x60
+#define KBD_COMMAND 0x64
+#define KBD_STATUS 0x64
+#define KBD_IBF (1 << 1) // 1: input buffer full (data ready for ec)
+#define KBD_OBF (1 << 0) // 1: output buffer full (data ready for host)
+
+#define EC_KBD_SMI_EVENT 0xCD
+#define EC_KBD_CMD_UNMUTE 0xE8
+#define EC_KBD_CMD_MUTE 0xE9
+
+u8 ec_kbc_read_ob(void);
+void ec_kbc_write_cmd(u8 cmd);
+void ec_kbc_write_ib(u8 data);
+
+// 62h/66h Command Interface
+#define EC_DATA 0x62
+#define EC_SC 0x66 // Status & Control Register
+#define SMI_EVT (1 << 6) // 1: SMI event was triggered
+#define SCI_EVT (1 << 5) // 1: SCI event was triggered
+
+// EC Commands (defined in ec_function_spec v3.12)
+#define RD_EC 0x80
+#define WR_EC 0x81
+#define QR_EC 0x84
+
+#define EC_CMD_EXIT_BOOT_BLOCK 0x85
+#define EC_CMD_NOTIFY_ACPI_ENTER 0x86
+#define EC_CMD_NOTIFY_ACPI_EXIT 0x87
+#define EC_CMD_WARM_RESET 0x8C
+
+// ECRAM Offsets
+#define EC_PERIPH_CNTL_3 0x0D
+#define EC_USB_S3_EN 0x26
+#define EC_PERIPH_STAT_3 0x35
+#define EC_THERM_0 0x78
+#define EC_WAKE_SRC_ENABLE 0xBF
+#define EC_FW_VER 0xE8 // 2 Bytes
+#define EC_IF_MIN_VER 0xEB
+#define EC_STATUS_REG 0xEC
+#define EC_IF_MAJ_VER 0xEF
+#define EC_MBAT_STATUS 0x0138
+
+
+// EC 0.83b added status bits:
+// BIT0=EC in RO mode
+// BIT1=Recovery Key Sequence Detected
+#define EC_IN_RO_MODE 0x1
+#define EC_IN_RECOVERY_MODE 0x3
+
+// EC 0.86a added enable bit:
+#define EC_LID_WAKE_ENABLE 0x4
+
+u8 ec_read_ob(void);
+void ec_write_cmd(u8 cmd);
+void ec_write_ib(u8 data);
+
+u8 ec_read(u16 addr);
+void ec_write(u16 addr, u8 data);
+u8 ec_it8987e_get_event(void);
+void ec_it8987e_enable_wake_events(void);
+
+#endif /* _EC_HP_IT8987E_EC_H */
diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/Kconfig b/src/mainboard/hp/spectre_x360_13t_ae000/Kconfig
new file mode 100644
index 0000000..00542d7
--- /dev/null
+++ b/src/mainboard/hp/spectre_x360_13t_ae000/Kconfig
@@ -0,0 +1,59 @@
+config BOARD_HP_SPECTRE_AE000
+ select SYSTEM_TYPE_LAPTOP
+ select BOARD_ROMSIZE_KB_8192
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select INTEL_LPSS_UART_FOR_CONSOLE
+ select SOC_INTEL_KABYLAKE
+ select MAINBOARD_USES_FSP2_0
+ select SPD_READ_BY_WORD
+ select MAINBOARD_HAS_LPC_TPM
+ select NO_POST # This platform does not have any way to see POST codes
+
+if BOARD_HP_SPECTRE_AE000
+
+config IRQ_SLOT_COUNT
+ int
+ default 18
+
+config MAINBOARD_VENDOR
+ string
+ default "HP"
+
+config MAINBOARD_FAMILY
+ string
+ default "HP Spectre x360"
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "13t-ae000"
+
+config MAINBOARD_DIR
+ string
+ default "hp/hp_spectre_x360_13_convertible"
+
+config DEVICETREE
+ string
+ default "devicetree.cb"
+
+config FMDFILE
+ string
+ default ""
+
+config MAX_CPUS
+ int
+ default 8
+
+config VGA_BIOS_ID
+ string
+ default "8086,0406"
+
+config DIMM_MAX
+ int
+ default 2
+
+config DIMM_SPD_SIZE
+ int
+ default 512
+
+endif
diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/Kconfig.name b/src/mainboard/hp/spectre_x360_13t_ae000/Kconfig.name
new file mode 100644
index 0000000..9f089a5
--- /dev/null
+++ b/src/mainboard/hp/spectre_x360_13t_ae000/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_HP_SPECTRE_AE000
+ bool "Spectre x360 13t-ae000"
diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/Makefile.inc b/src/mainboard/hp/spectre_x360_13t_ae000/Makefile.inc
new file mode 100644
index 0000000..35f0f6c
--- /dev/null
+++ b/src/mainboard/hp/spectre_x360_13t_ae000/Makefile.inc
@@ -0,0 +1,17 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2015 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+ramstage-y += ramstage.c
+ramstage-y += hda_verb.c
diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/acpi/ac.asl b/src/mainboard/hp/spectre_x360_13t_ae000/acpi/ac.asl
new file mode 100644
index 0000000..489bdcd
--- /dev/null
+++ b/src/mainboard/hp/spectre_x360_13t_ae000/acpi/ac.asl
@@ -0,0 +1,80 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+// Scope (EC0)
+
+Device (ADP1)
+{
+ Name (_HID, "ACPI0003" /* Power Source Device */) // _HID: Hardware ID
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (0x0F)
+ }
+
+ Method (_PSR, 0, NotSerialized) // _PSR: Power Source
+ {
+ If ((\_SB_.PCI0.LPCB.EC0.ECOK == 1))
+ {
+ Local0 = \_SB_.PCI0.LPCB.EC0.SW2S
+ }
+ Else
+ {
+ Local0 = 1
+ }
+
+ Return (Local0)
+ }
+
+ Method (_PCL, 0, NotSerialized) // _PCL: Power Consumer List
+ {
+ Return (_SB) /* \_SB_ */
+ }
+}
+
+Device (LID0)
+{
+ Name (_HID, EisaId ("PNP0C0D") /* Lid Device */) // _HID: Hardware ID
+ Method (_LID, 0, NotSerialized) // _LID: Lid Status
+ {
+ If ((\_SB_.PCI0.LPCB.EC0.ECOK == 1))
+ {
+ If ((\_SB_.PCI0.LPCB.EC0.ECLS == 1))
+ {
+ Local0 = 0
+ }
+ Else
+ {
+ Local0 = 1
+ }
+ }
+ Else
+ {
+ Local0 = 1
+ }
+
+ /* \_SB_.PCI0.LPCB.EC0.ULID (1) */
+ Return (Local0)
+ }
+}
+
+Device (PWRB)
+{
+ Name (_HID, EisaId ("PNP0C0C") /* Power Button Device */) // _HID: Hardware ID
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (0x0F)
+ }
+}
diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/acpi/battery.asl b/src/mainboard/hp/spectre_x360_13t_ae000/acpi/battery.asl
new file mode 100644
index 0000000..94ce92c
--- /dev/null
+++ b/src/mainboard/hp/spectre_x360_13t_ae000/acpi/battery.asl
@@ -0,0 +1,252 @@
+/*
+* This file is part of the coreboot project.
+*
+* Copyright (C) 2013 Google Inc.
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as
+* published by the Free Software Foundation; version 2 of
+* the License.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*/
+
+Device (BAT0)
+{
+ Name (FRST, 1)
+ Name (_HID, EisaId ("PNP0C0A") /* Control Method Battery */) // _HID: Hardware ID
+ Name (_UID, 1) // _UID: Unique ID
+ Name (_PCL, Package (0x01) // _PCL: Power Consumer List
+ {
+ _SB
+ })
+ Name (PBIF, Package (0x0D)
+ {
+ 1,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 1,
+ 0xFFFFFFFF,
+ 0xFA,
+ 0x96,
+ 0x0A,
+ 0x19,
+ "BAT0",
+ " ",
+ " ",
+ " "
+ })
+ Name (PBST, Package (0x04)
+ {
+ 0,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0x2710
+ })
+ Name (BAST, 0)
+ Name (B1ST, 0x0F)
+ Name (B1WT, 0)
+ Name (FABL, 0xFFFFFFFF)
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ If ((\_SB_.PCI0.LPCB.EC0.ECOK == 1))
+ {
+ If (\_SB_.PCI0.LPCB.EC0.MBTS)
+ {
+ B1ST = 0x1F
+ }
+ Else
+ {
+ B1ST = 0x0F
+ }
+ }
+ Else
+ {
+ B1ST = 0x0F
+ }
+
+ Return (B1ST) /* \_SB_.BAT0.B1ST */
+ }
+
+ Method (_BIF, 0, NotSerialized) // _BIF: Battery Information
+ {
+ If ((\_SB_.PCI0.LPCB.EC0.ECOK == 1))
+ {
+ If (\_SB_.PCI0.LPCB.EC0.MBTS)
+ {
+ UPBI ()
+ }
+ Else
+ {
+ IVBI ()
+ }
+ }
+ Else
+ {
+ IVBI ()
+ }
+
+ Return (PBIF) /* \_SB_.BAT0.PBIF */
+ }
+
+ Method (_BST, 0, NotSerialized) // _BST: Battery Status
+ {
+ If ((\_SB_.PCI0.LPCB.EC0.ECOK == 1))
+ {
+ If (\_SB_.PCI0.LPCB.EC0.MBTS)
+ {
+ UPBS ()
+ }
+ Else
+ {
+ IVBS ()
+ }
+ }
+ Else
+ {
+ IVBS ()
+ }
+
+ Return (PBST) /* \_SB_.BAT0.PBST */
+ }
+
+ Method (UPBI, 0, NotSerialized)
+ {
+ Local5 = \_SB_.PCI0.LPCB.EC0.BFCC /* \_SB_.PCI0.LPCB.EC0_.BFCC */
+ If ((Local5 && !(Local5 & 0x8000)))
+ {
+ Local5 >>= 0x05
+ Local5 <<= 0x05
+ PBIF [1] = Local5
+ PBIF [0x02] = Local5
+ Local2 = (Local5 / 0x64)
+ Local2 += 1
+ If ((\_SB_.PCI0.LPCB.EC0.BADC < 0x0C80))
+ {
+ Local4 = (Local2 * 0x0E)
+ PBIF [0x05] = (Local4 + 0x02)
+ Local4 = (Local2 * 0x09)
+ PBIF [0x06] = (Local4 + 0x02)
+ Local4 = (Local2 * 0x0B)
+ }
+ ElseIf ((SMA4 == 1))
+ {
+ Local4 = (Local2 * 0x0A)
+ PBIF [0x05] = (Local4 + 0x02)
+ Local4 = (Local2 * 0x05)
+ PBIF [0x06] = (Local4 + 0x02)
+ Local4 = (Local2 * 0x08)
+ }
+ Else
+ {
+ Local4 = (Local2 * 0x0C)
+ PBIF [0x05] = (Local4 + 0x02)
+ Local4 = (Local2 * 0x07)
+ PBIF [0x06] = (Local4 + 0x02)
+ Local4 = (Local2 * 0x0A)
+ }
+
+ FABL = (Local4 + 0x02)
+ }
+
+ Local0 = \_SB_.PCI0.LPCB.EC0.BVLB /* \_SB_.PCI0.LPCB.EC0_.BVLB */
+ Local1 = \_SB_.PCI0.LPCB.EC0.BVHB /* \_SB_.PCI0.LPCB.EC0_.BVHB */
+ Local1 <<= 0x08
+ Local0 |= Local1
+ PBIF [0x04] = Local0
+ Sleep (0x32)
+ PBIF [0x0B] = "LION"
+ PBIF [0x09] = "Primary"
+ UPUM ()
+ PBIF [0] = 1
+ }
+
+ Method (UPUM, 0, NotSerialized)
+ {
+ Local0 = Buffer (0x0A)
+ {
+ /* 0000 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........
+ /* 0008 */ 0x00, 0x00 // ..
+ }
+ Local6 = Buffer (0x05)
+ {
+ 0x36, 0x35, 0x35, 0x33, 0x35 // 65535
+ }
+ Local7 = Buffer (0x05)
+ {
+ 0x31, 0x32, 0x33, 0x32, 0x31 // 12321
+ }
+ PBIF [0x0C] = "HP"
+ }
+
+ Method (UPBS, 0, NotSerialized)
+ {
+ If ((BRTM == 1))
+ {
+ Local0 = \_SB_.PCI0.LPCB.EC0.MCUR /* \_SB_.PCI0.LPCB.EC0_.MCUR */
+ If ((Local0 & 0x8000))
+ {
+ If ((Local0 == 0xFFFF))
+ {
+ PBST [1] = 0xFFFFFFFF
+ }
+ Else
+ {
+ Local1 = ~Local0
+ Local1++
+ Local3 = (Local1 & 0xFFFF)
+ PBST [1] = Local3
+ }
+ }
+ Else
+ {
+ PBST [1] = Local0
+ }
+ }
+ Else
+ {
+ PBST [1] = 0xFFFFFFFF
+ }
+
+ Local5 = \_SB_.PCI0.LPCB.EC0.MBRM /* \_SB_.PCI0.LPCB.EC0_.MBRM */
+ If (!(Local5 & 0x8000))
+ {
+ Local5 >>= 0x05
+ Local5 <<= 0x05
+ If ((Local5 != DerefOf (PBST [0x02])))
+ {
+ PBST [0x02] = Local5
+ }
+ }
+
+ If ((!\_SB_.PCI0.LPCB.EC0.SW2S && (\_SB_.PCI0.LPCB.EC0.BACR == 1)))
+ {
+ PBST [0x02] = FABL /* \_SB_.BAT0.FABL */
+ }
+
+ PBST [0x03] = \_SB_.PCI0.LPCB.EC0.MBCV /* \_SB_.PCI0.LPCB.EC0_.MBCV */
+ PBST [0] = \_SB_.PCI0.LPCB.EC0.MBST /* \_SB_.PCI0.LPCB.EC0_.MBST */
+ }
+
+ Method (IVBI, 0, NotSerialized)
+ {
+ PBIF [1] = 0xFFFFFFFF
+ PBIF [0x02] = 0xFFFFFFFF
+ PBIF [0x04] = 0xFFFFFFFF
+ PBIF [0x09] = "Bad"
+ PBIF [0x0A] = "Bad"
+ PBIF [0x0B] = "Bad"
+ PBIF [0x0C] = "Bad"
+ }
+
+ Method (IVBS, 0, NotSerialized)
+ {
+ PBST [0] = 0
+ PBST [1] = 0xFFFFFFFF
+ PBST [0x02] = 0xFFFFFFFF
+ PBST [0x03] = 0x2710
+ }
+}
diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/acpi/ec.asl b/src/mainboard/hp/spectre_x360_13t_ae000/acpi/ec.asl
new file mode 100644
index 0000000..a417560
--- /dev/null
+++ b/src/mainboard/hp/spectre_x360_13t_ae000/acpi/ec.asl
@@ -0,0 +1,393 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Device (EC0)
+{
+ Name (_HID, EisaId ("PNP0C09") /* Embedded Controller Device */) // _HID: Hardware ID
+ Name (_UID, 1) // _UID: Unique ID
+ Name (_GPE, 0x17)
+ Name (PHOT, 1)
+
+ Name (_CRS, ResourceTemplate () {
+ IO (Decode16, 0x62, 0x62, 0, 1)
+ IO (Decode16, 0x66, 0x66, 0, 1)
+ })
+
+ OperationRegion (ERAM, EmbeddedControl, 0, 0xFF)
+ Field (ERAM, ByteAcc, NoLock, Preserve)
+ {
+ SMPR, 8,
+ SMST, 8,
+ SMAD, 8,
+ SMCM, 8,
+ SMD0, 256,
+ BCNT, 8,
+ SMAA, 8,
+ Offset (0x40),
+ SW2S, 1,
+ , 2,
+ ACCC, 1,
+ TRPM, 1,
+ Offset (0x41),
+ W7OS, 1,
+ QWOS, 1,
+ , 1,
+ SUSE, 1,
+ RFLG, 1,
+ Offset (0x43),
+ , 1,
+ , 1,
+ ACPS, 1,
+ ACKY, 1,
+ GFXT, 1,
+ Offset (0x44),
+ , 7,
+ DSMB, 1,
+ Offset (0x47),
+ TNT2, 8,
+ TNT3, 8,
+ Offset (0x4C),
+ STRM, 8,
+ Offset (0x4E),
+ LIDE, 1,
+ Offset (0x4F),
+ ACID, 8,
+ , 2,
+ PTHM, 1,
+ , 1,
+ BSEV, 1,
+ DPTL, 1,
+ Offset (0x52),
+ ECLS, 1,
+ Offset (0x55),
+ EC45, 8,
+ Offset (0x58),
+ RTMP, 8,
+ TNT1, 8,
+ Offset (0x5F),
+ , 1,
+ Offset (0x61),
+ SHPM, 8,
+ Offset (0x67),
+ , 1,
+ , 1,
+ GC6R, 1,
+ IGC6, 1,
+ , 2,
+ PVSE, 1,
+ PVSS, 1,
+ , 3,
+ PLGS, 1,
+ , 3,
+ TPDF, 1,
+ , 4,
+ BCTF, 1,
+ BMNF, 1,
+ BTVD, 1,
+ BF10, 1,
+ Offset (0x6C),
+ GWKR, 8,
+ Offset (0x70),
+ BADC, 16,
+ BFCC, 16,
+ BVLB, 8,
+ BVHB, 8,
+ BDVO, 8,
+ Offset (0x7F),
+ ECTB, 1,
+ Offset (0x82),
+ MBST, 8,
+ MCUR, 16,
+ MBRM, 16,
+ MBCV, 16,
+ Offset (0x8B),
+ LEDM, 3,
+ Offset (0x8D),
+ , 5,
+ MBFC, 1,
+ Offset (0x92),
+ SPSV, 8,
+ Offset (0x94),
+ GSSU, 1,
+ GSMS, 1,
+ Offset (0x95),
+ MMST, 4,
+ DMST, 4,
+ Offset (0xA0),
+ QBHK, 8,
+ Offset (0xA2),
+ QBBB, 8,
+ Offset (0xA4),
+ MBTS, 1,
+ , 6,
+ BACR, 1,
+ Offset (0xA6),
+ MBDC, 8,
+ Offset (0xA8),
+ ENWD, 1,
+ TMPR, 1,
+ Offset (0xAA),
+ , 1,
+ SMSZ, 1,
+ , 5,
+ RCDS, 1,
+ Offset (0xAD),
+ SADP, 8,
+ Offset (0xB2),
+ RPM1, 8,
+ RPM2, 8,
+ Offset (0xBA),
+ CLOW, 8,
+ CMAX, 8,
+ Offset (0xC1),
+ DPPC, 8,
+ Offset (0xC6),
+ , 1,
+ CVTS, 1,
+ Offset (0xCE),
+ NVDX, 8,
+ ECDX, 8,
+ EBPL, 1,
+ Offset (0xD2),
+ , 7,
+ DLYE, 1,
+ Offset (0xD4),
+ PSHD, 8,
+ PSLD, 8,
+ DBPL, 8,
+ STSP, 8,
+ Offset (0xDA),
+ PSIN, 8,
+ PSKB, 1,
+ PSTP, 1,
+ , 1,
+ PWOL, 1,
+ RTCE, 1,
+ Offset (0xE0),
+ DLYT, 8,
+ DLY2, 8,
+ Offset (0xE6),
+ SFHK, 8,
+ Offset (0xE9),
+ DTMT, 8,
+ PL12, 8,
+ ETMT, 8,
+ Offset (0xF2),
+ ZPDD, 1,
+ , 6,
+ ENPA, 1,
+ Offset (0xF4),
+ SFAN, 8,
+ Offset (0xF9),
+ , 7,
+ FTHM, 1
+ }
+
+ Name (ECOK, 0)
+ Name (BATO, 0)
+ Name (BATN, 0)
+ Name (BATF, 0xC0)
+ Name (TMEE, 0)
+ Name (TMDE, 0)
+
+ Method (BPOL, 1, NotSerialized)
+ {
+ DBPL = Arg0
+ EBPL = 1
+ }
+
+ Method (BPOM, 0, NotSerialized)
+ {
+ DBPL = 0
+ EBPL = 0
+ }
+
+ Method (GBAS, 0, NotSerialized)
+ {
+ If ((ECOK == 1))
+ {
+ BATF = 0
+ Local0 = MBTS /* \_SB_.PCI0.LPCB.EC0_.MBTS */
+ Local1 = SW2S /* \_SB_.PCI0.LPCB.EC0_.SW2S */
+ Local0 <<= 0x06
+ Local1 <<= 1
+ If (((BATO & 0x40) != Local0))
+ {
+ BATF |= 0x40
+ }
+
+ If (((BATO & 0x02) != Local1))
+ {
+ BATF |= 0x02
+ }
+
+ BATO = 0
+ BATO = (Local0 | Local1)
+ }
+ }
+
+ Method (_Q09, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ BPOM ()
+ GBAS ()
+ Notify (BAT0, 0x80) // Status Change
+ Notify (BAT0, 0x81) // Information Change
+ Notify (ADP1, 0x80) // Status Change
+ }
+
+ Method (_Q0D, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ Debug = "_Q0D : Switch Display (Fn+F4)"
+ /*\_SB_.PCI0.GFX0.GHDS (0)*/ /*Todo: fixme? where is this guy defined? */
+ Sleep (0xC8)
+ }
+
+ Method (_Q20, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ If ((ECOK == 1))
+ {
+ GBAS ()
+ If ((0x40 & BATF))
+ {
+ Notify (BAT0, 0x81) // Information Change
+ }
+
+ Notify (BAT0, 0x80) // Status Change
+ If ((0x02 & BATF))
+ {
+ Notify (ADP1, 0x80) // Status Change
+ PWRS = SW2S /* \_SB_.PCI0.LPCB.EC0_.SW2S */
+ }
+
+ PNOT ()
+ }
+ }
+
+ Method (_Q22, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ If ((ECOK == 1))
+ {
+ BACR = 0
+ Notify (BAT0, 0x80) // Status Change
+ }
+ }
+
+ Method (_Q2A, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ Notify (BAT0, 0x81) // Information Change
+ Notify (BAT0, 0x80) // Status Change
+ }
+
+ Method (_Q33, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ Local0 = ^^RTC.RTMN /* \_SB_.PCI0.LPCB.RTC_.RTMN */
+ FromBCD (Local0, Local0)
+ Local1 = ^^RTC.RTHR /* \_SB_.PCI0.LPCB.RTC_.RTHR */
+ FromBCD (Local1, Local1)
+ Local2 = ^^RTC.RTDY /* \_SB_.PCI0.LPCB.RTC_.RTDY */
+ Local3 = ^^RTC.RTSE /* \_SB_.PCI0.LPCB.RTC_.RTSE */
+ FromBCD (Local3, Local3)
+ If ((ECOK == 1))
+ {
+ PSIN = 0xFF
+ Sleep (1)
+ PSLD = Local0
+ PSHD = Local1
+ PSIN = 0x1C
+ Sleep (1)
+ PSLD = Local2
+ PSHD = Local3
+ PSIN = 0x1D
+ }
+ }
+
+ Method (_Q34, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ If ((ECOK == 1))
+ {
+ If ((ENWD == 1))
+ {
+ TMPR = 1
+ }
+ }
+ }
+
+ Method (_Q46, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ If ((ECOK == 1))
+ {
+ If ((CVTS == 1))
+ {
+ Local0 = 0x03
+ Local0 <<= 0x10
+ Local0 |= 0x03
+ Notify (VBPA, 0xCC) // Hardware-Specific
+ }
+
+ If ((CVTS == 0))
+ {
+ Local0 = 0x02
+ Local0 <<= 0x10
+ Local0 |= 0x02
+ Notify (VBPA, 0xCD) // Hardware-Specific
+ }
+ }
+ }
+
+ /* _Q80 _Q82 _Q83 thermal zone methods removed */
+
+ Method (_Q84, 0, Serialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ If ((PHOT == 1))
+ {
+ PHOT = 0x02
+ }
+ }
+
+ Method (_Q85, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ Notify (B0D4, 0x90) // Device-Specific
+ }
+
+ Method (_Q86, 0, Serialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ If ((PHOT == 1))
+ {
+ PHOT = 0x03
+ }
+ }
+
+ Method (_Q8A, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ If ((ECOK == 1))
+ {
+ If (LIDE)
+ {
+ Debug = "_Q8A : LID Switch Event"
+ LIDE = 0
+ Sleep (0x14)
+ Notify (LID0, 0x80) // Status Change
+ }
+ }
+ }
+
+/* TODO: revisit _Q8E _Q8F and wtf is _QE4 for? ? */
+
+#include "ac.asl"
+#include "battery.asl"
+#include "kb.asl"
+#include "mainboard.asl"
+/*#include "tpm.asl"*/
+}
diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/acpi/kb.asl b/src/mainboard/hp/spectre_x360_13t_ae000/acpi/kb.asl
new file mode 100644
index 0000000..296cdba
--- /dev/null
+++ b/src/mainboard/hp/spectre_x360_13t_ae000/acpi/kb.asl
@@ -0,0 +1,159 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Matt Parnell <mparnell(a)gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+// Scope is \_SB.PCI0.LPCB
+
+Device (PS2K)
+{
+ Name (_CID, EisaId ("PNP0303") /* IBM Enhanced Keyboard (101/102-key, PS/2 Mouse) */) // _CID: Compatible ID
+ Method (_HID, 0, NotSerialized) // _HID: Hardware ID
+ {
+ If ((OSYS >= 0x07DC))
+ {
+ Return ("HPQ8001")
+ }
+ Else
+ {
+ Return ("PNP0303")
+ }
+ }
+
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (0x0F)
+ }
+
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0060, // Range Minimum
+ 0x0060, // Range Maximum
+ 0x01, // Alignment
+ 0x01, // Length
+ )
+ IO (Decode16,
+ 0x0064, // Range Minimum
+ 0x0064, // Range Maximum
+ 0x01, // Alignment
+ 0x01, // Length
+ )
+ IRQ (Edge, ActiveHigh, Exclusive, )
+ {1}
+ })
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ StartDependentFn (0x00, 0x00)
+ {
+ FixedIO (
+ 0x0060, // Address
+ 0x01, // Length
+ )
+ FixedIO (
+ 0x0064, // Address
+ 0x01, // Length
+ )
+ IRQNoFlags ()
+ {1}
+ }
+ EndDependentFn ()
+ })
+
+ Method (_PRW, 0, NotSerialized) // _PRW: Power Resources for Wake
+ {
+ If (One)
+ {
+ Return (Package (0x02)
+ {
+ 0x3D,
+ 0x03
+ })
+ }
+ Else
+ {
+ Return (Package (0x02)
+ {
+ 0x1F,
+ 0x03
+ })
+ }
+ }
+
+ Method (_PSW, 1, NotSerialized) // _PSW: Power State Wake
+ {
+ KBWK = Arg0
+ }
+}
+
+Device (PS2M)
+{
+ Method (_HID, 0, NotSerialized) // _HID: Hardware ID
+ {
+ Return ("*SYN326A")
+ }
+
+ Method (_CID, 0, NotSerialized) // _CID: Compatible ID
+ {
+ Return (Package (0x03)
+ {
+ 0x001E2E4F,
+ 0x02002E4F,
+ 0x130FD041
+ })
+ }
+
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (0x0F)
+ }
+
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IRQ (Edge, ActiveHigh, Exclusive, )
+ {12}
+ })
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ StartDependentFn (0x00, 0x00)
+ {
+ IRQNoFlags ()
+ {12}
+ }
+ EndDependentFn ()
+ })
+ Method (_PRW, 0, NotSerialized) // _PRW: Power Resources for Wake
+ {
+ If (One)
+ {
+ Return (Package (0x02)
+ {
+ 0x3D,
+ 0x03
+ })
+ }
+ Else
+ {
+ Return (Package (0x02)
+ {
+ 0x1F,
+ 0x03
+ })
+ }
+ }
+
+ Method (_PSW, 1, NotSerialized) // _PSW: Power State Wake
+ {
+ TPWK = Arg0
+ }
+}
diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/acpi/mainboard.asl b/src/mainboard/hp/spectre_x360_13t_ae000/acpi/mainboard.asl
new file mode 100644
index 0000000..3c7189b
--- /dev/null
+++ b/src/mainboard/hp/spectre_x360_13t_ae000/acpi/mainboard.asl
@@ -0,0 +1,282 @@
+ /*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Matt Parnell <mparnell(a)gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+// Scope (EC0)
+
+Device (RTC)
+{
+ Name (_HID, EisaId ("PNP0B00") /* AT Real-Time Clock */) // _HID: Hardware ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0070, // Range Minimum
+ 0x0070, // Range Maximum
+ 0x01, // Alignment
+ 0x08, // Length
+ )
+ IRQNoFlags ()
+ {8}
+ })
+
+ OperationRegion (CMS0, SystemCMOS, 0, 0x40)
+ Field (CMS0, ByteAcc, NoLock, Preserve)
+ {
+ RTSE, 8,
+ RTSA, 8,
+ RTMN, 8,
+ RTMA, 8,
+ RTHR, 8,
+ RTHA, 8,
+ RTDY, 8,
+ RTDE, 8
+ }
+}
+
+Scope (\_SB.PCI0.LPCB.RTC)
+{
+ OperationRegion (CMS0, SystemCMOS, 0, 0x40)
+ Field (CMS0, ByteAcc, NoLock, Preserve)
+ {
+ RTSE, 8,
+ RTSA, 8,
+ RTMN, 8,
+ RTMA, 8,
+ RTHR, 8,
+ RTHA, 8,
+ RTDY, 8,
+ RTDE, 8
+ }
+}
+
+Device (VBPA)
+{
+ Name (_HID, "INT33D6" /* Intel Virtual Buttons Device */) // _HID: Hardware ID
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ If ((OSYS >= 0x07DD))
+ {
+ Return (0x0F)
+ }
+ Else
+ {
+ Return (0)
+ }
+ }
+
+ Name (VBST, 0)
+ Method (VBDL, 0, NotSerialized)
+ {
+ If ((\_SB_.PCI0.LPCB.EC0.ECOK == 1))
+ {
+ If ((\_SB_.PCI0.LPCB.EC0.CVTS == 0))
+ {
+ VBST = 0x40
+ }
+ Else
+ {
+ VBST = 0
+ }
+ }
+ }
+
+ Method (VGBS, 0, NotSerialized)
+ {
+ If ((\_SB_.PCI0.LPCB.EC0.ECOK == 1))
+ {
+ If ((\_SB_.PCI0.LPCB.EC0.CVTS == 0))
+ {
+ VBST = 0x40
+ }
+ Else
+ {
+ VBST = 0
+ }
+ }
+
+ Return (VBST) /* \_SB_.VBPA.VBST */
+ }
+}
+
+Device (CIND)
+{
+ Name (_HID, "INT33D3" /* Intel GPIO Buttons */) // _HID: Hardware ID
+ Name (_CID, "PNP0C60" /* Display Sensor Device */) // _CID: Compatible ID
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ If ((OSYS >= 0x07DD))
+ {
+ Return (0x0B)
+ }
+ Else
+ {
+ Return (0)
+ }
+ }
+}
+
+Device (GFX0)
+{
+ Name (_ADR, 0x00020000) // _ADR: Address
+}
+
+Device (B0D4)
+{
+Method (PCIC, 1, Serialized)
+ {
+ If ((ECR1 == One))
+ {
+ If ((Arg0 == PCIG))
+ {
+ Return (One)
+ }
+ }
+
+ Return (Zero)
+ }
+
+ Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method
+ {
+ If (PCIC (Arg0))
+ {
+ Return (PCID (Arg0, Arg1, Arg2, Arg3))
+ }
+
+ Return (Buffer (1)
+ {
+ 0x00 // .
+ })
+ }
+
+ Name (_ADR, 0x00040000) // _ADR: Address
+}
+
+Device (ISP0)
+{
+ Name (_ADR, 0x00050000) // _ADR: Address
+}
+
+Scope (\)
+{
+ Name (PCIG, ToUUID ("e5c937d0-3553-4d7a-9117-ea4d19c3434d") /* Device Labeling Interface */)
+ Name (KBWK, 0)
+ Name (TPWK, 0)
+
+ Field (GNVS, AnyAcc, Lock, Preserve)
+ {
+ ECR1, 8
+ }
+
+ OperationRegion (EXBU, SystemMemory, 0x2F822018, 0x3008)
+ Field (EXBU, AnyAcc, Lock, Preserve)
+ {
+ AEAX, 32,
+ AEBX, 32,
+ AECX, 32,
+ AEDX, 32,
+ AREF, 32,
+ DAB0, 8,
+ DAB1, 8,
+ DAB2, 8,
+ DAB3, 8,
+ WBUF, 1024,
+ TJMX, 8,
+ FNKY, 8,
+ CAME, 8,
+ VTDT, 8,
+ DPMD, 8,
+ WLVD, 16,
+ WLDD, 16,
+ WLSV, 16,
+ WLSS, 16,
+ BTVD, 16,
+ BTDD, 16,
+ WWVD, 16,
+ WWDD, 16,
+ WMVD, 16,
+ WMDD, 16,
+ GPVD, 16,
+ GPDD, 16,
+ SMA4, 8,
+ PMEE, 8,
+ WSD0, 8,
+ WSD1, 8,
+ WSD2, 8,
+ WSD3, 8,
+ WAR7, 8,
+ DBCM, 8,
+ CPUP, 64,
+ GPUP, 32,
+ SYSP, 64,
+ FANP, 32,
+ BATP, 32,
+ HDDP, 32,
+ CPUT, 8,
+ GPUT, 8,
+ SYST, 8,
+ FANT, 8,
+ BATT, 8,
+ TTST, 8,
+ RTCF, 8,
+ BODD, 8,
+ BRTM, 8,
+ NOCD, 8,
+ PWVD, 16,
+ PWDD, 16,
+ PWSV, 16,
+ PWSS, 16,
+ Offset (0x400),
+ SBUF, 2048
+ }
+
+ Method (PCID, 4, Serialized)
+ {
+ If ((Arg0 == PCIG))
+ {
+ If ((Arg1 >= 0x03))
+ {
+ If ((Arg2 == Zero))
+ {
+ Return (Buffer (0x02)
+ {
+ 0x01, 0x03 // ..
+ })
+ }
+
+ If ((Arg2 == 0x08))
+ {
+ Return (One)
+ }
+
+ If ((Arg2 == 0x09))
+ {
+ Return (Package (0x05)
+ {
+ 0xC350,
+ Ones,
+ Ones,
+ 0xC350,
+ Ones
+ })
+ }
+ }
+ }
+
+ Return (Buffer (One)
+ {
+ 0x00 // .
+ })
+ }
+}
diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/acpi/superio.asl b/src/mainboard/hp/spectre_x360_13t_ae000/acpi/superio.asl
new file mode 100644
index 0000000..e912e04
--- /dev/null
+++ b/src/mainboard/hp/spectre_x360_13t_ae000/acpi/superio.asl
@@ -0,0 +1,87 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+// Scope is \_SB.PCI0.LPCB
+
+Device (SIO)
+{
+ Name (_HID, EisaId("PNP0A05"))
+ Name (_UID, 0)
+ Name (_ADR, 0)
+
+#ifdef SIO_EC_ENABLE_PS2K
+ Device (PS2K) // Keyboard
+ {
+ Name (_UID, 0)
+ Name (_ADR, 0)
+ Name (_HID, EISAID("PNP0303"))
+ Name (_CID, EISAID("PNP030B"))
+
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0F)
+ }
+
+ Name (_CRS, ResourceTemplate()
+ {
+ FixedIO (0x60, 0x01)
+ FixedIO (0x64, 0x01)
+ IRQNoFlags () {1}
+ })
+
+ Name (_PRS, ResourceTemplate()
+ {
+ StartDependentFn (0, 0)
+ {
+ FixedIO (0x60, 0x01)
+ FixedIO (0x64, 0x01)
+ IRQNoFlags () {1}
+ }
+ EndDependentFn ()
+ })
+ }
+#endif
+
+#ifdef SIO_ENABLE_PS2M
+ Device (PS2M) // Mouse
+ {
+ Name (_HID, EISAID("PNP0F13"))
+
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0F)
+ }
+
+ Name (_CRS, ResourceTemplate()
+ {
+ FixedIO (0x60, 0x01)
+ FixedIO (0x64, 0x01)
+ IRQNoFlags () {12}
+ })
+
+ Name (_PRS, ResourceTemplate()
+ {
+ StartDependentFn (0, 0)
+ {
+ FixedIO (0x60, 0x01)
+ FixedIO (0x64, 0x01)
+ IRQNoFlags () {12}
+ }
+ EndDependentFn ()
+ })
+ }
+#endif
+
+}
diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/acpi/tpm.asl b/src/mainboard/hp/spectre_x360_13t_ae000/acpi/tpm.asl
new file mode 100644
index 0000000..d24d05f
--- /dev/null
+++ b/src/mainboard/hp/spectre_x360_13t_ae000/acpi/tpm.asl
@@ -0,0 +1,446 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Matt Parnell <mparnell(a)gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Device (_SB.TPM)
+{
+ Method (_HID, 0, NotSerialized) // _HID: Hardware ID
+ {
+ If (TCMF)
+ {
+ Return (0x01013469)
+ }
+ ElseIf ((TTDP == Zero))
+ {
+ Return (0x310CD041)
+ }
+ Else
+ {
+ Return ("MSFT0101")
+ }
+ }
+
+ Method (_STR, 0, NotSerialized) // _STR: Description String
+ {
+ If ((TTDP == Zero))
+ {
+ Return (Unicode ("TPM 1.2 Device"))
+ }
+ Else
+ {
+ Return (Unicode ("TPM 2.0 Device"))
+ }
+ }
+
+ Name (_UID, One) // _UID: Unique ID
+ Name (CRST, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadOnly,
+ 0x00000000, // Address Base
+ 0x00001000, // Address Length
+ _Y31)
+ Memory32Fixed (ReadOnly,
+ 0xFED70000, // Address Base
+ 0x00001000, // Address Length
+ _Y32)
+ })
+ Name (CRSD, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite,
+ 0xFED40000, // Address Base
+ 0x00005000, // Address Length
+ _Y33)
+ })
+ Name (CRSI, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite,
+ 0xFED40000, // Address Base
+ 0x00005000, // Address Length
+ _Y34)
+ })
+ Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings
+ {
+ If ((AMDT == One))
+ {
+ CreateDWordField (CRST, \_SB.TPM._Y31._BAS, MTFB) // _BAS: Base Address
+ CreateDWordField (CRST, \_SB.TPM._Y31._LEN, LTFB) // _LEN: Length
+ MTFB = TPMB /* \TPMB */
+ LTFB = 0x1000
+ CreateDWordField (CRST, \_SB.TPM._Y32._BAS, MTFC) // _BAS: Base Address
+ CreateDWordField (CRST, \_SB.TPM._Y32._LEN, LTFC) // _LEN: Length
+ MTFC = TPMC /* \TPMC */
+ LTFC = 0x1000
+ Return (CRST) /* \_SB_.TPM_.CRST */
+ }
+ Else
+ {
+ If ((DTPT == One))
+ {
+ CreateDWordField (CRSD, \_SB.TPM._Y33._BAS, MTFE) // _BAS: Base Address
+ CreateDWordField (CRSD, \_SB.TPM._Y33._LEN, LTFE) // _LEN: Length
+ MTFE = 0xFED40000
+ LTFE = 0x0880
+ Return (CRSD) /* \_SB_.TPM_.CRSD */
+ }
+ ElseIf ((TTPF == One))
+ {
+ CreateDWordField (CRSI, \_SB.TPM._Y34._BAS, MTFD) // _BAS: Base Address
+ CreateDWordField (CRSI, \_SB.TPM._Y34._LEN, LTFD) // _LEN: Length
+ MTFD = 0xFED40000
+ LTFD = 0x5000
+ Return (CRSI) /* \_SB_.TPM_.CRSI */
+ }
+ ElseIf ((TTPF == Zero))
+ {
+ CreateDWordField (CRSI, \_SB.TPM._Y34._BAS, MTFF) // _BAS: Base Address
+ MTFF = TPMM /* \TPMM */
+ Return (CRSI) /* \_SB_.TPM_.CRSI */
+ }
+
+ MTFE = Zero
+ LTFE = Zero
+ Return (CRSI) /* \_SB_.TPM_.CRSI */
+ }
+
+ Return (CRSI) /* \_SB_.TPM_.CRSI */
+ }
+
+ OperationRegion (TMMB, SystemMemory, 0xFED40000, 0x5000)
+ Field (TMMB, ByteAcc, Lock, Preserve)
+ {
+ Offset (0x04),
+ LCST, 32,
+ Offset (0x40),
+ CREQ, 32,
+ CSTS, 32,
+ Offset (0x4C),
+ SCMD, 32
+ }
+
+ OperationRegion (CRBD, SystemMemory, TPMM, 0x48)
+ Field (CRBD, AnyAcc, NoLock, Preserve)
+ {
+ Offset (0x04),
+ HERR, 32,
+ Offset (0x40),
+ HCMD, 32,
+ HSTS, 32
+ }
+
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ If ((TTDP == Zero))
+ {
+ If (TPMF)
+ {
+ Return (0x0F)
+ }
+
+ Return (Zero)
+ }
+ ElseIf ((TTDP == One))
+ {
+ If (TPMF)
+ {
+ Return (0x0F)
+ }
+
+ Return (Zero)
+ }
+
+ Return (Zero)
+ }
+
+ Method (STRT, 3, Serialized)
+ {
+ OperationRegion (TPMR, SystemMemory, FTPM, 0x1000)
+ Field (TPMR, AnyAcc, NoLock, Preserve)
+ {
+ Offset (0x04),
+ FERR, 32,
+ Offset (0x0C),
+ BEGN, 32
+ }
+
+ Name (TIMR, Zero)
+ If ((ToInteger (Arg0) != Zero)){}
+ Switch (ToInteger (Arg1))
+ {
+ Case (Zero)
+ {
+ Return (Buffer (One)
+ {
+ 0x03 // .
+ })
+ }
+ Case (One)
+ {
+ TIMR = Zero
+ If ((AMDT == One))
+ {
+ While (((BEGN == One) && (TIMR < 0x0200)))
+ {
+ If ((BEGN == One))
+ {
+ Sleep (One)
+ TIMR++
+ }
+ }
+ }
+ ElseIf ((((HSTS & 0x02) | (HSTS & One)
+ ) == 0x03))
+ {
+ HCMD = One
+ }
+ Else
+ {
+ FERR = One
+ BEGN = Zero
+ }
+
+ Return (Zero)
+ }
+
+ }
+
+ Return (One)
+ }
+
+ Method (CRYF, 3, Serialized)
+ {
+ If ((ToInteger (Arg0) != One)){}
+ Switch (ToInteger (Arg1))
+ {
+ Case (Zero)
+ {
+ Return (Buffer (One)
+ {
+ 0x03 // .
+ })
+ }
+ Case (One)
+ {
+ Name (TPMV, Package (0x02)
+ {
+ One,
+ Package (0x02)
+ {
+ One,
+ 0x20
+ }
+ })
+ If ((_STA () == Zero))
+ {
+ Return (Package (0x01)
+ {
+ Zero
+ })
+ }
+
+ Return (TPMV) /* \_SB_.TPM_.CRYF.TPMV */
+ }
+
+ }
+
+ Return (Buffer (One)
+ {
+ 0x00 // .
+ })
+ }
+}
+
+
+
+Scope (_SB.TPM)
+{
+ OperationRegion (TSMI, SystemIO, SMIA, 0x02)
+ Field (TSMI, WordAcc, NoLock, Preserve)
+ {
+ SMI, 16
+ }
+
+ OperationRegion (ATNV, SystemMemory, PPIM, PPIL)
+ Field (ATNV, AnyAcc, NoLock, Preserve)
+ {
+ RQST, 32,
+ RCNT, 32,
+ ERRO, 32,
+ FLAG, 32,
+ MISC, 32,
+ OPTN, 32,
+ SRSP, 32
+ }
+
+ Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method
+ {
+ If ((Arg0 == ToUUID ("3dddfaa6-361b-4eb4-a424-8d10089d1653") /* Physical Presence Interface */))
+ {
+ Switch (ToInteger (Arg2))
+ {
+ Case (Zero)
+ {
+ Return (Buffer (0x02)
+ {
+ 0xFF, 0x01 // ..
+ })
+ }
+ Case (One)
+ {
+ If ((PPIV == Zero))
+ {
+ Return ("1.2")
+ }
+ Else
+ {
+ Return ("1.3")
+ }
+ }
+ Case (0x02)
+ {
+ RQST = DerefOf (Arg3 [Zero])
+ SRSP = Zero
+ FLAG = 0x02
+ TMF1 = OFST /* \OFST */
+ SRSP = Zero
+ SMI = TMF1 /* \TMF1 */
+ Return (SRSP) /* \_SB_.TPM_.SRSP */
+ }
+ Case (0x03)
+ {
+ Name (PPI1, Package (0x02)
+ {
+ Zero,
+ Zero
+ })
+ PPI1 [One] = RQST /* \_SB_.TPM_.RQST */
+ Return (PPI1) /* \_SB_.TPM_._DSM.PPI1 */
+ }
+ Case (0x04)
+ {
+ Return (TRST) /* \TRST */
+ }
+ Case (0x05)
+ {
+ Name (PPI2, Package (0x03)
+ {
+ Zero,
+ Zero,
+ Zero
+ })
+ SRSP = Zero
+ FLAG = 0x05
+ SMI = OFST /* \OFST */
+ PPI2 [One] = RCNT /* \_SB_.TPM_.RCNT */
+ PPI2 [0x02] = ERRO /* \_SB_.TPM_.ERRO */
+ Return (PPI2) /* \_SB_.TPM_._DSM.PPI2 */
+ }
+ Case (0x06)
+ {
+ Return (0x03)
+ }
+ Case (0x07)
+ {
+ RQST = DerefOf (Arg3 [Zero])
+ FLAG = 0x07
+ OPTN = Zero
+ If ((RQST == 0x17))
+ {
+ ToInteger (DerefOf (Arg3 [One]), OPTN) /* \_SB_.TPM_.OPTN */
+ }
+
+ TMF1 = OFST /* \OFST */
+ SRSP = Zero
+ SMI = TMF1 /* \TMF1 */
+ Return (SRSP) /* \_SB_.TPM_.SRSP */
+ }
+ Case (0x08)
+ {
+ RQST = DerefOf (Arg3 [Zero])
+ FLAG = 0x08
+ TMF1 = OFST /* \OFST */
+ SRSP = Zero
+ SMI = TMF1 /* \TMF1 */
+ Return (SRSP) /* \_SB_.TPM_.SRSP */
+ }
+ Default
+ {
+ }
+
+ }
+ }
+ ElseIf ((Arg0 == ToUUID ("376054ed-cc13-4675-901c-4756d7f2d45d")))
+ {
+ Switch (ToInteger (Arg2))
+ {
+ Case (Zero)
+ {
+ Return (Buffer (One)
+ {
+ 0x03 // .
+ })
+ }
+ Case (One)
+ {
+ RQST = DerefOf (Arg3 [Zero])
+ FLAG = 0x09
+ TMF1 = OFST /* \OFST */
+ SRSP = Zero
+ SMI = TMF1 /* \TMF1 */
+ Return (SRSP) /* \_SB_.TPM_.SRSP */
+ }
+ Default
+ {
+ }
+
+ }
+ }
+
+ If ((Arg0 == ToUUID ("cf8e16a5-c1e8-4e25-b712-4f54a96702c8")))
+ {
+ Return (CRYF (Arg1, Arg2, Arg3))
+ }
+
+ If ((Arg0 == ToUUID ("6bbf6cab-5463-4714-b7cd-f0203c0368d4")))
+ {
+ Return (STRT (Arg1, Arg2, Arg3))
+ }
+
+ Return (Buffer (One)
+ {
+ 0x00 // .
+ })
+ }
+
+ Method (TPTS, 1, Serialized)
+ {
+ Switch (ToInteger (Arg0))
+ {
+ Case (0x04)
+ {
+ RQST = Zero
+ FLAG = 0x09
+ SRSP = Zero
+ SMI = OFST /* \OFST */
+ }
+ Case (0x05)
+ {
+ RQST = Zero
+ FLAG = 0x09
+ SRSP = Zero
+ SMI = OFST /* \OFST */
+ }
+
+ }
+ }
+}
diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/acpi_tables.c b/src/mainboard/hp/spectre_x360_13t_ae000/acpi_tables.c
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/src/mainboard/hp/spectre_x360_13t_ae000/acpi_tables.c
diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/board_info.txt b/src/mainboard/hp/spectre_x360_13t_ae000/board_info.txt
new file mode 100644
index 0000000..62be952
--- /dev/null
+++ b/src/mainboard/hp/spectre_x360_13t_ae000/board_info.txt
@@ -0,0 +1,10 @@
+Vendor name: HP
+Board name: Spectre 13t-ae000
+Board serial: DAOX33MBAFO
+Board URL: https://support.hp.com/us-en/product/HP-Spectre-13-ae000-x360-Convertible-P…
+Category: laptop
+ROM package: SOIC8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: n
+Release year: 2017
diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/devicetree.cb b/src/mainboard/hp/spectre_x360_13t_ae000/devicetree.cb
new file mode 100644
index 0000000..2bf6b15
--- /dev/null
+++ b/src/mainboard/hp/spectre_x360_13t_ae000/devicetree.cb
@@ -0,0 +1,221 @@
+chip soc/intel/skylake
+
+ # Enable deep Sx states
+ register "deep_s3_enable_ac" = "0"
+ register "deep_s3_enable_dc" = "0"
+ register "deep_s5_enable_ac" = "0"
+ register "deep_s5_enable_dc" = "0"
+ register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
+
+ register "eist_enable" = "1"
+
+ # Set the Thermal Control Circuit (TCC) activaction value to 95C
+ # even though FSP integration guide says to set it to 100C for SKL-U
+ # (offset at 0), because when the TCC activates at 100C, the CPU
+ # will have already shut itself down from overheating protection.
+ register "tcc_offset" = "5" # TCC of 95C
+
+ # GPE configuration
+ # Note that GPE events called out in ASL code rely on this
+ # route. i.e. If this route changes then the affected GPE
+ # offset bits also need to be changed.
+ register "gpe0_dw0" = "GPP_C"
+ register "gpe0_dw1" = "GPP_D"
+ register "gpe0_dw2" = "GPP_E"
+
+# these are probably very wrong
+ # Enable EC Port 0x68/0x6C
+ register "gen1_dec" = "0x00040069"
+
+ # EC range is 0x800-0x9ff
+ register "gen2_dec" = "0x00fc0901"
+
+ # EC range is 0x1610-0x161F
+ register "gen3_dec" = "0x0001C1611"
+
+ # Enable "Intel Speed Shift Technology"
+ register "speed_shift_enable" = "1"
+
+ # Disable DPTF
+ register "dptf_enable" = "0"
+
+ # FSP Configuration
+ register "ProbelessTrace" = "0"
+ register "EnableLan" = "0"
+ register "EnableSata" = "0" # do we actually need this with only nvme?
+ register "SataSalpSupport" = "0"
+ register "SataMode" = "0"
+ register "SataPortsEnable[0]" = "0"
+ register "SataPortsEnable[1]" = "0"
+ register "SataPortsEnable[2]" = "0"
+ register "SataPortsDevSlp[0]" = "0"
+ register "SataPortsDevSlp[2]" = "0"
+ register "SataSpeedLimit" = "2"
+ register "EnableAzalia" = "1"
+ register "DspEnable" = "0"
+ register "IoBufferOwnership" = "0"
+ register "EnableTraceHub" = "0"
+ register "SsicPortEnable" = "0"
+ register "SmbusEnable" = "1"
+ register "Cio2Enable" = "0"
+ register "ScsEmmcEnabled" = "0"
+ register "ScsEmmcHs400Enabled" = "0"
+ register "ScsSdCardEnabled" = "0"
+ register "PttSwitch" = "0"
+ register "SkipExtGfxScan" = "1"
+ register "Device4Enable" = "1"
+ register "HeciEnabled" = "0"
+ register "SaGv" = "3"
+ register "PmConfigSlpS3MinAssert" = "2" # 50ms
+ register "PmConfigSlpS4MinAssert" = "1" # 1s
+ register "PmConfigSlpSusMinAssert" = "3" # 500ms
+ register "PmConfigSlpAMinAssert" = "3" # 2s
+ register "PmTimerDisabled" = "0"
+
+ # EC/KBC requires continuous mode
+ register "serirq_mode" = "SERIRQ_CONTINUOUS"
+
+ register "pirqa_routing" = "PCH_IRQ11"
+ register "pirqb_routing" = "PCH_IRQ10"
+ register "pirqc_routing" = "PCH_IRQ11"
+ register "pirqd_routing" = "PCH_IRQ11"
+ register "pirqe_routing" = "PCH_IRQ11"
+ register "pirqf_routing" = "PCH_IRQ11"
+ register "pirqg_routing" = "PCH_IRQ11"
+ register "pirqh_routing" = "PCH_IRQ11"
+
+ # VR Settings Configuration for 4 Domains
+ #+----------------+-----------+-----------+-------------+----------+
+ #| Domain/Setting | SA | IA | GT Unsliced | GT |
+ #+----------------+-----------+-----------+-------------+----------+
+ #| Psi1Threshold | 20A | 20A | 20A | 20A |
+ #| Psi2Threshold | 4A | 5A | 5A | 5A |
+ #| Psi3Threshold | 1A | 1A | 1A | 1A |
+ #| Psi3Enable | 1 | 1 | 1 | 1 |
+ #| Psi4Enable | 1 | 1 | 1 | 1 |
+ #| ImonSlope | 0 | 0 | 0 | 0 |
+ #| ImonOffset | 0 | 0 | 0 | 0 |
+ #| IccMax | 7A | 34A | 35A | 35A |
+ #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
+ #| AC LoadLine | 15 mOhm | 5.7 mOhm | 5.2 mOhm | 5.2 mOhm |
+ #| DC LoadLine | 14.3 mOhm | 4.83 mOhm | 4.2 mOhm | 4.2 mOhm |
+ #+----------------+-----------+-----------+-------------+----------+
+ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(4),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .icc_max = VR_CFG_AMP(7),
+ .voltage_limit = 1520,
+ .ac_loadline = 1500,
+ .dc_loadline = 1430,
+ }"
+
+ register "domain_vr_config[VR_IA_CORE]" = "{
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(5),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .icc_max = VR_CFG_AMP(34),
+ .voltage_limit = 1520,
+ .ac_loadline = 570,
+ .dc_loadline = 483,
+ }"
+
+ register "domain_vr_config[VR_GT_UNSLICED]" = "{
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(5),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .icc_max = VR_CFG_AMP(35),
+ .voltage_limit = 1520,
+ .ac_loadline = 520,
+ .dc_loadline = 420,
+ }"
+
+ register "domain_vr_config[VR_GT_SLICED]" = "{
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(5),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .icc_max = VR_CFG_AMP(35),
+ .voltage_limit = 1520,
+ .ac_loadline = 520,
+ .dc_loadline = 420,
+ }"
+
+ # Enable Root Ports 5 and 9
+ register "PcieRpEnable[0]" = "1"
+ register "PcieRpEnable[1]" = "1"
+ register "PcieRpEnable[4]" = "1"
+ register "PcieRpEnable[8]" = "1"
+
+ # NVMe for port 9 settings
+ register "PcieRpClkReqSupport[8]" = "1"
+ register "PcieRpClkReqNumber[8]" = "1"
+ register "PcieRpAdvancedErrorReporting[8]" = "1"
+ register "PcieRpLtrEnable[8]" = "1"
+ register "PcieRpClkSrcNumber[8]" = "1"
+
+ # USB2
+ register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # Type-A Port Left
+ register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC1)" # Type-C Port
+ register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC1)" # Type-C Port
+ register "usb2_ports[4]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera
+ register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
+
+ # USB3
+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port
+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port
+ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port
+
+ # PL2 override 25W
+ register "tdp_pl2_override" = "25"
+
+ # Send an extra VR mailbox command for the PS4 exit issue
+ register "SendVrMbxCmd" = "2"
+
+ # Lock Down
+ register "common_soc_config" = "{
+ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+ }"
+
+ device cpu_cluster 0 on
+ device lapic 0 on end
+ end
+ device domain 0 on
+ device pci 00.0 on end # Host Bridge
+ device pci 02.0 on end # UHD Graphics 620
+ device pci 04.0 on end # Thermal Subsystem DSP
+ device pci 13.0 on end # Intel Sensor Hub
+ device pci 14.0 on end # USB 3 Controller
+ device pci 14.2 on end # Thermal Subsystem DSP
+ device pci 15.0 on end # I2C Controller
+ device pci 1c.0 on end # PCIe Root Port 1
+ device pci 1c.1 on end # PCIe Root Port 2
+ device pci 1c.4 on end # PCIe Root Port 5
+ device pci 1d.0 on end # PCIe Root Port 9
+ device pci 1e.0 off end # UART
+ device pci 1e.2 off end # SPI
+ device pci 1f.0 on end # ISA Bridge
+ device pci 1f.2 on end # Memory Controller
+ device pci 1f.3 on end # Intel HDA
+ device pci 1f.4 on end # SMBus
+ end
+end
diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/dsdt.asl b/src/mainboard/hp/spectre_x360_13t_ae000/dsdt.asl
new file mode 100644
index 0000000..d36c960
--- /dev/null
+++ b/src/mainboard/hp/spectre_x360_13t_ae000/dsdt.asl
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2015 Google Inc.
+ * Copyright (C) 2015 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x02, // DSDT revision: ACPI v2.0 and up
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x01072009 // OEM revision
+)
+{
+ // Some generic macros
+ #include <soc/intel/skylake/acpi/platform.asl>
+
+ // global NVS and variables
+ #include <soc/intel/skylake/acpi/globalnvs.asl>
+
+ // CPU
+ #include <cpu/intel/common/acpi/cpu.asl>
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ #include <soc/intel/skylake/acpi/systemagent.asl>
+ #include <soc/intel/skylake/acpi/pch.asl>
+ }
+
+ }
+
+ // Chipset specific sleep states
+ #include <soc/intel/skylake/acpi/sleepstates.asl>
+}
diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/gpio.h b/src/mainboard/hp/spectre_x360_13t_ae000/gpio.h
new file mode 100644
index 0000000..42a6287
--- /dev/null
+++ b/src/mainboard/hp/spectre_x360_13t_ae000/gpio.h
@@ -0,0 +1,202 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Matt Parnell <mparnell(a)gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef MAINBOARD_GPIO_H
+#define MAINBOARD_GPIO_H
+
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+
+#ifndef __ACPI__
+
+/* Pad configuration in ramstage. */
+static const struct pad_config gpio_table[] = {
+/* ------- GPIO group GPP_A ------- */
+/* RCIN# */_PAD_CFG_STRUCT(GPP_A0, 0x44000702, 0x18),
+/* LAD0 */_PAD_CFG_STRUCT(GPP_A1, 0x44000702, 0x3c19),
+/* LAD1 */_PAD_CFG_STRUCT(GPP_A2, 0x44000702, 0x3c1a),
+/* LAD2 */_PAD_CFG_STRUCT(GPP_A3, 0x44000702, 0x3c1b),
+/* LAD3 */_PAD_CFG_STRUCT(GPP_A4, 0x44000702, 0x3c1c),
+/* LFRAME# */_PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x1d),
+/* SERIRQ */_PAD_CFG_STRUCT(GPP_A6, 0x44000702, 0x1e),
+/* GPIO */_PAD_CFG_STRUCT(GPP_A7, 0x82080102, 0x1f),
+/* CLKRUN# */_PAD_CFG_STRUCT(GPP_A8, 0x44000702, 0x20),
+/* CLKOUT_LPC0 */_PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x1021),
+/* CLKOUT_LPC1 */_PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x1022),
+/* GPIO */_PAD_CFG_STRUCT(GPP_A11, 0x44000300, 0x23),
+/* ISH_GP6 */_PAD_CFG_STRUCT(GPP_A12, 0x44000b02, 0x24),
+/* SUSWARN#/SUSPWRDNACK */_PAD_CFG_STRUCT(GPP_A13, 0x44000700, 0x25),
+/* GPIO */_PAD_CFG_STRUCT(GPP_A14, 0x44000300, 0x26),
+/* SUS_ACK# */_PAD_CFG_STRUCT(GPP_A15, 0x44000702, 0x3027),
+/* GPIO */_PAD_CFG_STRUCT(GPP_A16, 0x44000300, 0x28),
+/* GPIO */_PAD_CFG_STRUCT(GPP_A17, 0x44000100, 0x29),
+/* ISH_GP0 */_PAD_CFG_STRUCT(GPP_A18, 0x44000700, 0x2a),
+/* ISH_GP1 */_PAD_CFG_STRUCT(GPP_A19, 0x44000700, 0x2b),
+/* ISH_GP2 */_PAD_CFG_STRUCT(GPP_A20, 0x44000700, 0x2c),
+/* ISH_GP3 */_PAD_CFG_STRUCT(GPP_A21, 0x44000700, 0x2d),
+/* ISH_GP4 */_PAD_CFG_STRUCT(GPP_A22, 0x44000700, 0x2e),
+/* ISH_GP5 */_PAD_CFG_STRUCT(GPP_A23, 0x44000502, 0x3f),
+/* ------- GPIO Group GPP_B -------*/
+/* GPIO */_PAD_CFG_STRUCT(GPP_B0, 0x44000300, 0x30),
+/* GPIO */_PAD_CFG_STRUCT(GPP_B1, 0x44000300, 0x31),
+/* GPIO */_PAD_CFG_STRUCT(GPP_B2, 0x44000300, 0x32),
+/* GPIO */_PAD_CFG_STRUCT(GPP_B3, 0x84000300, 0x33),
+/* GPIO */_PAD_CFG_STRUCT(GPP_B4, 0x44000301, 0x34),
+/* SRCCLKREQ0# */_PAD_CFG_STRUCT(GPP_B5, 0x44000700, 0x35),
+/* GPIO */_PAD_CFG_STRUCT(GPP_B6, 0x44000300, 0x36),
+/* SRCCLKREQ2# */_PAD_CFG_STRUCT(GPP_B7, 0x44000702, 0x37),
+/* GPIO */_PAD_CFG_STRUCT(GPP_B8, 0x44000300, 0x38),
+/* SRCCLKREQ4# */_PAD_CFG_STRUCT(GPP_B9, 0x44000702, 0x39),
+/* SRCCLKREQ5# */_PAD_CFG_STRUCT(GPP_B10, 0x44000700, 0x3a),
+/* GPIO */_PAD_CFG_STRUCT(GPP_B11, 0x44000300, 0x3b),
+/* GPIO */_PAD_CFG_STRUCT(GPP_B12, 0x44000300, 0x3c),
+/* PLTRST# */_PAD_CFG_STRUCT(GPP_B13, 0x44000700, 0x3d),
+/* SPKR */_PAD_CFG_STRUCT(GPP_B14, 0x44000700, 0x103e),
+/* GSPI0_CS# */_PAD_CFG_STRUCT(GPP_B15, 0x44000700, 0x3f),
+/* GSPI0_CLK */_PAD_CFG_STRUCT(GPP_B16, 0x84000700, 0x40),
+/* GSPI0_MISO */_PAD_CFG_STRUCT(GPP_B17, 0x44000700, 0x41),
+/* GSPI0_MOSI */_PAD_CFG_STRUCT(GPP_B18, 0x84000700, 0x42),
+/* GPIO */_PAD_CFG_STRUCT(GPP_B19, 0x44000300, 0x43),
+/* GPIO */_PAD_CFG_STRUCT(GPP_B20, 0x44000300, 0x1044),
+/* GPIO */_PAD_CFG_STRUCT(GPP_B21, 0x44000300, 0x1045),
+/* GSPIO_MOSI */_PAD_CFG_STRUCT(GPP_B22, 0x44000700, 0x1046),
+/* GPIO */_PAD_CFG_STRUCT(GPP_B23, 0x44000300, 0x47),
+/* ------- GPIO Group GPP_C ------- */
+/* SMBCLK */_PAD_CFG_STRUCT(GPP_C0, 0x44000702, 0x48),
+/* SMBDATA */_PAD_CFG_STRUCT(GPP_C1, 0x44000702, 0x1049),
+/* GPIO */_PAD_CFG_STRUCT(GPP_C2, 0x44000201, 0x104a),
+/* GPIO */_PAD_CFG_STRUCT(GPP_C3, 0x44000201, 0x4b),
+/* GPIO */_PAD_CFG_STRUCT(GPP_C4, 0x44000201, 0x4c),
+/* GPIO */_PAD_CFG_STRUCT(GPP_C5, 0x44000201, 0x4d),
+/* RESERVED */_PAD_CFG_STRUCT(GPP_C6, 0xffffffff, 0xffffff00),
+/* RESERVED */_PAD_CFG_STRUCT(GPP_C7, 0xffffffff, 0xffffff00),
+/* UART0_RXD */_PAD_CFG_STRUCT(GPP_C8, 0x44000700, 0x50),
+/* UART0_TXD */_PAD_CFG_STRUCT(GPP_C9, 0x44000700, 0x51),
+/* UART0_RTS# */_PAD_CFG_STRUCT(GPP_C10, 0x44000700, 0x52),
+/* UART0_CTS# */_PAD_CFG_STRUCT(GPP_C11, 0x44000700, 0x53),
+/* GPIO */_PAD_CFG_STRUCT(GPP_C12, 0x44000300, 0x54),
+/* GPIO */_PAD_CFG_STRUCT(GPP_C13, 0x44000300, 0x55),
+/* GPIO */_PAD_CFG_STRUCT(GPP_C14, 0x44000300, 0x56),
+/* GPIO */_PAD_CFG_STRUCT(GPP_C15, 0x44000300, 0x57),
+/* I2C0_SDA */_PAD_CFG_STRUCT(GPP_C16, 0x44000702, 0x58),
+/* I2C0_SCL */_PAD_CFG_STRUCT(GPP_C17, 0x44000702, 0x59),
+/* GPIO */_PAD_CFG_STRUCT(GPP_C18, 0x44000300, 0x5a),
+/* GPIO */_PAD_CFG_STRUCT(GPP_C19, 0x44000300, 0x5b),
+/* GPIO */_PAD_CFG_STRUCT(GPP_C20, 0x44000300, 0x5c),
+/* GPIO */_PAD_CFG_STRUCT(GPP_C21, 0x44000300, 0x5d),
+/* GPIO */_PAD_CFG_STRUCT(GPP_C22, 0x82880102, 0x105e),
+/* GPIO */_PAD_CFG_STRUCT(GPP_C23, 0x80880102, 0x5f),
+/* ------- GPIO Group GPP_D ------- */
+/* GPIO */_PAD_CFG_STRUCT(GPP_D0, 0x44000300, 0x60),
+/* GPIO */_PAD_CFG_STRUCT(GPP_D1, 0x44000300, 0x61),
+/* GPIO */_PAD_CFG_STRUCT(GPP_D2, 0x44000300, 0x62),
+/* GPIO */_PAD_CFG_STRUCT(GPP_D3, 0x44000300, 0x63),
+/* GPIO */_PAD_CFG_STRUCT(GPP_D4, 0x44000300, 0x64),
+/* ISH_I2C0_SDA */_PAD_CFG_STRUCT(GPP_D5, 0x44000702, 0x65),
+/* ISH_I2C0_SCL */_PAD_CFG_STRUCT(GPP_D6, 0x44000702, 0x66),
+/* ISH_I2C1_SDA */_PAD_CFG_STRUCT(GPP_D7, 0x44000702, 0x67),
+/* ISH_I2C1_SCL */_PAD_CFG_STRUCT(GPP_D8, 0x44000702, 0x68),
+/* GPIO */_PAD_CFG_STRUCT(GPP_D9, 0x82000102, 0x69),
+/* GPIO */_PAD_CFG_STRUCT(GPP_D10, 0x44000200, 0x6a),
+/* GPIO */_PAD_CFG_STRUCT(GPP_D11, 0x44000300, 0x6b),
+/* GPIO */_PAD_CFG_STRUCT(GPP_D12, 0x44000200, 0x6c),
+/* GPIO */_PAD_CFG_STRUCT(GPP_D13, 0x44000300, 0x6d),
+/* GPIO */_PAD_CFG_STRUCT(GPP_D14, 0x44000300, 0x6e),
+/* GPIO */_PAD_CFG_STRUCT(GPP_D15, 0x44000300, 0x6f),
+/* GPIO */_PAD_CFG_STRUCT(GPP_D16, 0x44000300, 0x70),
+/* GPIO */_PAD_CFG_STRUCT(GPP_D17, 0x44000300, 0x71),
+/* GPIO */_PAD_CFG_STRUCT(GPP_D18, 0x44000300, 0x72),
+/* GPIO */_PAD_CFG_STRUCT(GPP_D19, 0x44000300, 0x73),
+/* GPIO */_PAD_CFG_STRUCT(GPP_D20, 0x44000300, 0x74),
+/* GPIO */_PAD_CFG_STRUCT(GPP_D21, 0x44000300, 0x75),
+/* GPIO */_PAD_CFG_STRUCT(GPP_D22, 0x44000300, 0x76),
+/* GPIO */_PAD_CFG_STRUCT(GPP_D23, 0x44000300, 0x77),
+/* ------- GPIO Group GPP_E ------- */
+/* GPIO */_PAD_CFG_STRUCT(GPP_E0, 0x84000102, 0x18),
+/* GPIO */_PAD_CFG_STRUCT(GPP_E1, 0x84000102, 0x19),
+/* SATAXPCIE2 */_PAD_CFG_STRUCT(GPP_E2, 0x84000500, 0x1a),
+/* GPIO */_PAD_CFG_STRUCT(GPP_E3, 0x44000300, 0x1b),
+/* GPIO */_PAD_CFG_STRUCT(GPP_E4, 0x84000200, 0x101c),
+/* GPIO */_PAD_CFG_STRUCT(GPP_E5, 0x44000300, 0x1d),
+/* GPIO */_PAD_CFG_STRUCT(GPP_E6, 0x44000300, 0x1e),
+/* GPIO */_PAD_CFG_STRUCT(GPP_E7, 0x44000300, 0x1f),
+/* GPIO */_PAD_CFG_STRUCT(GPP_E8, 0x44000300, 0x20),
+/* GPIO */_PAD_CFG_STRUCT(GPP_E9, 0x44000300, 0x21),
+/* GPIO */_PAD_CFG_STRUCT(GPP_E10, 0x44000201, 0x22),
+/* GPIO */_PAD_CFG_STRUCT(GPP_E11, 0x80100102, 0x23),
+/* GPIO */_PAD_CFG_STRUCT(GPP_E12, 0x84000201, 0x24),
+/* DDPB_HPD0 */_PAD_CFG_STRUCT(GPP_E13, 0x44000700, 0x25),
+/* DDPC_HPD1 */_PAD_CFG_STRUCT(GPP_E14, 0x44000700, 0x26),
+/* GPIO */_PAD_CFG_STRUCT(GPP_E15, 0x80880300, 0x27),
+/* GPIO */_PAD_CFG_STRUCT(GPP_E16, 0x84000300, 0x28),
+/* EDP_HPD */_PAD_CFG_STRUCT(GPP_E17, 0x44000702, 0x29),
+/* DDPB_CTRLCLK */_PAD_CFG_STRUCT(GPP_E18, 0x44000702, 0x2a),
+/* DDPB_CTRLDATA */_PAD_CFG_STRUCT(GPP_E19, 0x44000702, 0x102b),
+/* DDPC_CTRLCLK */_PAD_CFG_STRUCT(GPP_E20, 0x44000702, 0x2c),
+/* DDPC_CTRLDATA */_PAD_CFG_STRUCT(GPP_E21, 0x44000702, 0x102d),
+/* GPIO */_PAD_CFG_STRUCT(GPP_E22, 0x44000300, 0x2e),
+/* GPIO */_PAD_CFG_STRUCT(GPP_E23, 0x44000201, 0x102f),
+/* ------- GPIO Group GPD ------- */
+/* GPIO */_PAD_CFG_STRUCT(GPD0, 0x4000201, 0x50),
+/* ACPRESENT */_PAD_CFG_STRUCT(GPD1, 0x4000700, 0x51),
+/* GPIO */_PAD_CFG_STRUCT(GPD2, 0x4000200, 0x52),
+/* PWRBTN# */_PAD_CFG_STRUCT(GPD3, 0x4000702, 0x3053),
+/* SLP_S3# */_PAD_CFG_STRUCT(GPD4, 0x4000700, 0x54),
+/* SLP_S4# */_PAD_CFG_STRUCT(GPD5, 0x4000700, 0x55),
+/* SLP_A# */_PAD_CFG_STRUCT(GPD6, 0x4000700, 0x56),
+/* GPIO */_PAD_CFG_STRUCT(GPD7, 0x4000301, 0x57),
+/* GPIO */_PAD_CFG_STRUCT(GPD8, 0x44000300, 0x58),
+/* GPIO */_PAD_CFG_STRUCT(GPD9, 0x44000300, 0x59),
+/* SLP_S5# */_PAD_CFG_STRUCT(GPD10, 0x44000700, 0x5a),
+/* GPIO */_PAD_CFG_STRUCT(GPD11, 0x44000300, 0x5b),
+/* ------- GPIO Group GPP_F ------- */
+/* GPIO */_PAD_CFG_STRUCT(GPP_F0, 0x44000300, 0x30),
+/* GPIO */_PAD_CFG_STRUCT(GPP_F1, 0x44000300, 0x31),
+/* GPIO */_PAD_CFG_STRUCT(GPP_F2, 0x44000300, 0x32),
+/* GPIO */_PAD_CFG_STRUCT(GPP_F3, 0x44000300, 0x33),
+/* GPIO */_PAD_CFG_STRUCT(GPP_F4, 0x44000300, 0x34),
+/* GPIO */_PAD_CFG_STRUCT(GPP_F5, 0x44000300, 0x35),
+/* GPIO */_PAD_CFG_STRUCT(GPP_F6, 0x44000300, 0x36),
+/* GPIO */_PAD_CFG_STRUCT(GPP_F7, 0x44000300, 0x37),
+/* GPIO */_PAD_CFG_STRUCT(GPP_F8, 0x44000100, 0x38),
+/* GPIO */_PAD_CFG_STRUCT(GPP_F9, 0x44000100, 0x39),
+/* I2C5_SDA */_PAD_CFG_STRUCT(GPP_F10, 0x44000702, 0x3a),
+/* I2C5_SCL */_PAD_CFG_STRUCT(GPP_F11, 0x44000702, 0x3b),
+/* GPIO */_PAD_CFG_STRUCT(GPP_F12, 0x44000300, 0x3c),
+/* GPIO */_PAD_CFG_STRUCT(GPP_F13, 0x44000300, 0x3d),
+/* GPIO */_PAD_CFG_STRUCT(GPP_F14, 0x44000300, 0x3e),
+/* GPIO */_PAD_CFG_STRUCT(GPP_F15, 0x44000300, 0x3f),
+/* GPIO */_PAD_CFG_STRUCT(GPP_F16, 0x44000300, 0x40),
+/* GPIO */_PAD_CFG_STRUCT(GPP_F17, 0x44000300, 0x41),
+/* GPIO */_PAD_CFG_STRUCT(GPP_F18, 0x44000300, 0x42),
+/* GPIO */_PAD_CFG_STRUCT(GPP_F19, 0x44000300, 0x43),
+/* GPIO */_PAD_CFG_STRUCT(GPP_F20, 0x44000300, 0x44),
+/* GPIO */_PAD_CFG_STRUCT(GPP_F21, 0x44000300, 0x45),
+/* GPIO */_PAD_CFG_STRUCT(GPP_F22, 0x44000300, 0x46),
+/* GPIO */_PAD_CFG_STRUCT(GPP_F23, 0x44000300, 0x47),
+/* ------- GPIO Group GPP_G ------- */
+/* GPIO */_PAD_CFG_STRUCT(GPP_G0, 0x44000102, 0x48),
+/* GPIO */_PAD_CFG_STRUCT(GPP_G1, 0x44000102, 0x49),
+/* GPIO */_PAD_CFG_STRUCT(GPP_G2, 0x44000100, 0x4a),
+/* GPIO */_PAD_CFG_STRUCT(GPP_G3, 0x44000100, 0x4b),
+/* GPIO */_PAD_CFG_STRUCT(GPP_G4, 0x44000100, 0x4c),
+/* GPIO */_PAD_CFG_STRUCT(GPP_G5, 0x44000100, 0x4d),
+/* GPIO */_PAD_CFG_STRUCT(GPP_G6, 0x44000100, 0x4e),
+/* GPIO */_PAD_CFG_STRUCT(GPP_G7, 0x44000100, 0x4f),
+};
+
+#endif
+
+#endif
diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.c b/src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.c
new file mode 100644
index 0000000..c0de990
--- /dev/null
+++ b/src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.c
@@ -0,0 +1,83 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Intel Corporation
+ * (Written by Naresh G Solanki <naresh.solanki(a)intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <bootstate.h>
+#include <chip.h>
+#include <console/console.h>
+#include <device/azalia_device.h>
+#include <soc/intel/common/hda_verb.h>
+#include <soc/pci_devs.h>
+
+#include "hda_verb.h"
+
+static void codecs_init(u8 *base, u32 codec_mask)
+{
+ int i;
+
+ /* Can support up to 4 codecs */
+ for (i = 3; i >= 0; i--) {
+ if (codec_mask & (1 << i))
+ hda_codec_init(base, i, cim_verb_data_size,
+ cim_verb_data);
+ }
+
+ if (pc_beep_verbs_size)
+ hda_codec_write(base, pc_beep_verbs_size, pc_beep_verbs);
+}
+
+static void mb_hda_codec_init(void *unused)
+{
+ static struct soc_intel_skylake_config *config;
+ u8 *base;
+ struct resource *res;
+ u32 codec_mask;
+ struct device *dev;
+
+ dev = SA_DEV_ROOT;
+ /* Check if HDA is enabled, else return */
+ if (dev == NULL || dev->chip_info == NULL)
+ return;
+
+ config = dev->chip_info;
+
+ /*
+ * IoBufferOwnership 0:HD-A Link, 1:Shared HD-A Link and I2S Port,
+ * 3:I2S Ports. In HDA mode where codec need to be programmed with
+ * verb table
+ */
+ if (config->IoBufferOwnership == 3)
+ return;
+
+ /* Find base address */
+ dev = pcidev_path_on_root(PCH_DEVFN_HDA);
+ if (dev == NULL)
+ return;
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (!res)
+ return;
+
+ base = res2mmio(res, 0, 0);
+ printk(BIOS_DEBUG, "HDA: base = %p\n", base);
+
+ codec_mask = hda_codec_detect(base);
+
+ if (codec_mask) {
+ printk(BIOS_DEBUG, "HDA: codec_mask = %02x\n", codec_mask);
+ codecs_init(base, codec_mask);
+ }
+}
+
+BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, mb_hda_codec_init, NULL);
diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.h b/src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.h
new file mode 100644
index 0000000..510a9ce
--- /dev/null
+++ b/src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.h
@@ -0,0 +1,72 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef HDA_VERB_H
+#define HDA_VERB_H
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ /* coreboot specific header */
+ 0x10ec0295, /* Codec Vendor / Device ID: Realtek */
+ 0x103c83b9, /* Subsystem ID */
+ 0x0000000d, /* Number of NID entries */
+
+ /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x103c83b9 */
+ AZALIA_SUBVENDOR(0x0, 0x103c83b9),
+
+ /* Pin Widget Verb Table */
+
+ /* Pin Complex (NID 0x12) */
+ AZALIA_PIN_CFG(0x0, 0x12, 0xb7a60130),
+
+ /* Pin Complex (NID 0x13) */
+ AZALIA_PIN_CFG(0x0, 0x13, 0x40000000),
+
+ /* Pin Complex (NID 0x14) */
+ AZALIA_PIN_CFG(0x0, 0x14, 0x411111f0),
+
+ /* Pin Complex (NID 0x16) */
+ AZALIA_PIN_CFG(0x0, 0x16, 0x411111f0),
+
+ /* Pin Complex (NID 0x17) */
+ AZALIA_PIN_CFG(0x0, 0x17, 0x90170110),
+
+ /* Pin Complex (NID 0x18) */
+ AZALIA_PIN_CFG(0x0, 0x18, 0x411111f0),
+
+ /* Pin Complex (NID 0x19) */
+ AZALIA_PIN_CFG(0x0, 0x19, 0x03a11040),
+
+ /* Pin Complex (NID 0x1A) */
+ AZALIA_PIN_CFG(0x0, 0x1A, 0x411111f0),
+
+ /* Pin Complex (NID 0x1B) */
+ AZALIA_PIN_CFG(0x0, 0x1B, 0x411111f0),
+
+ /* Pin Complex (NID 0x1D) */
+ AZALIA_PIN_CFG(0x0, 0x1D, 0x40600001),
+
+ /* Pin Complex (NID 0x1E) */
+ AZALIA_PIN_CFG(0x0, 0x1E, 0x411111f0),
+
+ /* Pin Complex (NID 0x21) */
+ AZALIA_PIN_CFG(0x0, 0x21, 0x03211020),
+};
+
+const u32 pc_beep_verbs[] = {
+};
+AZALIA_ARRAY_SIZES;
+#endif
diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/mainboard.c b/src/mainboard/hp/spectre_x360_13t_ae000/mainboard.c
new file mode 100644
index 0000000..462b995
--- /dev/null
+++ b/src/mainboard/hp/spectre_x360_13t_ae000/mainboard.c
@@ -0,0 +1,50 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Purism SPC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <smbios.h>
+#include <string.h>
+#include <cbfs.h>
+
+#define MAX_SERIAL_LENGTH 0x100
+
+const char *smbios_mainboard_serial_number(void)
+{
+ static char serial_number[MAX_SERIAL_LENGTH + 1] = {0};
+ struct cbfsf file;
+
+ if (serial_number[0] != 0)
+ return serial_number;
+
+ if (cbfs_boot_locate(&file, "serial_number", NULL) == 0) {
+ struct region_device cbfs_region;
+ size_t serial_len;
+
+ cbfs_file_data(&cbfs_region, &file);
+
+ serial_len = region_device_sz(&cbfs_region);
+ if (serial_len <= MAX_SERIAL_LENGTH) {
+ if (rdev_readat(&cbfs_region, serial_number, 0,
+ serial_len) == serial_len) {
+ serial_number[serial_len] = 0;
+ return serial_number;
+ }
+ }
+ }
+
+ strncpy(serial_number, CONFIG_MAINBOARD_SERIAL_NUMBER,
+ MAX_SERIAL_LENGTH);
+
+ return serial_number;
+}
diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/ramstage.c b/src/mainboard/hp/spectre_x360_13t_ae000/ramstage.c
new file mode 100644
index 0000000..94f8071
--- /dev/null
+++ b/src/mainboard/hp/spectre_x360_13t_ae000/ramstage.c
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corporation
+ * Copyright (C) 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/ramstage.h>
+#include "gpio.h"
+
+void mainboard_silicon_init_params(FSP_SIL_UPD *params)
+{
+ /* Configure pads prior to SiliconInit() in case there's any
+ * dependencies during hardware initialization. */
+ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/romstage.c b/src/mainboard/hp/spectre_x360_13t_ae000/romstage.c
new file mode 100644
index 0000000..faf4090
--- /dev/null
+++ b/src/mainboard/hp/spectre_x360_13t_ae000/romstage.c
@@ -0,0 +1,79 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2010 coresystems GmbH
+ * Copyright (C) 2015 Google Inc.
+ * Copyright (C) 2015 Intel Corporation
+ * Copyright (C) 2017 Purism SPC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <assert.h>
+#include <soc/romstage.h>
+#include <spd_bin.h>
+#include <string.h>
+
+static void mainboard_fill_dq_map_data(void *dq_map_ptr)
+{
+ /* DQ byte map */
+ const u8 dq_map[2][12] = {
+ { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0,
+ 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 },
+ { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC,
+ 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } };
+ memcpy(dq_map_ptr, dq_map, sizeof(dq_map));
+}
+
+static void mainboard_fill_dqs_map_data(void *dqs_map_ptr)
+{
+ /* DQS CPU<>DRAM map */
+ const u8 dqs_map[2][8] = {
+ { 0, 1, 3, 2, 4, 5, 6, 7 },
+ { 1, 0, 4, 5, 2, 3, 6, 7 } };
+ memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map));
+}
+
+static void mainboard_fill_rcomp_res_data(void *rcomp_ptr)
+{
+ /* Rcomp resistor */
+ const u16 RcompResistor[3] = { 121, 81, 100 };
+ memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor));
+}
+
+static void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr)
+{
+ /* Rcomp target */
+ const u16 RcompTarget[5] = { 100, 40, 20, 20, 26 };
+ memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget));
+}
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+ FSP_M_CONFIG *mem_cfg;
+ struct spd_block blk = {
+ .addr_map = { 0x50 },
+ };
+
+ mem_cfg = &mupd->FspmConfig;
+
+ get_spd_smbus(&blk);
+ dump_spd_info(&blk);
+ assert(blk.spd_array[0][0] != 0);
+
+ mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0);
+ mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0);
+ mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor);
+ mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget);
+
+ mem_cfg->DqPinsInterleaved = TRUE;
+ mem_cfg->MemorySpdDataLen = blk.len;
+ mem_cfg->MemorySpdPtr00 = (uintptr_t) blk.spd_array[0];
+}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ie744cdccd3d110b4137e0b017b3f8497d23c0497
Gerrit-Change-Number: 34946
Gerrit-PatchSet: 1
Gerrit-Owner: Matt Parnell <mparnell(a)gmail.com>
Gerrit-MessageType: newchange
6
55
Change in coreboot[master]: Revert "src/Kconfig: enable USE_BLOBS by default"
by Nico Huber (Code Review) 07 Aug '23
by Nico Huber (Code Review) 07 Aug '23
07 Aug '23
Hello Julius Werner, Angel Pons, Felix Held,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/41848
to review the following change.
Change subject: Revert "src/Kconfig: enable USE_BLOBS by default"
......................................................................
Revert "src/Kconfig: enable USE_BLOBS by default"
This reverts commit a6b887e017f2310db79067b18b216036907b2d90.
It was brought to my attention that the 3rdparty/blobs/ repository
is full of licenses that don't adhere to our binary policy (that
demands unlimited redistribution rights). IANAL, but if the license
texts apply literally, it is not allowed to clone the blobs
repository without reading and agreeing to them.
Change-Id: I7079e23481eb96d1140f2fa5bc1abe7bd4b2bac8
Signed-off-by: Nico Huber <nico.h(a)gmx.de>
---
M src/Kconfig
M util/abuild/abuild
2 files changed, 1 insertion(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/41848/1
diff --git a/src/Kconfig b/src/Kconfig
index 2a2a144..6a748db 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -214,7 +214,6 @@
config USE_BLOBS
bool "Allow use of binary-only repository"
- default y
help
This draws in the blobs repository, which contains binary files that
might be required for some chipsets or boards.
diff --git a/util/abuild/abuild b/util/abuild/abuild
index b6a6bfe..4d5ba35 100755
--- a/util/abuild/abuild
+++ b/util/abuild/abuild
@@ -715,7 +715,7 @@
shift;;
-B|--blobs) shift
customizing="${customizing}, blobs"
- configoptions="${configoptions}CONFIG_USE_AMD_BLOBS=y\nCONFIG_ADD_FSP_BINARIES=y\n"
+ configoptions="${configoptions}CONFIG_USE_BLOBS=y\nCONFIG_USE_AMD_BLOBS=y\nCONFIG_ADD_FSP_BINARIES=y\n"
;;
-A|--any-toolchain) shift
customizing="${customizing}, any-toolchain"
--
To view, visit https://review.coreboot.org/c/coreboot/+/41848
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I7079e23481eb96d1140f2fa5bc1abe7bd4b2bac8
Gerrit-Change-Number: 41848
Gerrit-PatchSet: 1
Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org>
Gerrit-MessageType: newchange
4
8
Change in coreboot[master]: mb/yanling: Add Yanling YL-KBR6L mainboard + doc
by Thomas (Code Review) 07 Aug '23
by Thomas (Code Review) 07 Aug '23
07 Aug '23
Thomas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48769 )
Change subject: mb/yanling: Add Yanling YL-KBR6L mainboard + doc
......................................................................
mb/yanling: Add Yanling YL-KBR6L mainboard + doc
The Yanling YL-KBR6L (aka Yanling N18) is a Protecli FW6 with a newer
CPUs (i5-8250U), different SuperIO chip (ITE IT8613F), slightly
different (newer?) flash memory chip (MX25L6436F) and support for a
mPCIe modem.
Working:
- USB 3.0 front ports (SeaBIOS, Linux and FreeBSD)
- 6 Ethernet ports
- HDMI port with libgfxinit and VGA Option ROM
- flashrom
- PCIe WiFi
- SATA and mSATA
- mPCIe Modem in mSATA slot (tested with Simcom SIM7100E mPCIe)
- Super I/O serial port 0 (RS232 via front RJ45 connector)
- SeaBIOS payload (version rel-1.14.0)
- Booting Ubuntu 20.04, FreeBSD 12.2
- 64GB RAM (tested with Crucial CT2K32G4SFD8266)
Untested (same as Protectli FW6):
- Internal USB 2.0 headers
- Boot with cleaned ME
Misc:
- Removed "ProbelessTrace" in devicetree as done for other boards by
coreboot.
Change-Id: Icbc18914670f87f0943b371400c509ff0eeacf6a
Signed-off-by: Thomas Kupper <thomas.kupper(a)gmail.com>
---
M Documentation/mainboard/index.md
A Documentation/mainboard/yanling/yl-kbr6l.md
A Documentation/mainboard/yanling/yl-kbr6l_front.jpg
A src/mainboard/yanling/Kconfig
A src/mainboard/yanling/Kconfig.name
A src/mainboard/yanling/yl_kbr6l/Kconfig
A src/mainboard/yanling/yl_kbr6l/Kconfig.name
A src/mainboard/yanling/yl_kbr6l/Makefile.inc
A src/mainboard/yanling/yl_kbr6l/acpi/ec.asl
A src/mainboard/yanling/yl_kbr6l/acpi/superio.asl
A src/mainboard/yanling/yl_kbr6l/board_info.txt
A src/mainboard/yanling/yl_kbr6l/bootblock.c
A src/mainboard/yanling/yl_kbr6l/data.vbt
A src/mainboard/yanling/yl_kbr6l/devicetree.cb
A src/mainboard/yanling/yl_kbr6l/dsdt.asl
A src/mainboard/yanling/yl_kbr6l/gma-mainboard.ads
A src/mainboard/yanling/yl_kbr6l/gpio.h
A src/mainboard/yanling/yl_kbr6l/ramstage.c
A src/mainboard/yanling/yl_kbr6l/romstage.c
19 files changed, 820 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/48769/1
diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md
index 95efe55..2480069 100644
--- a/Documentation/mainboard/index.md
+++ b/Documentation/mainboard/index.md
@@ -179,3 +179,7 @@
## UP
- [Squared](up/squared/index.md)
+
+## Yanling
+
+- [YL-KBR6L](yanling/yl-kbr6l.md)
\ No newline at end of file
diff --git a/Documentation/mainboard/yanling/yl-kbr6l.md b/Documentation/mainboard/yanling/yl-kbr6l.md
new file mode 100644
index 0000000..28d1d56
--- /dev/null
+++ b/Documentation/mainboard/yanling/yl-kbr6l.md
@@ -0,0 +1,133 @@
+# Yanling YL-KBR6L
+
+This board and therefore its documentation is very, very similar to the Protectli FW6. This document is based on theirs, all praise to 3mdeb/Protectli.
+
+This page describes how to run coreboot on the [Yanling YL-KBR6L], or [Yanling N18] as it seems to be called officially (and its three CPU variants).
+
+
+
+## Required proprietary blobs
+
+To build a minimal working coreboot image some blobs are required (assuming
+only the BIOS region is being modified).
+
+```eval_rst
++-----------------+---------------------------------+---------------------+
+| Binary file | Apply | Required / Optional |
++=================+=================================+=====================+
+| FSP-M, FSP-S | Intel Firmware Support Package | Required |
++-----------------+---------------------------------+---------------------+
+| microcode | CPU microcode | Required |
++-----------------+---------------------------------+---------------------+
+| vgabios | VGA Option ROM | Optional |
++-----------------+---------------------------------+---------------------+
+```
+
+FSP-M and FSP-S are obtained after splitting the Kaby Lake FSP binary (done
+automatically by the coreboot build system and included into the image) from
+the `3rdparty/fsp` submodule.
+
+Microcode updates are automatically included into the coreboot image by build
+system from the `3rdparty/intel-microcode` submodule.
+
+VGA Option ROM is not required to boot, but if one needs graphics in pre-OS
+stage, it should be included (if not using libgfxinit).
+
+## Flashing coreboot
+
+### Internal programming
+
+The main SPI flash can be accessed using [flashrom]. The first version
+supporting the chipset is flashrom v1.1. Firmware an be easily flashed
+with internal programmer (either BIOS region or full image).
+
+### External programming
+
+The system has an internal flash chip which is a 8 MiB soldered SOIC-8 chip.
+This chip is located on the bottom side of the case (the radiator side). One
+has to remove all screws (in order): 4 top cover screws, 4 side cover screws
+(one side is enough), 4 mainboard screws, 4 CPU screws (under DIMMs). Lift up
+the mainboard and turn around it. The flash chip is near the SoC on the DIMM
+slots side. Use a clip (or solder the wires) to program the chip. Specifically,
+it's a Macronix MX25L6436F M2I-08Q (3V) - [datasheet][MX25L6436F].
+
+## Known issues
+
+- assume the same as for Protectli FW6:
+
+- After flashing with external programmer it is always required to reset RTC
+ with jumper or disconnect coin cell temporarily. Only then the platform will
+ boot after flashing.
+- FW6A does not always work reliably with all DIMMs. Linux happens to hang or
+ gives many panics. This issue was present also with vendor BIOS.
+- Sometimes FSPMemoryInit return errors or hangs (especially with 2 DIMMs
+ connected). A workaround is to power cycle the board (even a few times) or
+ temporarily disconnect DIMM when platform is powered off.
+- When using libgfxinit and SeaBIOS bootsplash, the red color is dim
+
+## Untested
+
+- assume the same as for Protectli FW6:
+
+Not all mainboard's peripherals and functions were tested because of lack of
+the cables or not being populated on the board case.
+
+- Internal USB 2.0 headers
+- Boot with cleaned ME
+
+## Working
+
+- USB 3.0 front ports (SeaBIOS and Linux)
+- 6 Ethernet ports
+- HDMI port with libgfxinit and VGA Option ROM
+- flashrom
+- PCIe WiFi
+- SATA and mSATA
+- mPCIe Modem in mSATA slot (tested with Simcom SIM7100E mPCIe)
+- Super I/O serial port 0 (RS232 via front RJ45 connector)
+- SeaBIOS payload (version rel-1.14)
+- Booting Ubuntu 20.04, FreeBSD 12.2
+- 64GB RAM (tested with Crucial CT2K32G4SFD8266)
+
+## Technology
+
+```eval_rst
++---------------------+-----------------------------------------------+
+| CPU | [Intel Core i5-8250U] |
++---------------------+-----------------------------------------------+
+| PCH | Kaby Lake U w/ iHDCP2.2 Premium |
++---------------------+-----------------------------------------------+
+| Super I/O, EC | ITE IT8613F |
++---------------------+-----------------------------------------------+
+| Coprocessor | Intel Management Engine |
++---------------------+-----------------------------------------------+
+| Ethernet Controller | 6x Intel I211AT |
++---------------------+-----------------------------------------------+
+```
+Information about the PCH can be found in [Intel 7th and 8th gen datasheet vol 1] and [Intel 7th and 8th gen datasheet vol 2].
+
+## Ports
+
+```eval_rst
++---------------------+-----------------------------------------------+
+| Ethernet | 6x 1GbE |
++---------------------+-----------------------------------------------+
+| USB | 4x USB 3.0 |
++---------------------+-----------------------------------------------+
+| Serial/COM | 1x RJ-45 serial port |
++---------------------+-----------------------------------------------+
+| SATA | 1x mSATA (port 0) + 1x SATA 3.0 (port 1) |
++---------------------+-----------------------------------------------+
+| Cellular Modem | 1x mPCIe, shared with mSATA slot, nano-SIM |
++---------------------+-----------------------------------------------+
+| Wifi/Bluetooth | 1x mPCIe slot, under mSATA/Modem, |
+| | supports half-size cards only |
++---------------------+-----------------------------------------------+
+```
+
+[flashrom]: https://flashrom.org/Flashrom
+[Intel 7th and 8th gen datasheet vol 1]: https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/7th…
+[Intel 7th and 8th gen datasheet vol 2]: https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/7th…
+[MX25L6436F]: https://www.mxic.com.tw/Lists/Datasheet/Attachments/7405/MX25L6436F,%203V,%…
+[Yanling YL-KBR6L]: https://www.aliexpress.com/item/1005001813291053.html
+[Yanling N18]:https://www.ylipc.com/product/network_server_network_server/N18_Firewa…
diff --git a/Documentation/mainboard/yanling/yl-kbr6l_front.jpg b/Documentation/mainboard/yanling/yl-kbr6l_front.jpg
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/Documentation/mainboard/yanling/yl-kbr6l_front.jpg
diff --git a/src/mainboard/yanling/Kconfig b/src/mainboard/yanling/Kconfig
new file mode 100644
index 0000000..2972a38
--- /dev/null
+++ b/src/mainboard/yanling/Kconfig
@@ -0,0 +1,15 @@
+if VENDOR_YANLING
+
+choice
+ prompt "Mainboard model"
+
+source "src/mainboard/yanling/*/Kconfig.name"
+
+endchoice
+
+source "src/mainboard/yanling/*/Kconfig"
+
+config MAINBOARD_VENDOR
+ default "Yanling"
+
+endif # VENDOR_YANLING
diff --git a/src/mainboard/yanling/Kconfig.name b/src/mainboard/yanling/Kconfig.name
new file mode 100644
index 0000000..6cc7ef1
--- /dev/null
+++ b/src/mainboard/yanling/Kconfig.name
@@ -0,0 +1,2 @@
+config VENDOR_YANLING
+ bool "Yanling"
diff --git a/src/mainboard/yanling/yl_kbr6l/Kconfig b/src/mainboard/yanling/yl_kbr6l/Kconfig
new file mode 100644
index 0000000..838bc44
--- /dev/null
+++ b/src/mainboard/yanling/yl_kbr6l/Kconfig
@@ -0,0 +1,57 @@
+if BOARD_YANLING_YLKBR6L
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select BOARD_ROMSIZE_KB_8192
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select INTEL_GMA_HAVE_VBT
+ select MAINBOARD_HAS_LIBGFXINIT
+ select SEABIOS_ADD_SERCON_PORT_FILE if PAYLOAD_SEABIOS
+ select SOC_INTEL_KABYLAKE
+ select SPI_FLASH_MACRONIX
+ select SUPERIO_ITE_IT8613E
+ select MAINBOARD_HAS_CRB_TPM
+ select HAVE_INTEL_PTT
+ select TPM2
+
+config IRQ_SLOT_COUNT
+ int
+ default 18
+
+config MAINBOARD_DIR
+ string
+ default "yanling/yl_kbr6l"
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "YLKBR6L"
+
+config DIMM_MAX
+ int
+ default 2
+
+config DIMM_SPD_SIZE
+ int
+ default 512
+
+config MAX_CPUS
+ int
+ default 8
+
+config VGA_BIOS_ID
+ string
+ default "8086,5917"
+
+config PXE_ROM_ID
+ string
+ default "8086,1539"
+
+config CBFS_SIZE
+ hex
+ default 0x600000
+
+config USE_PM_ACPI_TIMER
+ default n
+
+endif
diff --git a/src/mainboard/yanling/yl_kbr6l/Kconfig.name b/src/mainboard/yanling/yl_kbr6l/Kconfig.name
new file mode 100644
index 0000000..8b039de
--- /dev/null
+++ b/src/mainboard/yanling/yl_kbr6l/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_YANLING_YLKBR6L
+ bool "YLKBR6L"
diff --git a/src/mainboard/yanling/yl_kbr6l/Makefile.inc b/src/mainboard/yanling/yl_kbr6l/Makefile.inc
new file mode 100644
index 0000000..4cd7aac
--- /dev/null
+++ b/src/mainboard/yanling/yl_kbr6l/Makefile.inc
@@ -0,0 +1,7 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+
+bootblock-y += bootblock.c
+
+ramstage-y += ramstage.c
+
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/yanling/yl_kbr6l/acpi/ec.asl b/src/mainboard/yanling/yl_kbr6l/acpi/ec.asl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/src/mainboard/yanling/yl_kbr6l/acpi/ec.asl
diff --git a/src/mainboard/yanling/yl_kbr6l/acpi/superio.asl b/src/mainboard/yanling/yl_kbr6l/acpi/superio.asl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/src/mainboard/yanling/yl_kbr6l/acpi/superio.asl
diff --git a/src/mainboard/yanling/yl_kbr6l/board_info.txt b/src/mainboard/yanling/yl_kbr6l/board_info.txt
new file mode 100644
index 0000000..c12e388
--- /dev/null
+++ b/src/mainboard/yanling/yl_kbr6l/board_info.txt
@@ -0,0 +1,6 @@
+Vendor name: Yanling
+Board name: YL-KBR6L
+Category: sbc
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/yanling/yl_kbr6l/bootblock.c b/src/mainboard/yanling/yl_kbr6l/bootblock.c
new file mode 100644
index 0000000..e35a7cc
--- /dev/null
+++ b/src/mainboard/yanling/yl_kbr6l/bootblock.c
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <bootblock_common.h>
+#include <superio/ite/it8613e/it8613e.h>
+#include <superio/ite/common/ite.h>
+
+#define GPIO_DEV PNP_DEV(0x2e, IT8613E_GPIO)
+#define UART_DEV PNP_DEV(0x2e, IT8613E_SP1)
+
+void bootblock_mainboard_early_init(void)
+{
+ ite_reg_write(GPIO_DEV, 0x2c, 0x41); /* disable K8 power seq */
+ ite_reg_write(GPIO_DEV, 0x2d, 0x02); /* PCICLK 25MHz */
+ ite_enable_serial(UART_DEV, CONFIG_TTYS0_BASE);
+}
diff --git a/src/mainboard/yanling/yl_kbr6l/data.vbt b/src/mainboard/yanling/yl_kbr6l/data.vbt
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/src/mainboard/yanling/yl_kbr6l/data.vbt
diff --git a/src/mainboard/yanling/yl_kbr6l/devicetree.cb b/src/mainboard/yanling/yl_kbr6l/devicetree.cb
new file mode 100644
index 0000000..b57ab96
--- /dev/null
+++ b/src/mainboard/yanling/yl_kbr6l/devicetree.cb
@@ -0,0 +1,278 @@
+chip soc/intel/skylake
+
+ # Enable deep Sx states
+ register "deep_s3_enable_ac" = "0"
+ register "deep_s3_enable_dc" = "0"
+ register "deep_s5_enable_ac" = "1"
+ register "deep_s5_enable_dc" = "1"
+ register "deep_sx_config" = "DSX_EN_WAKE_PIN | DSX_DIS_AC_PRESENT_PD"
+ register "s0ix_enable" = "1"
+
+ register "gpe0_dw0" = "GPP_B"
+ register "gpe0_dw1" = "GPP_D"
+ register "gpe0_dw2" = "GPP_E"
+
+ register "gen1_dec" = "0x00fc0201"
+ register "gen2_dec" = "0x007c0a01"
+ register "gen3_dec" = "0x000c03e1"
+ register "gen4_dec" = "0x001c02e1"
+
+ register "eist_enable" = "1"
+
+ # Disable DPTF
+ register "dptf_enable" = "0"
+
+ # Enable VT-d
+ register "ignore_vtd" = "0"
+
+ # Enable SERIRQ continuous
+ register "serirq_mode" = "SERIRQ_CONTINUOUS"
+
+ register "tcc_offset" = "5" # TCC of 95C
+
+ # FSP Configuration
+ register "SataSalpSupport" = "0"
+ register "SataMode" = "0"
+ register "DspEnable" = "0"
+ register "IoBufferOwnership" = "0"
+ register "SsicPortEnable" = "0"
+ register "ScsEmmcHs400Enabled" = "0"
+ register "SkipExtGfxScan" = "1"
+ register "HeciEnabled" = "1"
+ register "SaGv" = "SaGv_Enabled"
+ register "IslVrCmd" = "2"
+ register "PmConfigSlpS3MinAssert" = "2" # 50ms
+ register "PmConfigSlpS4MinAssert" = "4" # 4s
+ register "PmConfigSlpSusMinAssert" = "1" # 500ms
+ register "PmConfigSlpAMinAssert" = "3" # 2s
+
+ # VR Settings Configuration for 4 Domains
+ #+----------------+-------+-------+-------+-------+
+ #| Domain/Setting | SA | IA | GTUS | GTS |
+ #+----------------+-------+-------+-------+-------+
+ #| Psi1Threshold | 20A | 20A | 20A | 20A |
+ #| Psi2Threshold | 4A | 5A | 5A | 5A |
+ #| Psi3Threshold | 1A | 1A | 1A | 1A |
+ #| Psi3Enable | 1 | 1 | 1 | 1 |
+ #| Psi4Enable | 1 | 1 | 1 | 1 |
+ #| ImonSlope | 0 | 0 | 0 | 0 |
+ #| ImonOffset | 0 | 0 | 0 | 0 |
+ #| IccMax | 7A | 34A | 35A | 35A |
+ #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
+ #| AcLoadline(ohm)| 10.3m | 2.4m | 3.1m | 3.1m |
+ #| DcLoadline(ohm)| 10.3m | 2.4m | 3.1m | 3.1m |
+ #+----------------+-------+-------+-------+-------+
+ #Note: IccMax settings are moved to SoC code
+ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(4),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .voltage_limit = 1520,
+ }"
+
+ register "domain_vr_config[VR_IA_CORE]" = "{
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(5),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .voltage_limit = 1520,
+ }"
+
+ register "domain_vr_config[VR_GT_UNSLICED]" = "{
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(5),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .voltage_limit = 1520,
+ }"
+
+ register "domain_vr_config[VR_GT_SLICED]" = "{
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(5),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .voltage_limit = 1520,
+ }"
+
+ # Send an extra VR mailbox command for the PS4 exit issue
+ register "SendVrMbxCmd" = "2"
+
+ # Enable SATA ports 1,2
+ register "SataPortsEnable[0]" = "1"
+ register "SataPortsEnable[1]" = "1"
+ register "SataPortsEnable[2]" = "0"
+ register "SataPortsDevSlp[0]" = "0"
+ register "SataPortsDevSlp[1]" = "0"
+
+ # Enable Root ports. 1-6 for LAN and Root Port 9
+ register "PcieRpEnable[0]" = "1"
+ register "PcieRpEnable[1]" = "1"
+ register "PcieRpEnable[2]" = "1"
+ register "PcieRpEnable[3]" = "1"
+ register "PcieRpEnable[4]" = "1"
+ register "PcieRpEnable[5]" = "1"
+ register "PcieRpEnable[8]" = "1" # mPCIe WiFi
+
+ # Enable Advanced Error Reporting for RP 1-6, 9
+ register "PcieRpAdvancedErrorReporting[0]" = "1"
+ register "PcieRpAdvancedErrorReporting[1]" = "1"
+ register "PcieRpAdvancedErrorReporting[2]" = "1"
+ register "PcieRpAdvancedErrorReporting[3]" = "1"
+ register "PcieRpAdvancedErrorReporting[4]" = "1"
+ register "PcieRpAdvancedErrorReporting[5]" = "1"
+ register "PcieRpAdvancedErrorReporting[8]" = "1"
+
+ # Enable Latency Tolerance Reporting Mechanism RP 1-6, 9
+ register "PcieRpLtrEnable[0]" = "1"
+ register "PcieRpLtrEnable[1]" = "1"
+ register "PcieRpLtrEnable[2]" = "1"
+ register "PcieRpLtrEnable[3]" = "1"
+ register "PcieRpLtrEnable[4]" = "1"
+ register "PcieRpLtrEnable[5]" = "1"
+ register "PcieRpLtrEnable[8]" = "1"
+
+ # TODO: Check why protectli used them and WiFi won't work
+ # for me if I set them -> err: lost pci device
+ # Enable RP 9 CLKREQ# support
+ #register "PcieRpClkReqSupport[8]" = "1"
+ # RP 9 uses CLKREQ0#
+ #register "PcieRpClkReqNumber[8]" = "0"
+
+ # Clocks 0-5 for RP 1-6
+ register "PcieRpClkSrcNumber[0]" = "0"
+ register "PcieRpClkSrcNumber[1]" = "1"
+ register "PcieRpClkSrcNumber[2]" = "2"
+ register "PcieRpClkSrcNumber[3]" = "3"
+ register "PcieRpClkSrcNumber[4]" = "4"
+ register "PcieRpClkSrcNumber[5]" = "5"
+ # RP 9 shares CLKSRC5# with RP 6
+ register "PcieRpClkSrcNumber[8]" = "5"
+
+
+ # USB 2.0 enable ports 1-8, disable ports 9-12
+ register "usb2_ports[0]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port
+ register "usb2_ports[1]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port
+ register "usb2_ports[2]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port
+ register "usb2_ports[3]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port
+ register "usb2_ports[4]" = "USB2_PORT_SHORT(OC_SKIP)" # Type-A Port
+ register "usb2_ports[5]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port
+ register "usb2_ports[6]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port
+ register "usb2_ports[7]" = "USB2_PORT_SHORT(OC_SKIP)" # mPCIe slot
+
+ # USB 3.0 enable ports 1-4, disable ports 5-6
+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port
+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port
+ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port
+ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port
+
+ register "SerialIoDevMode" = "{ \
+ [PchSerialIoIndexI2C0] = PchSerialIoDisabled, \
+ [PchSerialIoIndexI2C1] = PchSerialIoDisabled, \
+ [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \
+ [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \
+ [PchSerialIoIndexI2C4] = PchSerialIoDisabled, \
+ [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \
+ [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \
+ [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \
+ [PchSerialIoIndexUart0] = PchSerialIoDisabled, \
+ [PchSerialIoIndexUart1] = PchSerialIoDisabled, \
+ [PchSerialIoIndexUart2] = PchSerialIoDisabled, \
+ }"
+
+ # Lock Down CHIPSET_LOCKDOWN_COREBOOT
+ register "common_soc_config" = "{
+ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+ }"
+
+ device cpu_cluster 0 on
+ device lapic 0 on end
+ end
+ device domain 0 on
+ device pci 00.0 on end # 8086 5914 - Host Bridge
+ device pci 02.0 on end # 8086 5917 - Integrated Graphics Device
+ device pci 04.0 off end # 8086 ???? - SA thermal subsystem
+ device pci 05.0 off end # 8086 ???? - SA IMGU
+ device pci 08.0 off end # 8086 ???? - Gaussian Mixture Model
+ device pci 13.0 off end # 8086 9d35 - Integrated Sensor Hub
+ device pci 14.0 on end # 8086 9d2f - USB xHCI
+ device pci 14.1 off end # 8086 9d30 - USB xDCI (OTG)
+ device pci 14.2 off end # 8086 9d31 - Thermal Subsystem
+ device pci 14.3 off end # 8086 9d32 - Camera I/O Host Controller
+ device pci 15.0 off end # 8086 9d60 - I2C #0
+ device pci 15.1 off end # 8086 9d61 - I2C #1
+ device pci 15.2 off end # 8086 9d62 - I2C #2
+ device pci 15.3 off end # 8086 9d63 - I2C #3
+ device pci 16.0 on end # 8086 9d3a - Management Engine Interface 1
+ device pci 16.1 off end # 8086 9d3b - Management Engine Interface 2
+ device pci 16.2 off end # 8086 9d3c - Management Engine IDE-Redirection
+ device pci 16.3 off end # 8086 9d3d - Management Engine KT Redirection
+ device pci 16.4 off end # 8086 9d3e - Management Engine Interface 3
+ device pci 17.0 on end # 8086 9d03 - SATA
+ device pci 19.0 off end # 8086 9d66 - UART #2
+ device pci 19.1 off end # 8086 9d65 - I2C #5
+ device pci 19.2 off end # 8086 9d64 - I2C #4
+ device pci 1c.0 on end # 8086 9d10 - PCI Express Port 1
+ device pci 1c.1 on end # 8086 9d11 - PCI Express Port 2
+ device pci 1c.2 on end # 8086 9d12 - PCI Express Port 3
+ device pci 1c.3 on end # 8086 9d13 - PCI Express Port 4
+ device pci 1c.4 on end # 8086 9d14 - PCI Express Port 5
+ device pci 1c.5 on end # 8086 9d15 - PCI Express Port 6
+ device pci 1c.6 off end # 8086 9d16 - PCI Express Port 7
+ device pci 1c.7 off end # 8086 9d17 - PCI Express Port 8
+ device pci 1d.0 on # 8086 9d18 - PCI Express Port 9 - WiFi
+ smbios_slot_desc
+ "SlotTypePciExpressMini52pinWithoutBSKO"
+ "SlotLengthShort" "WIFI1" "SlotDataBusWidth1X"
+ end
+ device pci 1d.1 off end # 8086 9d19 - PCI Express Port 10
+ device pci 1d.2 off end # 8086 9d1a - PCI Express Port 11
+ device pci 1d.3 off end # 8086 9d1b - PCI Express Port 12
+ device pci 1e.0 off end # 8086 9d27 - UART #0
+ device pci 1e.1 off end # 8086 9d28 - UART #1
+ device pci 1e.2 off end # 8086 9d29 - GSPI #0
+ device pci 1e.3 off end # 8086 9d2a - GSPI #1
+ device pci 1e.4 off end # 8086 9d2b - eMMC
+ device pci 1e.5 off end # 8086 ???? - SDIO
+ device pci 1e.6 off end # 8086 9d2d = SDXC
+ device pci 1f.0 on # 8086 9d4e - LPC Controller
+ chip superio/ite/it8613e
+ device pnp 2e.0 off end
+ device pnp 2e.1 on # COM 1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.4 off end # Environment Controller
+ device pnp 2e.5 off end # Keyboard
+ device pnp 2e.6 off end # Mouse
+ device pnp 2e.7 off end # GPIO
+ device pnp 2e.a off end # CIR
+ end
+ end # LPC Interface
+ device pci 1f.1 on end # 8086 9d20 - P2SB
+ device pci 1f.2 on end # 8086 9d21 - Power Management Controller
+ device pci 1f.3 off end # 8086 9d71 - Intel HDA
+ device pci 1f.4 on end # 8086 9d23 - SMBus
+ device pci 1f.5 off end # 8086 9d24 - PCH SPI
+ device pci 1f.6 off end # 8086 9d25 - GbE
+ end
+ chip drivers/crb
+ device mmio 0xfed40000 on end
+ end
+end
diff --git a/src/mainboard/yanling/yl_kbr6l/dsdt.asl b/src/mainboard/yanling/yl_kbr6l/dsdt.asl
new file mode 100644
index 0000000..3de4e26
--- /dev/null
+++ b/src/mainboard/yanling/yl_kbr6l/dsdt.asl
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <acpi/acpi.h>
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ ACPI_DSDT_REV_2,
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x20110725 /* OEM revision */
+)
+{
+ #include <soc/intel/common/block/acpi/acpi/platform.asl>
+ #include <soc/intel/skylake/acpi/globalnvs.asl>
+ #include <cpu/intel/common/acpi/cpu.asl>
+
+ Device (\_SB.PCI0)
+ {
+ #include <soc/intel/skylake/acpi/systemagent.asl>
+ #include <soc/intel/skylake/acpi/pch.asl>
+ }
+
+ #include <southbridge/intel/common/acpi/sleepstates.asl>
+}
diff --git a/src/mainboard/yanling/yl_kbr6l/gma-mainboard.ads b/src/mainboard/yanling/yl_kbr6l/gma-mainboard.ads
new file mode 100644
index 0000000..0e0f4f8
--- /dev/null
+++ b/src/mainboard/yanling/yl_kbr6l/gma-mainboard.ads
@@ -0,0 +1,15 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+ ports : constant Port_List :=
+ (HDMI1,
+ others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/yanling/yl_kbr6l/gpio.h b/src/mainboard/yanling/yl_kbr6l/gpio.h
new file mode 100644
index 0000000..7ec5a8a
--- /dev/null
+++ b/src/mainboard/yanling/yl_kbr6l/gpio.h
@@ -0,0 +1,179 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef _GPIOFW6B_H
+#define _GPIOFW6B_H
+
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+
+#ifndef __ACPI__
+
+/* Pad configuration in ramstage. */
+static const struct pad_config gpio_table[] = {
+/* RCIN# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
+/* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1),
+/* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1),
+/* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1),
+/* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1),
+/* LPC_FRAME */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
+/* LPC_SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
+/* PIRQA_N*/ PAD_CFG_TERM_GPO(GPP_A7, 1, NONE, DEEP),
+/* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
+/* PCH_LPC_CLK0 */ PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1),
+/* PCH_LPC_CLK1 */ PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1),
+/* PME# */ PAD_CFG_NF(GPP_A11, UP_20K, DEEP, NF1),
+/* ISH_GP6 */ PAD_NC(GPP_A12, NONE),
+/* PCH_SUSPWRACB */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
+/* PCH_SUSSTAT */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
+/* PCH_SUSACK */ PAD_CFG_NF(GPP_A15, DN_20K, DEEP, NF1),
+/* SD_1P8_SEL */ PAD_NC(GPP_A16, NONE),
+/* SD_PWR_EN */ PAD_NC(GPP_A17, NONE),
+/* ISH_GP0 */ PAD_NC(GPP_A18, NONE),
+/* ISH_GP1 */ PAD_NC(GPP_A19, NONE),
+/* ISH_GP2 */ PAD_NC(GPP_A20, NONE),
+/* ISH_GP3 */ PAD_NC(GPP_A21, NONE),
+/* ISH_GP4 */ PAD_NC(GPP_A22, NONE),
+/* ISH_GP5 */ PAD_NC(GPP_A23, NONE),
+/* CORE_VID0 */ PAD_NC(GPP_B0, NONE),
+/* CORE_VID1 */ PAD_NC(GPP_B1, NONE),
+/* VRALERT_N */ PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1),
+/* CPU_GP2 */ PAD_NC(GPP_B3, NONE),
+/* CPU_GP3 */ PAD_NC(GPP_B4, NONE),
+/* SRCCLKREQ0_N */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
+/* SRCCLKREQ1_N*/ PAD_NC(GPP_B6, NONE),
+/* SRCCLKREQ2_N*/ PAD_NC(GPP_B7, NONE),
+/* SRCCLKREQ3_N*/ PAD_NC(GPP_B8, NONE),
+/* SRCCLKREQ4_N*/ PAD_NC(GPP_B9, NONE),
+/* SRCCLKREQ5_N*/ PAD_NC(GPP_B10, NONE),
+/* EXT_PWR_GATE_N */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
+/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+/* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
+/* SPKR */ PAD_CFG_NF(GPP_B14, DN_20K, PLTRST, NF1),
+/* GSPI0_CS_N */ PAD_NC(GPP_B15, NONE),
+/* GSPI0_CLK */ PAD_NC(GPP_B16, NONE),
+/* GSPI0_MISO */ PAD_NC(GPP_B17, NONE),
+/* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE),
+/* GSPI1_CS_N */ PAD_NC(GPP_B19, NONE),
+/* GSPI1_CLK */ PAD_NC(GPP_B20, NONE),
+/* GSPI1_MISO */ PAD_NC(GPP_B21, NONE),
+/* GSPI1_MOSI */ PAD_NC(GPP_B22, NONE),
+/* SM1ALERT# */ PAD_NC(GPP_B23, NONE),
+/* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
+/* SMB_DATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
+/* SMBALERT# */ PAD_CFG_NF(GPP_C2, NONE, DEEP, NF1),
+/* SML0_CLK */ PAD_NC(GPP_C3, NONE),
+/* SML0DATA */ PAD_NC(GPP_C4, NONE),
+/* SML0ALERT# */ PAD_NC(GPP_C5, NONE),
+/* UART0_RXD */ PAD_NC(GPP_C8, NONE),
+/* UART0_TXD */ PAD_NC(GPP_C9, NONE),
+/* UART0_CTS_N */ PAD_NC(GPP_C10, NONE),
+/* UART0_RTS_N */ PAD_NC(GPP_C11, NONE),
+/* UART1_RXD */ PAD_NC(GPP_C12, NONE),
+/* UART1_TXD */ PAD_NC(GPP_C13, NONE),
+/* UART1_CTS_N */ PAD_NC(GPP_C14, NONE),
+/* UART1_RTS_N */ PAD_NC(GPP_C15, NONE),
+/* I2C0_SDA */ PAD_NC(GPP_C16, NONE),
+/* I2C0_SCL */ PAD_NC(GPP_C17, NONE),
+/* I2C1_SDA */ PAD_NC(GPP_C18, NONE),
+/* I2C1_SCL */ PAD_NC(GPP_C19, NONE),
+/* UART2_RXD */ PAD_NC(GPP_C20, NONE),
+/* UART2_TXD */ PAD_NC(GPP_C21, NONE),
+/* UART2_CTS_N */ PAD_NC(GPP_C22, NONE),
+/* UART2_RTS_N */ PAD_NC(GPP_C23, NONE),
+/* ITCH_SPI_CS */ PAD_NC(GPP_D0, NONE),
+/* ITCH_SPI_CLK */ PAD_NC(GPP_D1, NONE),
+/* ITCH_SPI_MISO_1 */ PAD_NC(GPP_D2, NONE),
+/* ITCH_SPI_MISO_0 */ PAD_NC(GPP_D3, NONE),
+/* FLASHTRIG */ PAD_NC(GPP_D4, NONE),
+/* ISH_I2C0_SDA */ PAD_NC(GPP_D5, NONE),
+/* ISH_I2C0_SCL */ PAD_NC(GPP_D6, NONE),
+/* ISH_I2C1_SDA */ PAD_NC(GPP_D7, NONE),
+/* ISH_I2C1_SCL */ PAD_NC(GPP_D8, NONE),
+/* GPP_D9 */ PAD_NC(GPP_D9, NONE),
+/* GPP_D10 */ PAD_NC(GPP_D10, NONE),
+/* GPP_D11 */ PAD_NC(GPP_D11, NONE),
+/* GPP_D12 */ PAD_NC(GPP_D12, NONE),
+/* ISH_UART0_RXD */ PAD_NC(GPP_D13, NONE),
+/* ISH_UART0_TXD */ PAD_NC(GPP_D14, NONE),
+/* ISH_UART0_RTS */ PAD_NC(GPP_D15, NONE),
+/* ISH_UART0_CTS */ PAD_NC(GPP_D16, NONE),
+/* DMIC_CLK_1 */ PAD_NC(GPP_D17, NONE),
+/* DMIC_DATA_1 */ PAD_NC(GPP_D18, NONE),
+/* DMIC_CLK_0 */ PAD_NC(GPP_D19, NONE),
+/* DMIC_DATA_0 */ PAD_NC(GPP_D20, NONE),
+/* ITCH_SPI_D2 */ PAD_NC(GPP_D21, NONE),
+/* ITCH_SPI_D3 */ PAD_NC(GPP_D22, NONE),
+/* I2S_MCLK */ PAD_NC(GPP_D23, NONE),
+/* SATAXPCIE0 (TP8) */ PAD_NC(GPP_E0, NONE),
+/* SATAXPCIE1 (TP9)*/ PAD_NC(GPP_E1, NONE),
+/* SATAXPCIE2 (TP10) */ PAD_NC(GPP_E2, NONE),
+/* CPU_GP0 */ PAD_NC(GPP_E3, NONE),
+/* SATA_DEVSLP0 */ PAD_NC(GPP_E4, NONE),
+/* SATA_DEVSLP1 */ PAD_NC(GPP_E5, NONE),
+/* SATA_DEVSLP2 */ PAD_NC(GPP_E6, NONE),
+/* CPU_GP1 */ PAD_NC(GPP_E7, NONE),
+/* SATA_LED */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
+/* USB2_OC_0 */ PAD_NC(GPP_E9, NONE),
+/* USB2_OC_1 */ PAD_NC(GPP_E10, NONE),
+/* USB2_OC_2 */ PAD_NC(GPP_E11, NONE),
+/* USB2_OC_3 */ PAD_NC(GPP_E12, NONE),
+/* DDI1_HPD */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
+/* DDI2_HPD */ PAD_NC(GPP_E14, NONE),
+/* DDI3_HPD */ PAD_NC(GPP_E15, NONE),
+/* DDI4_HPD */ PAD_NC(GPP_E16, NONE),
+/* EDP_HPD */ PAD_NC(GPP_E17, NONE),
+/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
+/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF1),
+/* DDPC_CTRLCLK */ PAD_NC(GPP_E20, NONE),
+/* DDPC_CTRLDATA */ PAD_NC(GPP_E21, NONE),
+/* DDPD_CTRLCLK */ PAD_NC(GPP_E22, NONE),
+/* DDPD_CTRLDATA */ PAD_NC(GPP_E23, NONE),
+/* I2S2_SCLK */ PAD_NC(GPP_F0, NONE),
+/* I2S2_SFRM */ PAD_NC(GPP_F1, NONE),
+/* I2S2_TXD */ PAD_NC(GPP_F2, NONE),
+/* I2S2_RXD */ PAD_NC(GPP_F3, NONE),
+/* I2C2_SDA */ PAD_NC(GPP_F4, NONE),
+/* I2C2_SCL */ PAD_NC(GPP_F5, NONE),
+/* I2C3_SDA */ PAD_NC(GPP_F6, NONE),
+/* I2C3_SCL */ PAD_NC(GPP_F7, NONE),
+/* I2C4_SDA */ PAD_NC(GPP_F8, NONE),
+/* I2C4_SDA */ PAD_NC(GPP_F9, NONE),
+/* I2C5_SDA */ PAD_NC(GPP_F10, NONE),
+/* I2C5_SCL */ PAD_NC(GPP_F11, NONE),
+/* EMMC_CMD */ PAD_NC(GPP_F12, NONE),
+/* EMMC_DATA0 */ PAD_NC(GPP_F13, NONE),
+/* EMMC_DATA1 */ PAD_NC(GPP_F14, NONE),
+/* EMMC_DATA2 */ PAD_NC(GPP_F15, NONE),
+/* EMMC_DATA3 */ PAD_NC(GPP_F16, NONE),
+/* EMMC_DATA4 */ PAD_NC(GPP_F17, NONE),
+/* EMMC_DATA5 */ PAD_NC(GPP_F18, NONE),
+/* EMMC_DATA6 */ PAD_NC(GPP_F19, NONE),
+/* EMMC_DATA7 */ PAD_NC(GPP_F20, NONE),
+/* EMMC_RCLK */ PAD_NC(GPP_F21, NONE),
+/* EMMC_CLK */ PAD_NC(GPP_F22, NONE),
+/* GPP_F23 */ PAD_NC(GPP_F23, NONE),
+/* SD_CMD */ PAD_NC(GPP_G0, NONE),
+/* SD_DATA0 */ PAD_NC(GPP_G1, NONE),
+/* SD_DATA1 */ PAD_NC(GPP_G2, NONE),
+/* SD_DATA2 */ PAD_NC(GPP_G3, NONE),
+/* SD_DATA3 */ PAD_NC(GPP_G4, NONE),
+/* SD_CD# */ PAD_NC(GPP_G5, NONE),
+/* SD_CLK */ PAD_NC(GPP_G6, NONE),
+/* SD_WP */ PAD_NC(GPP_G7, NONE),
+/* PCH_BATLOW */ PAD_NC(GPD0, NONE),
+/* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
+/* LAN_WAKE_N */ PAD_NC(GPD2, NONE),
+/* PWRBTN */ PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),
+/* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
+/* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
+/* PM_SLP_SA# (TP7) */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
+/* GPD7_RSVD */ PAD_CFG_TERM_GPO(GPD7, 1, NONE, DEEP),
+/* PM_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
+/* SLP_WLAN# (TP6) */ PAD_NC(GPD9, NONE),
+/* SLP_S5# (TP3) */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
+/* LANPHYC */ PAD_NC(GPD11, NONE),
+};
+
+#endif
+
+#endif
diff --git a/src/mainboard/yanling/yl_kbr6l/ramstage.c b/src/mainboard/yanling/yl_kbr6l/ramstage.c
new file mode 100644
index 0000000..9518b1d
--- /dev/null
+++ b/src/mainboard/yanling/yl_kbr6l/ramstage.c
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <soc/ramstage.h>
+
+#include "gpio.h"
+
+void mainboard_silicon_init_params(FSP_SIL_UPD *params)
+{
+ /*
+ * Configure pads prior to SiliconInit() in case there's any
+ * dependencies during hardware initialization.
+ */
+ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+
+ params->TurboMode = 1;
+ params->PchPort61hEnable = 1;
+ params->CdClock = 3;
+}
diff --git a/src/mainboard/yanling/yl_kbr6l/romstage.c b/src/mainboard/yanling/yl_kbr6l/romstage.c
new file mode 100644
index 0000000..2b68e1a
--- /dev/null
+++ b/src/mainboard/yanling/yl_kbr6l/romstage.c
@@ -0,0 +1,65 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <fsp/api.h>
+#include <soc/romstage.h>
+#include <spd_bin.h>
+#include <string.h>
+
+static void mainboard_fill_dq_map_data(void *dq_map_ch0, void *dq_map_ch1)
+{
+ const u8 dq_map[2][12] = {
+ { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0,
+ 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 },
+ { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC,
+ 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } };
+ memcpy(dq_map_ch0, dq_map[0], sizeof(dq_map[0]));
+ memcpy(dq_map_ch1, dq_map[1], sizeof(dq_map[1]));
+}
+
+static void mainboard_fill_dqs_map_data(void *dqs_map_ch0, void *dqs_map_ch1)
+{
+ const u8 dqs_map[2][8] = {
+ { 0, 1, 2, 3, 4, 5, 6, 7 },
+ { 1, 0, 2, 3, 4, 5, 6, 7 } };
+ memcpy(dqs_map_ch0, dqs_map[0], sizeof(dqs_map[0]));
+ memcpy(dqs_map_ch1, dqs_map[1], sizeof(dqs_map[1]));
+}
+
+static void mainboard_fill_rcomp_res_data(void *rcomp_ptr)
+{
+ const u16 RcompResistor[3] = { 121, 81, 100 };
+ memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor));
+}
+
+static void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr)
+{
+ static const u16 RcompTarget[5] = { 100, 40, 20, 20, 26 };
+ memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget));
+}
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+ FSP_M_CONFIG *mem_cfg;
+ mem_cfg = &mupd->FspmConfig;
+
+ mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0,
+ &mem_cfg->DqByteMapCh1);
+ mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0,
+ &mem_cfg->DqsMapCpu2DramCh1);
+ mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor);
+ mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget);
+
+ struct spd_block blk = {
+ .addr_map = { 0x50, 0x52, },
+ };
+
+ mem_cfg->DqPinsInterleaved = 1;
+ mem_cfg->CaVrefConfig = 2;
+
+ get_spd_smbus(&blk);
+ dump_spd_info(&blk);
+
+ mem_cfg->MemorySpdDataLen = blk.len;
+ mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0];
+ mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1];
+}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Icbc18914670f87f0943b371400c509ff0eeacf6a
Gerrit-Change-Number: 48769
Gerrit-PatchSet: 1
Gerrit-Owner: Thomas
Gerrit-MessageType: newchange
4
10
Change in coreboot[master]: util/amdfwtool: clean up Makefile, Makefile.inc
by Idwer Vollering (Code Review) 07 Aug '23
by Idwer Vollering (Code Review) 07 Aug '23
07 Aug '23
Idwer Vollering has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49086 )
Change subject: util/amdfwtool: clean up Makefile, Makefile.inc
......................................................................
util/amdfwtool: clean up Makefile, Makefile.inc
Signed-off-by: Idwer Vollering <vidwer(a)gmail.com>
Change-Id: Ia16af046acdc68c176b1c4ff434518a5f8f8bf9e
---
M util/amdfwtool/Makefile
M util/amdfwtool/Makefile.inc
2 files changed, 2 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/49086/1
diff --git a/util/amdfwtool/Makefile b/util/amdfwtool/Makefile
index 58606e3..00e6d59 100644
--- a/util/amdfwtool/Makefile
+++ b/util/amdfwtool/Makefile
@@ -9,7 +9,7 @@
$(TARGET): $(OBJ)
- $(CC) $(OBJ) $(LDFLAGS) -o $@
+ $(CC) $(OBJ) -o $@
%.o: %.c $(HEADER)
$(CC) $(CFLAGS) -c -o $@ $<
diff --git a/util/amdfwtool/Makefile.inc b/util/amdfwtool/Makefile.inc
index e794ed9..06a17f3 100644
--- a/util/amdfwtool/Makefile.inc
+++ b/util/amdfwtool/Makefile.inc
@@ -2,10 +2,8 @@
amdfwtoolobj = amdfwtool.o data_parse.o
-AMDFWTOOLCFLAGS=-O2 -Wall -Wextra -Wshadow
-
$(objutil)/amdfwtool/%.o: $(top)/util/amdfwtool/%.c # $(HEADER)
- $(HOSTCC) $(AMDFWTOOLCFLAGS) $(HOSTCFLAGS) -c -o $@ $<
+ $(HOSTCC) $(CFLAGS) -c -o $@ $<
$(objutil)/amdfwtool/amdfwtool: $(addprefix $(objutil)/amdfwtool/,$(amdfwtoolobj))
printf " AMDFWTOOL\n"
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ia16af046acdc68c176b1c4ff434518a5f8f8bf9e
Gerrit-Change-Number: 49086
Gerrit-PatchSet: 1
Gerrit-Owner: Idwer Vollering <vidwer(a)gmail.com>
Gerrit-MessageType: newchange
5
4
Change in coreboot[master]: sb/intel/bd82x6x/pch.c: Extract common functions
by Angel Pons (Code Review) 07 Aug '23
by Angel Pons (Code Review) 07 Aug '23
07 Aug '23
Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49167 )
Change subject: sb/intel/bd82x6x/pch.c: Extract common functions
......................................................................
sb/intel/bd82x6x/pch.c: Extract common functions
PCH identification functions and `pch_iobp_update` are used in multiple
stages. Move them out of `pch.c` to drop some ugly preprocessor usage.
Subsequent commits will use `pch_iobp_update` in romstage as well.
Change-Id: I8d33338a4f74fd03c8f99f8fcece99b63c28adab
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
---
M src/southbridge/intel/bd82x6x/Makefile.inc
A src/southbridge/intel/bd82x6x/common.c
M src/southbridge/intel/bd82x6x/pch.c
M src/southbridge/intel/bd82x6x/pch.h
4 files changed, 122 insertions(+), 119 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/49167/1
diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc
index 687fc97..469a50e 100644
--- a/src/southbridge/intel/bd82x6x/Makefile.inc
+++ b/src/southbridge/intel/bd82x6x/Makefile.inc
@@ -7,6 +7,7 @@
ramstage-y += pch.c
ramstage-y += azalia.c
+ramstage-y += common.c
ramstage-y += fadt.c
ramstage-y += lpc.c
ramstage-y += pci.c
@@ -26,8 +27,9 @@
ramstage-$(CONFIG_ELOG) += elog.c
-smm-y += smihandler.c me.c me_8.x.c pch.c me_common.c
+smm-y += common.c smihandler.c me.c me_8.x.c me_common.c
+romstage-y += common.c
romstage-y += me_status.c
romstage-y += early_rcba.c
romstage-y += early_pch.c
diff --git a/src/southbridge/intel/bd82x6x/common.c b/src/southbridge/intel/bd82x6x/common.c
new file mode 100644
index 0000000..7480174
--- /dev/null
+++ b/src/southbridge/intel/bd82x6x/common.c
@@ -0,0 +1,118 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#define __SIMPLE_DEVICE__
+
+#include <console/console.h>
+#include <delay.h>
+#include <device/pci.h>
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
+#include <stdint.h>
+
+#include "pch.h"
+
+int pch_silicon_revision(void)
+{
+ static int pch_revision_id = -1;
+
+ if (pch_revision_id < 0)
+ pch_revision_id = pci_read_config8(PCH_LPC_DEV, PCI_REVISION_ID);
+
+ return pch_revision_id;
+}
+
+int pch_silicon_type(void)
+{
+ static int pch_type = -1;
+
+ if (pch_type < 0)
+ pch_type = pci_read_config8(PCH_LPC_DEV, PCI_DEVICE_ID + 1);
+
+ return pch_type;
+}
+
+int pch_silicon_supported(int type, int rev)
+{
+ int cur_type = pch_silicon_type();
+ int cur_rev = pch_silicon_revision();
+
+ switch (type) {
+ case PCH_TYPE_CPT:
+ /* CougarPoint minimum revision */
+ if (cur_type == PCH_TYPE_CPT && cur_rev >= rev)
+ return 1;
+ /* PantherPoint any revision */
+ if (cur_type == PCH_TYPE_PPT)
+ return 1;
+ break;
+
+ case PCH_TYPE_PPT:
+ /* PantherPoint minimum revision */
+ if (cur_type == PCH_TYPE_PPT && cur_rev >= rev)
+ return 1;
+ break;
+ }
+
+ return 0;
+}
+
+#define IOBP_RETRY 1000
+static inline int iobp_poll(void)
+{
+ unsigned int try = IOBP_RETRY;
+ u32 data;
+
+ while (try--) {
+ data = RCBA32(IOBPS);
+ if ((data & 1) == 0)
+ return 1;
+ udelay(10);
+ }
+
+ printk(BIOS_ERR, "IOBP timeout\n");
+ return 0;
+}
+
+void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue)
+{
+ u32 data;
+
+ /* Set the address */
+ RCBA32(IOBPIRI) = address;
+
+ /* READ OPCODE */
+ if (pch_silicon_supported(PCH_TYPE_CPT, PCH_STEP_B0))
+ RCBA32(IOBPS) = IOBPS_RW_BX;
+ else
+ RCBA32(IOBPS) = IOBPS_READ_AX;
+ if (!iobp_poll())
+ return;
+
+ /* Read IOBP data */
+ data = RCBA32(IOBPD);
+ if (!iobp_poll())
+ return;
+
+ /* Check for successful transaction */
+ if ((RCBA32(IOBPS) & 0x6) != 0) {
+ printk(BIOS_ERR, "IOBP read 0x%08x failed\n", address);
+ return;
+ }
+
+ /* Update the data */
+ data &= andvalue;
+ data |= orvalue;
+
+ /* WRITE OPCODE */
+ if (pch_silicon_supported(PCH_TYPE_CPT, PCH_STEP_B0))
+ RCBA32(IOBPS) = IOBPS_RW_BX;
+ else
+ RCBA32(IOBPS) = IOBPS_WRITE_AX;
+ if (!iobp_poll())
+ return;
+
+ /* Write IOBP data */
+ RCBA32(IOBPD) = data;
+ if (!iobp_poll())
+ return;
+}
diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c
index 82b95f6..1c8786d 100644
--- a/src/southbridge/intel/bd82x6x/pch.c
+++ b/src/southbridge/intel/bd82x6x/pch.c
@@ -11,123 +11,6 @@
#include "chip.h"
#include "pch.h"
-int pch_silicon_revision(void)
-{
- static int pch_revision_id = -1;
-
-#ifdef __SIMPLE_DEVICE__
- pci_devfn_t dev = PCI_DEV(0, 0x1f, 0);
-#else
- struct device *dev = pcidev_on_root(0x1f, 0);
-#endif
-
- if (pch_revision_id < 0)
- pch_revision_id = pci_read_config8(dev, PCI_REVISION_ID);
- return pch_revision_id;
-}
-
-int pch_silicon_type(void)
-{
- static int pch_type = -1;
-
-#ifdef __SIMPLE_DEVICE__
- pci_devfn_t dev = PCI_DEV(0, 0x1f, 0);
-#else
- struct device *dev = pcidev_on_root(0x1f, 0);
-#endif
-
- if (pch_type < 0)
- pch_type = pci_read_config8(dev, PCI_DEVICE_ID + 1);
- return pch_type;
-}
-
-static int pch_silicon_supported(int type, int rev)
-{
- int cur_type = pch_silicon_type();
- int cur_rev = pch_silicon_revision();
-
- switch (type) {
- case PCH_TYPE_CPT:
- /* CougarPoint minimum revision */
- if (cur_type == PCH_TYPE_CPT && cur_rev >= rev)
- return 1;
- /* PantherPoint any revision */
- if (cur_type == PCH_TYPE_PPT)
- return 1;
- break;
-
- case PCH_TYPE_PPT:
- /* PantherPoint minimum revision */
- if (cur_type == PCH_TYPE_PPT && cur_rev >= rev)
- return 1;
- break;
- }
-
- return 0;
-}
-
-#define IOBP_RETRY 1000
-static inline int iobp_poll(void)
-{
- unsigned int try = IOBP_RETRY;
- u32 data;
-
- while (try--) {
- data = RCBA32(IOBPS);
- if ((data & 1) == 0)
- return 1;
- udelay(10);
- }
-
- printk(BIOS_ERR, "IOBP timeout\n");
- return 0;
-}
-
-void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue)
-{
- u32 data;
-
- /* Set the address */
- RCBA32(IOBPIRI) = address;
-
- /* READ OPCODE */
- if (pch_silicon_supported(PCH_TYPE_CPT, PCH_STEP_B0))
- RCBA32(IOBPS) = IOBPS_RW_BX;
- else
- RCBA32(IOBPS) = IOBPS_READ_AX;
- if (!iobp_poll())
- return;
-
- /* Read IOBP data */
- data = RCBA32(IOBPD);
- if (!iobp_poll())
- return;
-
- /* Check for successful transaction */
- if ((RCBA32(IOBPS) & 0x6) != 0) {
- printk(BIOS_ERR, "IOBP read 0x%08x failed\n", address);
- return;
- }
-
- /* Update the data */
- data &= andvalue;
- data |= orvalue;
-
- /* WRITE OPCODE */
- if (pch_silicon_supported(PCH_TYPE_CPT, PCH_STEP_B0))
- RCBA32(IOBPS) = IOBPS_RW_BX;
- else
- RCBA32(IOBPS) = IOBPS_WRITE_AX;
- if (!iobp_poll())
- return;
-
- /* Write IOBP data */
- RCBA32(IOBPD) = data;
- if (!iobp_poll())
- return;
-}
-
-#ifndef __SIMPLE_DEVICE__
/* Set bit in function disable register to hide this device */
static void pch_hide_devfn(unsigned int devfn)
{
@@ -426,4 +309,3 @@
CHIP_NAME("Intel Series 6/7 (Cougar Point/Panther Point) Southbridge")
.enable_dev = pch_enable,
};
-#endif
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index 1840a2b..dcab839 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -42,6 +42,7 @@
int pch_silicon_revision(void);
int pch_silicon_type(void);
+int pch_silicon_supported(int type, int rev);
void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
void enable_usb_bar(void);
--
To view, visit https://review.coreboot.org/c/coreboot/+/49167
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I8d33338a4f74fd03c8f99f8fcece99b63c28adab
Gerrit-Change-Number: 49167
Gerrit-PatchSet: 1
Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-MessageType: newchange
3
3
Change in coreboot[master]: [WIP]device/Kconfig: Introduce separate graphics menu for Intel
by Patrick Rudolph (Code Review) 07 Aug '23
by Patrick Rudolph (Code Review) 07 Aug '23
07 Aug '23
Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49176 )
Change subject: [WIP]device/Kconfig: Introduce separate graphics menu for Intel
......................................................................
[WIP]device/Kconfig: Introduce separate graphics menu for Intel
Allows to select an Intel graphics driver and a "generic" graphics driver.
TODO: Split it into even more chunks.
Change-Id: I410fecfdb8a99ca520b2c05edd9ed2558d7e0a92
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M payloads/external/SeaBIOS/Kconfig
M src/device/Kconfig
M src/device/pci_device.c
M src/device/pci_rom.c
M src/drivers/intel/gma/Makefile.inc
M src/drivers/intel/gma/int15.h
M src/mainboard/bostentech/gbyt4/mainboard.c
M src/mainboard/google/link/mainboard.c
M src/mainboard/google/rambi/mainboard.c
M src/mainboard/kontron/ktqm77/mainboard.c
M src/northbridge/intel/i945/Kconfig
M src/northbridge/intel/i945/gma.c
M src/northbridge/intel/pineview/Kconfig
M src/northbridge/intel/pineview/gma.c
M src/soc/intel/common/block/timer/Kconfig
15 files changed, 83 insertions(+), 42 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/49176/1
diff --git a/payloads/external/SeaBIOS/Kconfig b/payloads/external/SeaBIOS/Kconfig
index 9aea2d0..6399116 100644
--- a/payloads/external/SeaBIOS/Kconfig
+++ b/payloads/external/SeaBIOS/Kconfig
@@ -64,7 +64,7 @@
config SEABIOS_VGA_COREBOOT
prompt "Include generated option rom that implements legacy VGA BIOS compatibility"
default y if !VENDOR_EMULATION
- depends on !VGA_ROM_RUN && (VGA_TEXT_FRAMEBUFFER || LINEAR_FRAMEBUFFER)
+ depends on !(VGA_ROM_RUN || VGA_ROM_RUN_INTEL) && (VGA_TEXT_FRAMEBUFFER || LINEAR_FRAMEBUFFER)
bool
help
coreboot can initialize the GPU of some mainboards.
diff --git a/src/device/Kconfig b/src/device/Kconfig
index baa7110..6df9c17 100644
--- a/src/device/Kconfig
+++ b/src/device/Kconfig
@@ -71,8 +71,6 @@
default NO_GFX_INIT if VGA_BIOS && PAYLOAD_SEABIOS
default VGA_ROM_RUN if VGA_BIOS
default MAINBOARD_DO_NATIVE_VGA_INIT
- default MAINBOARD_USE_LIBGFXINIT
- default RUN_FSP_GOP if INTEL_GMA_HAVE_VBT
config MAINBOARD_DO_NATIVE_VGA_INIT
bool "Use native graphics init"
@@ -82,16 +80,6 @@
display without the need of a binary only VGA OPROM. Enabling this
option may be faster, but also lacks flexibility in setting modes.
-config MAINBOARD_USE_LIBGFXINIT
- bool "Use libgfxinit"
- depends on MAINBOARD_HAS_LIBGFXINIT
- select HAVE_VGA_TEXT_FRAMEBUFFER
- select HAVE_LINEAR_FRAMEBUFFER
- select VGA if VGA_TEXT_FRAMEBUFFER
- help
- Use the SPARK library `libgfxinit` for the native graphics
- initialization. This requires an Ada toolchain.
-
# TODO: Explain differences (if any) for onboard cards.
config VGA_ROM_RUN
bool "Run VGA Option ROMs"
@@ -106,6 +94,56 @@
more complete BIOS interrupt services available than coreboot,
which some option ROMs require in order to function correctly.
+config NO_GFX_INIT
+ bool "None"
+ depends on !MAINBOARD_FORCE_NATIVE_VGA_INIT
+ help
+ Select this to not perform any graphics initialization in
+ coreboot. This is useful if the payload (e.g. SeaBIOS) can
+ initialize graphics or if pre-boot graphics are not required.
+
+endchoice
+
+choice
+ prompt "Intel Integrated Graphics initialization"
+ default NO_INTEL_GFX_INIT if VGA_BIOS && PAYLOAD_SEABIOS
+ default VGA_ROM_RUN_INTEL if VGA_BIOS
+ default MAINBOARD_DO_NATIVE_INTEL_VGA_INIT
+ default MAINBOARD_USE_LIBGFXINIT
+ default RUN_FSP_GOP if INTEL_GMA_HAVE_VBT
+
+config MAINBOARD_DO_NATIVE_INTEL_VGA_INIT
+ bool "Use native graphics init"
+ depends on MAINBOARD_HAS_NATIVE_INTEL_VGA_INIT
+ help
+ Some mainboards, such as the Asus P5gc, allow initializing the
+ display without the need of a binary only VGA OPROM. Enabling this
+ option may be faster, but also lacks flexibility in setting modes
+ in the payload or legacy OS.
+
+config MAINBOARD_USE_LIBGFXINIT
+ bool "Use libgfxinit"
+ depends on MAINBOARD_HAS_LIBGFXINIT
+ select HAVE_VGA_TEXT_FRAMEBUFFER
+ select HAVE_LINEAR_FRAMEBUFFER
+ select VGA if VGA_TEXT_FRAMEBUFFER
+ help
+ Use the SPARK library `libgfxinit` for the native graphics
+ initialization. This requires an Ada toolchain.
+
+config VGA_ROM_RUN_INTEL
+ bool "Run Legacy Intel VGA Option ROMs"
+ depends on PCI && ARCH_X86 && !MAINBOARD_FORCE_NATIVE_VGA_INIT
+ select HAVE_VGA_TEXT_FRAMEBUFFER
+ help
+ Execute Intel VGA Option ROMs in coreboot if found. This can be
+ used to enable onboard Intel video cards when not using a SeaBIOS
+ payload.
+
+ When using a SeaBIOS payload it runs all option ROMs with much
+ more complete BIOS interrupt services available than coreboot,
+ which some option ROMs require in order to function correctly.
+
config RUN_FSP_GOP
bool "Run a GOP driver"
depends on HAVE_FSP_GOP && !MAINBOARD_NO_FSP_GOP
@@ -115,13 +153,12 @@
to run a GOP blob. This option enables graphics initialization with
such a blob.
-config NO_GFX_INIT
+config NO_INTEL_GFX_INIT
bool "None"
- depends on !MAINBOARD_FORCE_NATIVE_VGA_INIT
help
Select this to not perform any graphics initialization in
- coreboot. This is useful if the payload (e.g. SeaBIOS) can
- initialize graphics or if pre-boot graphics are not required.
+ coreboot on the IGD. This is useful if the payload (e.g. SeaBIOS)
+ can initialize graphics or if pre-boot graphics are not required.
endchoice
@@ -138,7 +175,7 @@
config S3_VGA_ROM_RUN
bool "Re-run VGA Option ROMs on S3 resume"
default y
- depends on VGA_ROM_RUN && HAVE_ACPI_RESUME
+ depends on (VGA_ROM_RUN || VGA_ROM_RUN_INTEL) && HAVE_ACPI_RESUME
help
Execute VGA Option ROMs in coreboot when resuming from S3 suspend.
@@ -150,7 +187,7 @@
config ALWAYS_LOAD_OPROM
def_bool n
- depends on VGA_ROM_RUN
+ depends on VGA_ROM_RUN || VGA_ROM_RUN_INTEL
help
Always load option ROMs if any are found. The decision to run
the ROM is still determined at runtime, but the distinction
@@ -171,7 +208,7 @@
bool "Load Option ROMs on PCI devices"
default n if PAYLOAD_SEABIOS
default y if !PAYLOAD_SEABIOS
- depends on VGA_ROM_RUN
+ depends on VGA_ROM_RUN || VGA_ROM_RUN_INTEL
help
Load Option ROMs stored on PCI/PCIe/AGP VGA devices in coreboot.
@@ -190,7 +227,7 @@
prompt "Option ROM execution type"
default PCI_OPTION_ROM_RUN_YABEL if !ARCH_X86
default PCI_OPTION_ROM_RUN_REALMODE if ARCH_X86
- depends on VGA_ROM_RUN
+ depends on VGA_ROM_RUN || VGA_ROM_RUN_INTEL
config PCI_OPTION_ROM_RUN_REALMODE
prompt "Native mode"
diff --git a/src/device/pci_device.c b/src/device/pci_device.c
index a7eb91d..bfdeeaf 100644
--- a/src/device/pci_device.c
+++ b/src/device/pci_device.c
@@ -718,6 +718,10 @@
static int should_load_oprom(struct device *dev)
{
+ if (!CONFIG(VGA_ROM_RUN) && CONFIG(VGA_ROM_RUN_INTEL) &&
+ dev->vendor != PCI_VENDOR_ID_INTEL)
+ return 0;
+
/* If S3_VGA_ROM_RUN is disabled, skip running VGA option
* ROMs when coming out of an S3 resume.
*/
@@ -737,7 +741,7 @@
{
struct rom_header *rom, *ram;
- if (!CONFIG(VGA_ROM_RUN))
+ if (!CONFIG(VGA_ROM_RUN) && !CONFIG(VGA_ROM_RUN_INTEL))
return;
/* Only execute VGA ROMs. */
diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c
index 4224c65..13ee765 100644
--- a/src/device/pci_rom.c
+++ b/src/device/pci_rom.c
@@ -178,7 +178,7 @@
struct rom_header *run_rom;
struct pci_data *rom_data;
- if (!CONFIG(VGA_ROM_RUN))
+ if (!CONFIG(VGA_ROM_RUN) && !CONFIG(VGA_ROM_RUN_INTEL))
return NULL;
run_rom = (struct rom_header *)(uintptr_t)PCI_VGA_RAM_IMAGE_START;
diff --git a/src/drivers/intel/gma/Makefile.inc b/src/drivers/intel/gma/Makefile.inc
index 964d13e..d73f800 100644
--- a/src/drivers/intel/gma/Makefile.inc
+++ b/src/drivers/intel/gma/Makefile.inc
@@ -2,7 +2,7 @@
ramstage-$(CONFIG_INTEL_DDI) += intel_ddi.c
ramstage-$(CONFIG_INTEL_EDID) += edid.c vbt.c
-ifeq ($(CONFIG_VGA_ROM_RUN),y)
+ifeq ($(CONFIG_VGA_ROM_RUN_INTEL),y)
ramstage-$(CONFIG_INTEL_INT15) += int15.c
endif
ramstage-$(CONFIG_INTEL_GMA_ACPI) += acpi.c
diff --git a/src/drivers/intel/gma/int15.h b/src/drivers/intel/gma/int15.h
index cddd4ac..461d144 100644
--- a/src/drivers/intel/gma/int15.h
+++ b/src/drivers/intel/gma/int15.h
@@ -27,7 +27,7 @@
GMA_INT15_ACTIVE_LFP_EDP = 0x03,
};
-#if CONFIG(VGA_ROM_RUN)
+#if CONFIG(VGA_ROM_RUN_INTEL)
/* Install custom int15 handler for VGA OPROM */
void install_intel_vga_int15_handler(int active_lfp, int pfit, int display, int panel_type);
#else
diff --git a/src/mainboard/bostentech/gbyt4/mainboard.c b/src/mainboard/bostentech/gbyt4/mainboard.c
index d0131bc..857a0c2 100644
--- a/src/mainboard/bostentech/gbyt4/mainboard.c
+++ b/src/mainboard/bostentech/gbyt4/mainboard.c
@@ -2,12 +2,12 @@
#include <device/device.h>
#include <console/console.h>
-#if CONFIG(VGA_ROM_RUN)
+#if CONFIG(VGA_ROM_RUN_INTEL)
#include <x86emu/x86emu.h>
#endif
#include <arch/interrupt.h>
-#if CONFIG(VGA_ROM_RUN)
+#if CONFIG(VGA_ROM_RUN_INTEL)
static int int15_handler(void)
{
int res = 1;
@@ -98,7 +98,7 @@
static void mainboard_enable(struct device *dev)
{
-#if CONFIG(VGA_ROM_RUN)
+#if CONFIG(VGA_ROM_RUN_INTEL)
/* Install custom int15 handler for VGA OPROM */
mainboard_interrupt_handlers(0x15, &int15_handler);
#endif
diff --git a/src/mainboard/google/link/mainboard.c b/src/mainboard/google/link/mainboard.c
index c4b621a..fd04031 100644
--- a/src/mainboard/google/link/mainboard.c
+++ b/src/mainboard/google/link/mainboard.c
@@ -4,7 +4,7 @@
#include <device/device.h>
#include <device/pci_ops.h>
#include <console/console.h>
-#if CONFIG(VGA_ROM_RUN)
+#if CONFIG(VGA_ROM_RUN_INTEL)
#include <x86emu/x86emu.h>
#endif
#include <acpi/acpi.h>
@@ -18,7 +18,7 @@
#include <ec/google/chromeec/ec.h>
#include <vendorcode/google/chromeos/chromeos.h>
-#if CONFIG(VGA_ROM_RUN)
+#if CONFIG(VGA_ROM_RUN_INTEL)
static int int15_handler(void)
{
int res = 0;
@@ -171,7 +171,7 @@
dev->ops->init = mainboard_init;
dev->ops->get_smbios_data = link_onboard_smbios_data;
dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
-#if CONFIG(VGA_ROM_RUN)
+#if CONFIG(VGA_ROM_RUN_INTEL)
/* Install custom int15 handler for VGA OPROM */
mainboard_interrupt_handlers(0x15, &int15_handler);
#endif
diff --git a/src/mainboard/google/rambi/mainboard.c b/src/mainboard/google/rambi/mainboard.c
index 41d9795..894cc74 100644
--- a/src/mainboard/google/rambi/mainboard.c
+++ b/src/mainboard/google/rambi/mainboard.c
@@ -2,7 +2,7 @@
#include <device/device.h>
#include <console/console.h>
-#if CONFIG(VGA_ROM_RUN)
+#if CONFIG(VGA_ROM_RUN_INTEL)
#include <x86emu/x86emu.h>
#endif
#include <arch/interrupt.h>
@@ -13,7 +13,7 @@
#include <bootstate.h>
#include <vendorcode/google/chromeos/chromeos.h>
-#if CONFIG(VGA_ROM_RUN)
+#if CONFIG(VGA_ROM_RUN_INTEL)
static int int15_handler(void)
{
int res = 1;
@@ -144,7 +144,7 @@
dev->ops->init = mainboard_init;
dev->ops->get_smbios_data = mainboard_smbios_data;
dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
-#if CONFIG(VGA_ROM_RUN)
+#if CONFIG(VGA_ROM_RUN_INTEL)
/* Install custom int15 handler for VGA OPROM */
mainboard_interrupt_handlers(0x15, &int15_handler);
#endif
diff --git a/src/mainboard/kontron/ktqm77/mainboard.c b/src/mainboard/kontron/ktqm77/mainboard.c
index 95e639a..c571c7f 100644
--- a/src/mainboard/kontron/ktqm77/mainboard.c
+++ b/src/mainboard/kontron/ktqm77/mainboard.c
@@ -4,14 +4,14 @@
#include <device/device.h>
#include <device/pci_def.h>
#include <console/console.h>
-#if CONFIG(VGA_ROM_RUN)
+#if CONFIG(VGA_ROM_RUN_INTEL)
#include <x86emu/x86emu.h>
#endif
#include <option.h>
#include <arch/interrupt.h>
#include <southbridge/intel/bd82x6x/pch.h>
-#if CONFIG(VGA_ROM_RUN)
+#if CONFIG(VGA_ROM_RUN_INTEL)
static int int15_handler(void)
{
int res = 0;
diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig
index 091d2f1..919331b 100644
--- a/src/northbridge/intel/i945/Kconfig
+++ b/src/northbridge/intel/i945/Kconfig
@@ -12,7 +12,7 @@
select INTEL_GMA_ACPI
select INTEL_GMA_SSC_ALTERNATE_REF
select INTEL_EDID
- select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT
+ select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_INTEL_VGA_INIT
select PARALLEL_MP
config VBOOT
diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c
index b396eff..7447ab2 100644
--- a/src/northbridge/intel/i945/gma.c
+++ b/src/northbridge/intel/i945/gma.c
@@ -672,7 +672,7 @@
if (!CONFIG(NO_GFX_INIT))
pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
- if (CONFIG(MAINBOARD_DO_NATIVE_VGA_INIT)) {
+ if (CONFIG(MAINBOARD_DO_NATIVE_INTEL_VGA_INIT)) {
int vga_disable = (pci_read_config16(dev, GGC) & 2) >> 1;
if (acpi_is_wakeup_s3()) {
printk(BIOS_INFO,
diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig
index 962825a..fe4fd6b 100644
--- a/src/northbridge/intel/pineview/Kconfig
+++ b/src/northbridge/intel/pineview/Kconfig
@@ -10,8 +10,8 @@
select HAVE_DEBUG_RAM_SETUP
select VGA
select MAINBOARD_HAS_NATIVE_INTEL_VGA_INIT
- select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT
- select INTEL_EDID if MAINBOARD_DO_NATIVE_VGA_INIT
+ select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_INTEL_VGA_INIT
+ select INTEL_EDID if MAINBOARD_DO_NATIVE_INTEL_VGA_INIT
select INTEL_GMA_ACPI
select PARALLEL_MP
select NO_CBFS_MCACHE
diff --git a/src/northbridge/intel/pineview/gma.c b/src/northbridge/intel/pineview/gma.c
index e0ed0f0..fcd05f8 100644
--- a/src/northbridge/intel/pineview/gma.c
+++ b/src/northbridge/intel/pineview/gma.c
@@ -224,7 +224,7 @@
if (!CONFIG(NO_GFX_INIT))
pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
- if (!CONFIG(MAINBOARD_DO_NATIVE_VGA_INIT)) {
+ if (!CONFIG(MAINBOARD_DO_NATIVE_INTEL_VGA_INIT)) {
/* PCI init, will run VBIOS */
pci_dev_init(dev);
} else {
diff --git a/src/soc/intel/common/block/timer/Kconfig b/src/soc/intel/common/block/timer/Kconfig
index 42613a8..f7d705c 100644
--- a/src/soc/intel/common/block/timer/Kconfig
+++ b/src/soc/intel/common/block/timer/Kconfig
@@ -5,7 +5,7 @@
config USE_LEGACY_8254_TIMER
bool "Use Legacy 8254 Timer"
- default y if PAYLOAD_SEABIOS || VGA_ROM_RUN
+ default y if PAYLOAD_SEABIOS || VGA_ROM_RUN || VGA_ROM_RUN_INTEL
default n
help
Setting this makes the Legacy 8254 Timer available by disabling
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I410fecfdb8a99ca520b2c05edd9ed2558d7e0a92
Gerrit-Change-Number: 49176
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>
Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-Reviewer: Damien Zammit
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
Gerrit-MessageType: newchange
5
10
Change in coreboot[master]: eltan/verified_boot: include vboot21 code directly
by Joel Kitching (Code Review) 07 Aug '23
by Joel Kitching (Code Review) 07 Aug '23
07 Aug '23
Joel Kitching has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37654 )
Change subject: eltan/verified_boot: include vboot21 code directly
......................................................................
eltan/verified_boot: include vboot21 code directly
vboot 2.1 data structures and code, as well as the fwlib21 build
target, are all being deprecated. Any use of these data
structures and code should be forked and handled separately.
The data structures and functions used by eltan verified boot
were never part of the vboot API, and were never intended to be
used by external parties.
Instead of building fwlib21 target, build fwlib instead, which
will be the only available library going forward. This can
provide access to the vb2_sha.h API.
Note that vboot 2.1 error codes will also be deprecated in the
future. At this point, vb2_error_t may also be forked and
included in eltan_vb21.h.
BUG=b:124141368, chromium:968464
TEST=util/abuild/abuild -v -B -e -p none -t FACEBOOK_FBG1701
BRANCH=none
Change-Id: Iae58a0c42161ddfec9908f9867286e3dc1f055a2
Signed-off-by: Joel Kitching <kitching(a)google.com>
---
M src/vendorcode/eltan/security/include/cb_sha.h
M src/vendorcode/eltan/security/lib/Makefile.inc
M src/vendorcode/eltan/security/verified_boot/Makefile.inc
A src/vendorcode/eltan/security/verified_boot/eltan_vb21.c
A src/vendorcode/eltan/security/verified_boot/eltan_vb21.h
M src/vendorcode/eltan/security/verified_boot/vboot_check.c
6 files changed, 1,114 insertions(+), 32 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/37654/1
diff --git a/src/vendorcode/eltan/security/include/cb_sha.h b/src/vendorcode/eltan/security/include/cb_sha.h
index 9a231d8..eea9f40 100644
--- a/src/vendorcode/eltan/security/include/cb_sha.h
+++ b/src/vendorcode/eltan/security/include/cb_sha.h
@@ -16,9 +16,7 @@
#ifndef __SECURITY_CB_SHA_H__
#define __SECURITY_CB_SHA_H__
-#include <2rsa.h>
-#include <vb21_common.h>
-#include <vb2_api.h>
+#include <vb2_sha.h>
vb2_error_t cb_sha_little_endian(enum vb2_hash_algorithm hash_alg, const uint8_t *data,
uint32_t len, uint8_t *digest);
diff --git a/src/vendorcode/eltan/security/lib/Makefile.inc b/src/vendorcode/eltan/security/lib/Makefile.inc
index 2e11fb5..d79d70b 100644
--- a/src/vendorcode/eltan/security/lib/Makefile.inc
+++ b/src/vendorcode/eltan/security/lib/Makefile.inc
@@ -16,7 +16,9 @@
# call with $1 = stage name to create rules for building the library
# for the stage and adding it to the stage's set of object files.
define vendor-security-lib
-VEN_SEC_LIB_$(1) = $(obj)/external/ven_sec_lib-$(1)/vboot_fw21.a
+VEN_SEC_LIB_$(1) = \
+ $(obj)/external/ven_sec_lib-$(1)/vboot_fw.a
+
VEN_SEC_CFLAGS_$(1) += $$(patsubst -I%,-I$(top)/%,\
$$(patsubst $(src)/%.h,$(top)/$(src)/%.h,\
$$(filter-out -I$(obj), $$(CPPFLAGS_$(1)))))
@@ -32,29 +34,25 @@
$(MAKE) -C $(VBOOT_SOURCE) \
BUILD=$$(abspath $$(dir $$(VEN_SEC_LIB_$(1)))) \
V=$(V) \
- fwlib21
+ fwlib
endef # vendor-security-for-stage
-CFLAGS_common += -I3rdparty/vboot/firmware/2lib/include
-CFLAGS_common += -I3rdparty/vboot/firmware/lib21/include
-
ifneq ($(filter y,$(CONFIG_VENDORCODE_ELTAN_VBOOT) $(CONFIG_VENDORCODE_ELTAN_MBOOT)),)
bootblock-y += cb_sha.c
-bootblock-y += ../../../../security/vboot/vboot_logic.c
$(eval $(call vendor-security-lib,bootblock))
-bootblock-srcs += $(obj)/external/ven_sec_lib-bootblock/vboot_fw21.a
+bootblock-srcs += $(obj)/external/ven_sec_lib-bootblock/vboot_fw.a
postcar-y += cb_sha.c
$(eval $(call vendor-security-lib,postcar))
-postcar-srcs += $(obj)/external/ven_sec_lib-postcar/vboot_fw21.a
+postcar-srcs += $(obj)/external/ven_sec_lib-postcar/vboot_fw.a
ramstage-y += cb_sha.c
$(eval $(call vendor-security-lib,ramstage))
-ramstage-srcs += $(obj)/external/ven_sec_lib-ramstage/vboot_fw21.a
+ramstage-srcs += $(obj)/external/ven_sec_lib-ramstage/vboot_fw.a
romstage-y += cb_sha.c
$(eval $(call vendor-security-lib,romstage))
-romstage-srcs += $(obj)/external/ven_sec_lib-romstage/vboot_fw21.a
+romstage-srcs += $(obj)/external/ven_sec_lib-romstage/vboot_fw.a
-endif
\ No newline at end of file
+endif
diff --git a/src/vendorcode/eltan/security/verified_boot/Makefile.inc b/src/vendorcode/eltan/security/verified_boot/Makefile.inc
index 97d8f81..1663fa5 100644
--- a/src/vendorcode/eltan/security/verified_boot/Makefile.inc
+++ b/src/vendorcode/eltan/security/verified_boot/Makefile.inc
@@ -15,7 +15,10 @@
ifneq ($(filter y,$(CONFIG_VENDORCODE_ELTAN_VBOOT) $(CONFIG_VENDORCODE_ELTAN_MBOOT)),)
-CPPFLAGS_common += -I$(src)/security/vboot
+bootblock-y += eltan_vb21.c
+postcar-y += eltan_vb21.c
+romstage-y += eltan_vb21.c
+ramstage-y += eltan_vb21.c
bootblock-y += vboot_check.c
postcar-y += vboot_check.c
diff --git a/src/vendorcode/eltan/security/verified_boot/eltan_vb21.c b/src/vendorcode/eltan/security/verified_boot/eltan_vb21.c
new file mode 100644
index 0000000..277b55a
--- /dev/null
+++ b/src/vendorcode/eltan/security/verified_boot/eltan_vb21.c
@@ -0,0 +1,840 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <vb2_sha.h>
+#include <vendorcode/eltan/security/verified_boot/eltan_vb21.h>
+
+/**
+ * a[] -= mod
+ */
+static void subM(const struct evb2_public_key *key, uint32_t *a)
+{
+ int64_t A = 0;
+ uint32_t i;
+ for (i = 0; i < key->arrsize; ++i) {
+ A += (uint64_t)a[i] - key->n[i];
+ a[i] = (uint32_t)A;
+ A >>= 32;
+ }
+}
+
+/**
+ * Return a[] >= mod
+ */
+static int evb2_mont_ge(const struct evb2_public_key *key, uint32_t *a)
+{
+ uint32_t i;
+ for (i = key->arrsize; i;) {
+ --i;
+ if (a[i] < key->n[i])
+ return 0;
+ if (a[i] > key->n[i])
+ return 1;
+ }
+ return 1; /* equal */
+}
+
+/**
+ * Montgomery c[] += a * b[] / R % mod
+ */
+static void montMulAdd(const struct evb2_public_key *key,
+ uint32_t *c,
+ const uint32_t a,
+ const uint32_t *b)
+{
+ uint64_t A = (uint64_t)a * b[0] + c[0];
+ uint32_t d0 = (uint32_t)A * key->n0inv;
+ uint64_t B = (uint64_t)d0 * key->n[0] + (uint32_t)A;
+ uint32_t i;
+
+ for (i = 1; i < key->arrsize; ++i) {
+ A = (A >> 32) + (uint64_t)a * b[i] + c[i];
+ B = (B >> 32) + (uint64_t)d0 * key->n[i] + (uint32_t)A;
+ c[i - 1] = (uint32_t)B;
+ }
+
+ A = (A >> 32) + (B >> 32);
+
+ c[i - 1] = (uint32_t)A;
+
+ if (A >> 32) {
+ subM(key, c);
+ }
+}
+
+/**
+ * Montgomery c[] += 0 * b[] / R % mod
+ */
+static void montMulAdd0(const struct evb2_public_key *key,
+ uint32_t *c,
+ const uint32_t *b)
+{
+ uint32_t d0 = c[0] * key->n0inv;
+ uint64_t B = (uint64_t)d0 * key->n[0] + c[0];
+ uint32_t i;
+
+ for (i = 1; i < key->arrsize; ++i) {
+ B = (B >> 32) + (uint64_t)d0 * key->n[i] + c[i];
+ c[i - 1] = (uint32_t)B;
+ }
+
+ c[i - 1] = B >> 32;
+}
+
+/**
+ * Montgomery c[] = a[] * b[] / R % mod
+ */
+static void montMul(const struct evb2_public_key *key,
+ uint32_t *c,
+ const uint32_t *a,
+ const uint32_t *b)
+{
+ uint32_t i;
+ for (i = 0; i < key->arrsize; ++i) {
+ c[i] = 0;
+ }
+ for (i = 0; i < key->arrsize; ++i) {
+ montMulAdd(key, c, a[i], b);
+ }
+}
+
+/* Montgomery c[] = a[] * 1 / R % key. */
+static void montMul1(const struct evb2_public_key *key,
+ uint32_t *c,
+ const uint32_t *a)
+{
+ int i;
+
+ for (i = 0; i < key->arrsize; ++i)
+ c[i] = 0;
+
+ montMulAdd(key, c, 1, a);
+ for (i = 1; i < key->arrsize; ++i)
+ montMulAdd0(key, c, a);
+}
+
+/**
+ * In-place public exponentiation.
+ *
+ * @param key Key to use in signing
+ * @param inout Input and output big-endian byte array
+ * @param workbuf32 Work buffer; caller must verify this is
+ * (3 * key->arrsize) elements long.
+ * @param exp RSA public exponent: either 65537 (F4) or 3
+ */
+static void modpow(const struct evb2_public_key *key, uint8_t *inout,
+ uint32_t *workbuf32, int exp)
+{
+ uint32_t *a = workbuf32;
+ uint32_t *aR = a + key->arrsize;
+ uint32_t *aaR = aR + key->arrsize;
+ uint32_t *aaa = aaR; /* Re-use location. */
+ int i;
+
+ /* Convert from big endian byte array to little endian word array. */
+ for (i = 0; i < (int)key->arrsize; ++i) {
+ uint32_t tmp =
+ ((uint32_t)inout[((key->arrsize - 1 - i) * 4) + 0]
+ << 24) |
+ (inout[((key->arrsize - 1 - i) * 4) + 1] << 16) |
+ (inout[((key->arrsize - 1 - i) * 4) + 2] << 8) |
+ (inout[((key->arrsize - 1 - i) * 4) + 3] << 0);
+ a[i] = tmp;
+ }
+
+ montMul(key, aR, a, key->rr); /* aR = a * RR / R mod M */
+ if (exp == 3) {
+ montMul(key, aaR, aR, aR); /* aaR = aR * aR / R mod M */
+ montMul(key, a, aaR, aR); /* a = aaR * aR / R mod M */
+ montMul1(key, aaa, a); /* aaa = a * 1 / R mod M */
+ } else {
+ /* Exponent 65537 */
+ for (i = 0; i < 16; i+=2) {
+ montMul(key, aaR, aR, aR); /* aaR = aR * aR / R mod M */
+ montMul(key, aR, aaR, aaR); /* aR = aaR * aaR / R mod M */
+ }
+ montMul(key, aaa, aR, a); /* aaa = aR * a / R mod M */
+ }
+
+ /* Make sure aaa < mod; aaa is at most 1x mod too large. */
+ if (evb2_mont_ge(key, aaa)) {
+ subM(key, aaa);
+ }
+
+ /* Convert to bigendian byte array */
+ for (i = (int)key->arrsize - 1; i >= 0; --i) {
+ uint32_t tmp = aaa[i];
+ *inout++ = (uint8_t)(tmp >> 24);
+ *inout++ = (uint8_t)(tmp >> 16);
+ *inout++ = (uint8_t)(tmp >> 8);
+ *inout++ = (uint8_t)(tmp >> 0);
+ }
+}
+
+/**
+ * Safer memcmp() for use in crypto.
+ *
+ * Compares the buffers to see if they are equal. Time taken to perform
+ * the comparison is dependent only on the size, not the relationship of
+ * the match between the buffers. Note that unlike memcmp(), this only
+ * indicates inequality, not which buffer is lesser.
+ *
+ * @param s1 First buffer
+ * @param s2 Second buffer
+ * @param size Number of bytes to compare
+ * @return 0 if match or size=0, non-zero if at least one byte mismatched.
+ */
+static vb2_error_t evb2_safe_memcmp(const void *s1, const void *s2, size_t size)
+{
+ const unsigned char *us1 = s1;
+ const unsigned char *us2 = s2;
+ int result = 0;
+
+ if (0 == size)
+ return 0;
+
+ /*
+ * Code snippet without data-dependent branch due to Nate Lawson
+ * (nate(a)root.org) of Root Labs.
+ */
+ while (size--)
+ result |= *us1++ ^ *us2++;
+
+ return result != 0;
+}
+
+/**
+ * Round up a number to a multiple of VB2_WORKBUF_ALIGN
+ *
+ * @param v Number to round up
+ * @return The number, rounded up.
+ */
+static inline uint32_t evb2_wb_round_up(uint32_t v)
+{
+ return (v + VB2_WORKBUF_ALIGN - 1) & ~(VB2_WORKBUF_ALIGN - 1);
+}
+
+/**
+ * Allocate space in a work buffer.
+ *
+ * Note that the returned buffer will always be aligned to VB2_WORKBUF_ALIGN.
+ *
+ * The work buffer acts like a stack, and detailed tracking of allocs and frees
+ * is not done. The caller must track the size of each allocation and free via
+ * evb2_workbuf_free() in the reverse order they were allocated.
+ *
+ * An acceptable alternate workflow inside a function is to pass in a const
+ * work buffer, then make a local copy. Allocations done to the local copy
+ * then don't change the passed-in work buffer, and will effectively be freed
+ * when the local copy goes out of scope.
+ *
+ * @param wb Work buffer
+ * @param size Requested size in bytes
+ * @return A pointer to the allocated space, or NULL if error.
+ */
+static void *evb2_workbuf_alloc(struct evb2_workbuf *wb, uint32_t size)
+{
+ uint8_t *ptr = wb->buf;
+
+ /* Round up size to work buffer alignment */
+ size = evb2_wb_round_up(size);
+
+ if (size > wb->size)
+ return NULL;
+
+ wb->buf += size;
+ wb->size -= size;
+
+ return ptr;
+}
+
+/**
+ * Free the preceding allocation.
+ *
+ * Note that the work buffer acts like a stack, and detailed tracking of
+ * allocs and frees is not done. The caller must track the size of each
+ * allocation and free them in reverse order.
+ *
+ * @param wb Work buffer
+ * @param size Size of data to free
+ */
+static void evb2_workbuf_free(struct evb2_workbuf *wb, uint32_t size)
+{
+ /* Round up size to work buffer alignment */
+ size = evb2_wb_round_up(size);
+
+ wb->buf -= size;
+ wb->size += size;
+}
+
+/*
+ * PKCS 1.5 padding (from the RSA PKCS#1 v2.1 standard)
+ *
+ * Depending on the RSA key size and hash function, the padding is calculated
+ * as follows:
+ *
+ * 0x00 || 0x01 || PS || 0x00 || T
+ *
+ * T: DER Encoded DigestInfo value which depends on the hash function used.
+ *
+ * SHA-1: (0x)30 21 30 09 06 05 2b 0e 03 02 1a 05 00 04 14 || H.
+ * SHA-256: (0x)30 31 30 0d 06 09 60 86 48 01 65 03 04 02 01 05 00 04 20 || H.
+ * SHA-512: (0x)30 51 30 0d 06 09 60 86 48 01 65 03 04 02 03 05 00 04 40 || H.
+ *
+ * Length(T) = 35 octets for SHA-1
+ * Length(T) = 51 octets for SHA-256
+ * Length(T) = 83 octets for SHA-512
+ *
+ * PS: octet string consisting of {Length(RSA Key) - Length(T) - 3} 0xFF
+ */
+static const uint8_t sha1_tail[] = {
+ 0x00,0x30,0x21,0x30,0x09,0x06,0x05,0x2b,
+ 0x0e,0x03,0x02,0x1a,0x05,0x00,0x04,0x14
+};
+
+static const uint8_t sha256_tail[] = {
+ 0x00,0x30,0x31,0x30,0x0d,0x06,0x09,0x60,
+ 0x86,0x48,0x01,0x65,0x03,0x04,0x02,0x01,
+ 0x05,0x00,0x04,0x20
+};
+
+static const uint8_t sha512_tail[] = {
+ 0x00,0x30,0x51,0x30,0x0d,0x06,0x09,0x60,
+ 0x86,0x48,0x01,0x65,0x03,0x04,0x02,0x03,
+ 0x05,0x00,0x04,0x40
+};
+
+/**
+ * Check pkcs 1.5 padding bytes
+ *
+ * @param sig Signature to verify
+ * @param key Key to take signature and hash algorithms from
+ * @return VB2_SUCCESS, or non-zero if error.
+ */
+static vb2_error_t evb2_check_padding(const uint8_t *sig,
+ const struct evb2_public_key *key)
+{
+ /* Determine padding to use depending on the signature type */
+ uint32_t sig_size = evb2_rsa_sig_size(key->sig_alg);
+ uint32_t hash_size = vb2_digest_size(key->hash_alg);
+ uint32_t pad_size = sig_size - hash_size;
+ const uint8_t *tail;
+ uint32_t tail_size;
+ int result = 0;
+ int i;
+
+ if (!sig_size || !hash_size || hash_size > sig_size)
+ return VB2_ERROR_RSA_PADDING_SIZE;
+
+ switch (key->hash_alg) {
+ case VB2_HASH_SHA1:
+ tail = sha1_tail;
+ tail_size = sizeof(sha1_tail);
+ break;
+ case VB2_HASH_SHA256:
+ tail = sha256_tail;
+ tail_size = sizeof(sha256_tail);
+ break;
+ case VB2_HASH_SHA512:
+ tail = sha512_tail;
+ tail_size = sizeof(sha512_tail);
+ break;
+ default:
+ return VB2_ERROR_RSA_PADDING_ALGORITHM;
+ }
+
+ /* First 2 bytes are always 0x00 0x01 */
+ result |= *sig++ ^ 0x00;
+ result |= *sig++ ^ 0x01;
+
+ /* Then 0xff bytes until the tail */
+ for (i = 0; i < pad_size - tail_size - 2; i++)
+ result |= *sig++ ^ 0xff;
+
+ /*
+ * Then the tail. Even though there are probably no timing issues
+ * here, we use evb2_safe_memcmp() just to be on the safe side.
+ */
+ result |= evb2_safe_memcmp(sig, tail, tail_size);
+
+ return result ? VB2_ERROR_RSA_PADDING : VB2_SUCCESS;
+}
+
+/**
+ * Return the exponent used by an RSA algorithm
+ *
+ * @param sig_alg Signature algorithm
+ * @return The exponent to use (3 or 65537(F4)), or 0 if error.
+ */
+static uint32_t evb2_rsa_exponent(enum vb2_signature_algorithm sig_alg)
+{
+ switch (sig_alg) {
+ case VB2_SIG_RSA1024:
+ case VB2_SIG_RSA2048:
+ case VB2_SIG_RSA4096:
+ case VB2_SIG_RSA8192:
+ return 65537;
+ case VB2_SIG_RSA2048_EXP3:
+ case VB2_SIG_RSA3072_EXP3:
+ return 3;
+ default:
+ return 0;
+ }
+}
+
+/**
+ * Verify a RSA PKCS1.5 signature against an expected hash digest.
+ *
+ * @param key Key to use in signature verification
+ * @param sig Signature to verify (destroyed in process)
+ * @param digest Digest of signed data
+ * @param wb Work buffer
+ * @return VB2_SUCCESS, or non-zero if error.
+ */
+static vb2_error_t evb2_rsa_verify_digest(const struct evb2_public_key *key,
+ uint8_t *sig, const uint8_t *digest,
+ const struct evb2_workbuf *wb)
+{
+ struct evb2_workbuf wblocal = *wb;
+ uint32_t *workbuf32;
+ uint32_t key_bytes;
+ int sig_size;
+ int pad_size;
+ int exp;
+ vb2_error_t rv;
+
+ if (!key || !sig || !digest)
+ return VB2_ERROR_RSA_VERIFY_PARAM;
+
+ sig_size = evb2_rsa_sig_size(key->sig_alg);
+ exp = evb2_rsa_exponent(key->sig_alg);
+ if (!sig_size || !exp) {
+ EVB2_DEBUG("Invalid signature type!\n");
+ return VB2_ERROR_RSA_VERIFY_ALGORITHM;
+ }
+
+ /* Signature length should be same as key length */
+ key_bytes = key->arrsize * sizeof(uint32_t);
+ if (key_bytes != sig_size) {
+ EVB2_DEBUG("Signature is of incorrect length!\n");
+ return VB2_ERROR_RSA_VERIFY_SIG_LEN;
+ }
+
+ workbuf32 = evb2_workbuf_alloc(&wblocal, 3 * key_bytes);
+ if (!workbuf32) {
+ EVB2_DEBUG("ERROR - vboot2 work buffer too small!\n");
+ return VB2_ERROR_RSA_VERIFY_WORKBUF;
+ }
+
+ modpow(key, sig, workbuf32, exp);
+
+ evb2_workbuf_free(&wblocal, 3 * key_bytes);
+
+ /*
+ * Check padding. Only fail immediately if the padding size is bad.
+ * Otherwise, continue on to check the digest to reduce the risk of
+ * timing based attacks.
+ */
+ rv = evb2_check_padding(sig, key);
+ if (rv == VB2_ERROR_RSA_PADDING_SIZE)
+ return rv;
+
+ /*
+ * Check digest. Even though there are probably no timing issues here,
+ * use evb2_safe_memcmp() just to be on the safe side. (That's also why
+ * we don't return before this check if the padding check failed.)
+ */
+ pad_size = sig_size - vb2_digest_size(key->hash_alg);
+ if (evb2_safe_memcmp(sig + pad_size, digest, key_bytes - pad_size)) {
+ EVB2_DEBUG("Digest check failed!\n");
+ if (!rv)
+ rv = VB2_ERROR_RSA_VERIFY_DIGEST;
+ }
+
+ return rv;
+}
+
+/**
+ * Return the description of an object starting with a evb21_struct_common
+ * header.
+ *
+ * Does not sanity-check the buffer; merely returns the pointer.
+ *
+ * @param buf Pointer to common object
+ * @return A pointer to description or an empty string if none.
+ */
+static const char *evb21_common_desc(const void *buf)
+{
+ const struct evb21_struct_common *c = buf;
+
+ return c->desc_size ? (const char *)c + c->fixed_size : "";
+}
+
+/**
+ * Verify the common struct header is fully contained in its parent data
+ *
+ * Also verifies the description is either zero-length or null-terminated.
+ *
+ * @param parent Parent data
+ * @param parent_size Parent size in bytes
+ * @return VB2_SUCCESS, or non-zero if error.
+ */
+static vb2_error_t evb21_verify_common_header(const void *parent,
+ uint32_t parent_size)
+{
+ const struct evb21_struct_common *c = parent;
+
+ /* Parent buffer size must be at least the claimed total size */
+ if (parent_size < c->total_size)
+ return VB2_ERROR_COMMON_TOTAL_SIZE;
+
+ /*
+ * And big enough for the fixed size, which itself must be at least as
+ * big as the common struct header.
+ */
+ if (c->total_size < c->fixed_size || c->fixed_size < sizeof(*c))
+ return VB2_ERROR_COMMON_FIXED_SIZE;
+
+ /* Make sure sizes are all multiples of 32 bits */
+ if (!evb2_aligned(c->total_size, sizeof(uint32_t)))
+ return VB2_ERROR_COMMON_TOTAL_UNALIGNED;
+ if (!evb2_aligned(c->fixed_size, sizeof(uint32_t)))
+ return VB2_ERROR_COMMON_FIXED_UNALIGNED;
+ if (!evb2_aligned(c->desc_size, sizeof(uint32_t)))
+ return VB2_ERROR_COMMON_DESC_UNALIGNED;
+
+ /* Check description */
+ if (c->desc_size > 0) {
+ /* Make sure description fits and doesn't wrap */
+ if (c->fixed_size + c->desc_size < c->fixed_size)
+ return VB2_ERROR_COMMON_DESC_WRAPS;
+ if (c->fixed_size + c->desc_size > c->total_size)
+ return VB2_ERROR_COMMON_DESC_SIZE;
+
+ /* Description must be null-terminated */
+ if (evb21_common_desc(c)[c->desc_size - 1] != 0)
+ return VB2_ERROR_COMMON_DESC_TERMINATOR;
+ }
+
+ return VB2_SUCCESS;
+}
+
+/**
+ * Verify a member is within the data for a parent object
+ *
+ * @param parent Parent data (starts with struct evb21_struct_common)
+ * @param min_offset Pointer to minimum offset where member can be located.
+ * If this offset is 0 on input, uses the size of the
+ * fixed header (and description, if any). This will be
+ * updated on return to the end of the passed member. On
+ * error, the value of min_offset is undefined.
+ * @param member_offset Offset of member data from start of parent, in bytes
+ * @param member_size Size of member data, in bytes
+ * @return VB2_SUCCESS, or non-zero if error.
+ */
+static vb2_error_t evb21_verify_common_member(const void *parent,
+ uint32_t *min_offset,
+ uint32_t member_offset,
+ uint32_t member_size)
+{
+ const struct evb21_struct_common *c = parent;
+ uint32_t member_end = member_offset + member_size;
+
+ /* Make sure member doesn't wrap */
+ if (member_end < member_offset)
+ return VB2_ERROR_COMMON_MEMBER_WRAPS;
+
+ /* Member offset and size must be 32-bit aligned */
+ if (!evb2_aligned(member_offset, sizeof(uint32_t)) ||
+ !evb2_aligned(member_size, sizeof(uint32_t)))
+ return VB2_ERROR_COMMON_MEMBER_UNALIGNED;
+
+ /* Initialize minimum offset if necessary */
+ if (!*min_offset)
+ *min_offset = c->fixed_size + c->desc_size;
+
+ /* Member must be after minimum offset */
+ if (member_offset < *min_offset)
+ return VB2_ERROR_COMMON_MEMBER_OVERLAP;
+
+ /* Member must end before total size */
+ if (member_end > c->total_size)
+ return VB2_ERROR_COMMON_MEMBER_SIZE;
+
+ /* Update minimum offset for subsequent checks */
+ *min_offset = member_end;
+
+ return VB2_SUCCESS;
+}
+
+/**
+ * Return expected signature size for a signature/hash algorithm pair
+ *
+ * @param sig_alg Signature algorithm
+ * @param hash_alg Hash algorithm
+ * @return The signature size, or zero if error / unsupported algorithm.
+ */
+static uint32_t evb2_sig_size(enum vb2_signature_algorithm sig_alg,
+ enum vb2_hash_algorithm hash_alg)
+{
+ uint32_t digest_size = vb2_digest_size(hash_alg);
+
+ /* Fail if we don't support the hash algorithm */
+ if (!digest_size)
+ return 0;
+
+ /* Handle unsigned hashes */
+ if (sig_alg == VB2_SIG_NONE)
+ return digest_size;
+
+ return evb2_rsa_sig_size(sig_alg);
+}
+
+/**
+ * Return the signature data for a signature
+ */
+static uint8_t *evb21_signature_data(struct evb21_signature *sig)
+{
+ return (uint8_t *)sig + sig->sig_offset;
+}
+
+/**
+ * Verify a signature against an expected hash digest.
+ *
+ * @param key Key to use in signature verification
+ * @param sig Signature to verify (may be destroyed in process)
+ * @param digest Digest of signed data
+ * @param wb Work buffer
+ * @return VB2_SUCCESS, or non-zero if error.
+ */
+static vb2_error_t evb21_verify_digest(const struct evb2_public_key *key,
+ struct evb21_signature *sig,
+ const uint8_t *digest,
+ const struct evb2_workbuf *wb)
+{
+ uint32_t key_sig_size = evb2_sig_size(key->sig_alg, key->hash_alg);
+
+ /* If we can't figure out the signature size, key algorithm was bad */
+ if (!key_sig_size)
+ return VB2_ERROR_VDATA_ALGORITHM;
+
+ /* Make sure the signature and key algorithms match */
+ if (key->sig_alg != sig->sig_alg || key->hash_alg != sig->hash_alg)
+ return VB2_ERROR_VDATA_ALGORITHM_MISMATCH;
+
+ if (sig->sig_size != key_sig_size)
+ return VB2_ERROR_VDATA_SIG_SIZE;
+
+ if (key->sig_alg == VB2_SIG_NONE) {
+ /* Bare hash */
+ if (evb2_safe_memcmp(evb21_signature_data(sig),
+ digest, key_sig_size))
+ return VB2_ERROR_VDATA_VERIFY_DIGEST;
+
+ return VB2_SUCCESS;
+ } else {
+ /* RSA-signed digest */
+ return evb2_rsa_verify_digest(key,
+ evb21_signature_data(sig),
+ digest, wb);
+ }
+}
+
+/**
+ * Return the size of a pre-processed RSA public key.
+ *
+ * @param sig_alg Signature algorithm
+ * @return The size of the preprocessed key in bytes, or 0 if error.
+ */
+static uint32_t evb2_packed_key_size(enum vb2_signature_algorithm sig_alg)
+{
+ uint32_t sig_size = evb2_rsa_sig_size(sig_alg);
+
+ if (!sig_size)
+ return 0;
+
+ /*
+ * Total size needed by a RSAPublicKey buffer is =
+ * 2 * key_len bytes for the n and rr arrays
+ * + sizeof len + sizeof n0inv.
+ */
+ return 2 * sig_size + 2 * sizeof(uint32_t);
+}
+
+/**
+ * Unpack the RSA data fields for a public key
+ *
+ * This is called by evb21_unpack_key() to extract the arrays from a packed key.
+ * These elements of *key will point inside the key_data buffer.
+ *
+ * @param key Destination key for RSA data fields
+ * @param key_data Packed key data (from inside a packed key buffer)
+ * @param key_size Size of packed key data in bytes
+ */
+static vb2_error_t evb2_unpack_key_data(struct evb2_public_key *key,
+ const uint8_t *key_data,
+ uint32_t key_size)
+{
+ const uint32_t *buf32 = (const uint32_t *)key_data;
+ uint32_t expected_key_size = evb2_packed_key_size(key->sig_alg);
+
+ /* Make sure buffer is the correct length */
+ if (!expected_key_size || expected_key_size != key_size) {
+ EVB2_DEBUG("Wrong key size for algorithm\n");
+ return VB2_ERROR_UNPACK_KEY_SIZE;
+ }
+
+ /* Check for alignment */
+ if (!evb2_aligned(buf32, sizeof(uint32_t)))
+ return VB2_ERROR_UNPACK_KEY_ALIGN;
+
+ key->arrsize = buf32[0];
+
+ /* Sanity check key array size */
+ if (key->arrsize * sizeof(uint32_t) != evb2_rsa_sig_size(key->sig_alg))
+ return VB2_ERROR_UNPACK_KEY_ARRAY_SIZE;
+
+ key->n0inv = buf32[1];
+
+ /* Arrays point inside the key data */
+ key->n = buf32 + 2;
+ key->rr = buf32 + 2 + key->arrsize;
+
+ return VB2_SUCCESS;
+}
+
+vb2_error_t evb21_unpack_key(struct evb2_public_key *key, const uint8_t *buf,
+ uint32_t size)
+{
+ const struct evb21_packed_key *pkey =
+ (const struct evb21_packed_key *)buf;
+ uint32_t sig_size;
+ uint32_t min_offset = 0;
+ vb2_error_t rv;
+
+ /* Check magic number */
+ if (pkey->c.magic != VB21_MAGIC_PACKED_KEY)
+ return VB2_ERROR_UNPACK_KEY_MAGIC;
+
+ rv = evb21_verify_common_header(buf, size);
+ if (rv)
+ return rv;
+
+ /* Make sure key data is inside */
+ rv = evb21_verify_common_member(pkey, &min_offset,
+ pkey->key_offset, pkey->key_size);
+ if (rv)
+ return rv;
+
+ /*
+ * Check for compatible version. No need to check minor version, since
+ * that's compatible across readers matching the major version, and we
+ * haven't added any new fields.
+ */
+ if (pkey->c.struct_version_major != VB21_PACKED_KEY_VERSION_MAJOR)
+ return VB2_ERROR_UNPACK_KEY_STRUCT_VERSION;
+
+ /* Copy key algorithms */
+ key->hash_alg = pkey->hash_alg;
+ if (!vb2_digest_size(key->hash_alg))
+ return VB2_ERROR_UNPACK_KEY_HASH_ALGORITHM;
+
+ key->sig_alg = pkey->sig_alg;
+ if (key->sig_alg != VB2_SIG_NONE) {
+ sig_size = evb2_rsa_sig_size(key->sig_alg);
+ if (!sig_size)
+ return VB2_ERROR_UNPACK_KEY_SIG_ALGORITHM;
+ rv = evb2_unpack_key_data(
+ key,
+ (const uint8_t *)pkey + pkey->key_offset,
+ pkey->key_size);
+ if (rv)
+ return rv;
+ }
+
+ /* Key description */
+ key->desc = evb21_common_desc(pkey);
+ key->version = pkey->key_version;
+ key->id = &pkey->id;
+
+ return VB2_SUCCESS;
+}
+
+uint32_t evb2_rsa_sig_size(enum vb2_signature_algorithm sig_alg)
+{
+ switch (sig_alg) {
+ case VB2_SIG_RSA1024:
+ return 1024 / 8;
+ case VB2_SIG_RSA2048:
+ case VB2_SIG_RSA2048_EXP3:
+ return 2048 / 8;
+ case VB2_SIG_RSA3072_EXP3:
+ return 3072 / 8;
+ case VB2_SIG_RSA4096:
+ return 4096 / 8;
+ case VB2_SIG_RSA8192:
+ return 8192 / 8;
+ default:
+ return 0;
+ }
+}
+
+vb2_error_t evb21_verify_data(const void *data, uint32_t size,
+ struct evb21_signature *sig,
+ const struct evb2_public_key *key,
+ const struct evb2_workbuf *wb)
+{
+ struct evb2_workbuf wblocal = *wb;
+ struct vb2_digest_context *dc;
+ uint8_t *digest;
+ uint32_t digest_size;
+ vb2_error_t rv;
+
+ if (sig->data_size != size) {
+ EVB2_DEBUG("Wrong amount of data signed.\n");
+ return VB2_ERROR_VDATA_SIZE;
+ }
+
+ /* Digest goes at start of work buffer */
+ digest_size = vb2_digest_size(key->hash_alg);
+ if (!digest_size)
+ return VB2_ERROR_VDATA_DIGEST_SIZE;
+
+ digest = evb2_workbuf_alloc(&wblocal, digest_size);
+ if (!digest)
+ return VB2_ERROR_VDATA_WORKBUF_DIGEST;
+
+ /* Hashing requires temp space for the context */
+ dc = evb2_workbuf_alloc(&wblocal, sizeof(*dc));
+ if (!dc)
+ return VB2_ERROR_VDATA_WORKBUF_HASHING;
+
+ rv = vb2_digest_init(dc, key->hash_alg);
+ if (rv)
+ return rv;
+
+ rv = vb2_digest_extend(dc, data, size);
+ if (rv)
+ return rv;
+
+ rv = vb2_digest_finalize(dc, digest, digest_size);
+ if (rv)
+ return rv;
+
+ evb2_workbuf_free(&wblocal, sizeof(*dc));
+
+ return evb21_verify_digest(key, sig, digest, &wblocal);
+}
diff --git a/src/vendorcode/eltan/security/verified_boot/eltan_vb21.h b/src/vendorcode/eltan/security/verified_boot/eltan_vb21.h
new file mode 100644
index 0000000..c2f7982
--- /dev/null
+++ b/src/vendorcode/eltan/security/verified_boot/eltan_vb21.h
@@ -0,0 +1,241 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef ELTAN_VB21_H
+#define ELTAN_VB21_H
+
+#include <vb2_api.h>
+#include <vb2_sha.h>
+
+#define EVB2_DEBUG(format, args...) \
+ printk(BIOS_INFO, format, ## args)
+
+/* Check if a pointer is aligned on an align-byte boundary */
+#define evb2_aligned(ptr, align) (!(((uintptr_t)(ptr)) & ((align) - 1)))
+
+/*
+ * Magic numbers used by evb21_struct_common.magic.
+ *
+ * All valid numbers should be listed here to avoid accidental overlap.
+ * Numbers start at a large value, so that previous parsers (which stored
+ * things like lengths and offsets at that field) will detect and reject new
+ * structs as invalid.
+ */
+enum evb21_struct_common_magic {
+ /* "Vb2P" = evb21_packed_key.c.magic */
+ VB21_MAGIC_PACKED_KEY = 0x50326256,
+};
+
+/* Work buffer */
+struct evb2_workbuf {
+ uint8_t *buf;
+ uint32_t size;
+};
+
+#define EVB2_ID_NUM_BYTES 20
+
+struct evb2_id {
+ uint8_t raw[EVB2_ID_NUM_BYTES];
+} __attribute__((packed));
+
+/* Public key structure in RAM */
+struct evb2_public_key {
+ uint32_t arrsize; /* Length of n[] and rr[] in number of uint32_t */
+ uint32_t n0inv; /* -1 / n[0] mod 2^32 */
+ const uint32_t *n; /* Modulus as little endian array */
+ const uint32_t *rr; /* R^2 as little endian array */
+ enum vb2_signature_algorithm sig_alg; /* Signature algorithm */
+ enum vb2_hash_algorithm hash_alg; /* Hash algorithm */
+ const char *desc; /* Description */
+ uint32_t version; /* Key version */
+ const struct evb2_id *id; /* Key ID */
+};
+
+/*
+ * Generic struct header for all vboot2.1 structs. This makes it easy to
+ * automatically parse and identify vboot structs (e.g., in futility). This
+ * must be the first member of the parent vboot2.1 struct.
+ */
+struct evb21_struct_common {
+ /* Magic number; see evb21_struct_common_magic for expected values */
+ uint32_t magic;
+
+ /*
+ * Parent struct version; see each struct for the expected value.
+ *
+ * How to handle struct version mismatches, if the parser is version
+ * A.b and the data is version C.d:
+ * 1) If A.b == C.d, we're good.
+ * 2) If A != C, the data cannot be parsed at all.
+ * 3) If b < d, C.d is a newer version of data which is backwards-
+ * compatible to old parsers. We're good.
+ * 4) If b > d, C.d is an older version of data. The parser should
+ * use default values for fields added after version d. We're
+ * good.
+ *
+ * Struct versions start at 3.0, since the highest version of the old
+ * structures was 2.1. This way, there is no possibility of collision
+ * for old code which depends on the version number.
+ */
+ uint16_t struct_version_major;
+ uint16_t struct_version_minor;
+
+ /*
+ * Size of the parent structure and all its data, including the
+ * description and any necessary padding. That is, all data must lie
+ * in a contiguous region of <total_size> bytes starting at the first
+ * byte of this header.
+ */
+ uint32_t total_size;
+
+ /*
+ * Size of the fixed portion of the parent structure. If a description
+ * is present, it must start at this offset.
+ */
+ uint32_t fixed_size;
+
+ /*
+ * The object may contain an ASCII description following the fixed
+ * portion of the structure. If it is present, it must be
+ * null-terminated, and padded with 0 (null) bytes to a multiple of 32
+ * bits.
+ *
+ * Size of ASCII description in bytes, counting null terminator and
+ * padding (if any). Set 0 if no description is present. If non-zero,
+ * there must be a null terminator (0) at offset (fixed_size +
+ * desc_size - 1).
+ */
+ uint32_t desc_size;
+} __attribute__((packed));
+
+/*
+ * Signature data
+ *
+ * The signature data must be arranged like this:
+ * 1) evb21_signature header struct h
+ * 2) Signature description (pointed to by h.c.fixed_size)
+ * 3) Signature data (pointed to by h.sig_offset)
+ */
+struct evb21_signature {
+ /* Common header fields */
+ struct evb21_struct_common c;
+
+ /* Offset of signature data from start of this struct */
+ uint32_t sig_offset;
+
+ /* Size of signature data in bytes */
+ uint32_t sig_size;
+
+ /* Size of the data block which was signed in bytes */
+ uint32_t data_size;
+
+ /* Signature algorithm used (enum vb2_signature_algorithm) */
+ uint16_t sig_alg;
+
+ /* Hash digest algorithm used (enum vb2_hash_algorithm) */
+ uint16_t hash_alg;
+
+ /*
+ * ID for the signature.
+ *
+ * If this is a keyblock signature entry, this is the ID of the key
+ * used to generate this signature. This allows the firmware to
+ * quickly determine which signature block (if any) goes with the key
+ * being used by the firmware.
+ *
+ * If this is a preamble hash entry, this is the ID of the data type
+ * being hashed. There is no key ID, because sig_alg=VB2_ALG_NONE.
+ */
+ struct evb2_id id;
+} __attribute__((packed));
+
+/* Current version of evb21_packed_key struct */
+#define VB21_PACKED_KEY_VERSION_MAJOR 3
+#define VB21_PACKED_KEY_VERSION_MINOR 0
+
+/*
+ * Packed public key data
+ *
+ * The key data must be arranged like this:
+ * 1) evb21_packed_key header struct h
+ * 2) Key description (pointed to by h.c.fixed_size)
+ * 3) Key data key (pointed to by h.key_offset)
+ */
+struct evb21_packed_key {
+ /* Common header fields */
+ struct evb21_struct_common c;
+
+ /* Offset of key data from start of this struct */
+ uint32_t key_offset;
+
+ /* Size of key data in bytes (NOT strength of key in bits) */
+ uint32_t key_size;
+
+ /* Signature algorithm used by the key (enum vb2_signature_algorithm) */
+ uint16_t sig_alg;
+
+ /*
+ * Hash digest algorithm used with the key (enum vb2_hash_algorithm).
+ * This is explicitly specified as part of the key to prevent use of a
+ * strong key with a weak hash.
+ */
+ uint16_t hash_alg;
+
+ /* Key version */
+ uint32_t key_version;
+
+ /* Key ID */
+ struct evb2_id id;
+} __attribute__((packed));
+
+/**
+ * Unpack a key for use in verification
+ *
+ * The elements of the unpacked key will point into the source buffer, so don't
+ * free the source buffer until you're done with the key.
+ *
+ * @param key Destintion for unpacked key
+ * @param buf Source buffer containing packed key
+ * @param size Size of buffer in bytes
+ * @return VB2_SUCCESS, or non-zero error code if error.
+ */
+vb2_error_t evb21_unpack_key(struct evb2_public_key *key, const uint8_t *buf,
+ uint32_t size);
+
+/**
+ * Verify data matches signature.
+ *
+ * @param data Data to verify
+ * @param size Size of data buffer. Note that amount of data to
+ * actually validate is contained in sig->data_size.
+ * @param sig Signature of data (destroyed in process)
+ * @param key Key to use to validate signature
+ * @param wb Work buffer
+ * @return VB2_SUCCESS, or non-zero error code if error.
+ */
+vb2_error_t evb21_verify_data(const void *data, uint32_t size,
+ struct evb21_signature *sig,
+ const struct evb2_public_key *key,
+ const struct evb2_workbuf *wb);
+
+/**
+ * Return the size of a RSA signature
+ *
+ * @param sig_alg Signature algorithm
+ * @return The size of the signature in bytes, or 0 if error.
+ */
+uint32_t evb2_rsa_sig_size(enum vb2_signature_algorithm sig_alg);
+
+#endif //ELTAN_VB21_H
diff --git a/src/vendorcode/eltan/security/verified_boot/vboot_check.c b/src/vendorcode/eltan/security/verified_boot/vboot_check.c
index bc502c9..7d39a44 100644
--- a/src/vendorcode/eltan/security/verified_boot/vboot_check.c
+++ b/src/vendorcode/eltan/security/verified_boot/vboot_check.c
@@ -16,8 +16,10 @@
#include <boot_device.h>
#include <bootmem.h>
#include <cbfs.h>
-#include <vboot_check.h>
-#include <vboot_common.h>
+#include <security/vboot/vboot_common.h>
+#include <vb2_sha.h>
+#include <vendorcode/eltan/security/verified_boot/vboot_check.h>
+#include <vendorcode/eltan/security/verified_boot/eltan_vb21.h>
#define RSA_PUBLICKEY_FILE_NAME "vboot_public_key.bin"
@@ -32,11 +34,11 @@
int verified_boot_check_manifest(void)
{
uint8_t *buffer;
- uint8_t sig_buffer[1024]; /* used to build vb21_signature */
+ uint8_t sig_buffer[1024]; /* used to build evb21_signature */
size_t size = 0;
- struct vb2_public_key key;
- struct vb2_workbuf wb;
- struct vb21_signature *vb2_sig_hdr = (struct vb21_signature *)sig_buffer;
+ struct evb2_public_key key;
+ struct evb2_workbuf wb;
+ struct evb21_signature *evb2_sig_hdr = (struct evb21_signature *)sig_buffer;
uint8_t wb_buffer[1024];
buffer = cbfs_boot_map_with_leak(RSA_PUBLICKEY_FILE_NAME, CBFS_TYPE_RAW, &size);
@@ -51,14 +53,14 @@
goto fail;
}
- if (vb21_unpack_key(&key, buffer, size)) {
+ if (evb21_unpack_key(&key, buffer, size)) {
printk(BIOS_ERR, "ERROR: Invalid public key!\n");
goto fail;
}
cbfs_boot_map_with_leak("oemmanifest.bin", CBFS_TYPE_RAW, &size);
if (size != (CONFIG_VENDORCODE_ELTAN_OEM_MANIFEST_ITEMS * DIGEST_SIZE) +
- vb2_rsa_sig_size(VB2_SIG_RSA2048)) {
+ evb2_rsa_sig_size(VB2_SIG_RSA2048)) {
printk(BIOS_ERR, "ERROR: Incorrect manifest size!\n");
goto fail;
}
@@ -67,18 +69,18 @@
wb.buf = (uint8_t *)&wb_buffer;
wb.size = sizeof(wb_buffer);
- /* Build vb2_sig_hdr buffer */
- vb2_sig_hdr->sig_offset = sizeof(struct vb21_signature) +
+ /* Build evb2_sig_hdr buffer */
+ evb2_sig_hdr->sig_offset = sizeof(struct evb21_signature) +
(CONFIG_VENDORCODE_ELTAN_OEM_MANIFEST_ITEMS * DIGEST_SIZE);
- vb2_sig_hdr->sig_alg = VB2_SIG_RSA2048;
- vb2_sig_hdr->sig_size = vb2_rsa_sig_size(VB2_SIG_RSA2048);
- vb2_sig_hdr->hash_alg = HASH_ALG;
- vb2_sig_hdr->data_size = CONFIG_VENDORCODE_ELTAN_OEM_MANIFEST_ITEMS * DIGEST_SIZE;
- memcpy(&sig_buffer[sizeof(struct vb21_signature)],
+ evb2_sig_hdr->sig_alg = VB2_SIG_RSA2048;
+ evb2_sig_hdr->sig_size = evb2_rsa_sig_size(VB2_SIG_RSA2048);
+ evb2_sig_hdr->hash_alg = HASH_ALG;
+ evb2_sig_hdr->data_size = CONFIG_VENDORCODE_ELTAN_OEM_MANIFEST_ITEMS * DIGEST_SIZE;
+ memcpy(&sig_buffer[sizeof(struct evb21_signature)],
(uint8_t *)CONFIG_VENDORCODE_ELTAN_OEM_MANIFEST_LOC, size);
- if (vb21_verify_data(&sig_buffer[sizeof(struct vb21_signature)], vb2_sig_hdr->data_size,
- (struct vb21_signature *)&sig_buffer, &key, &wb)) {
+ if (evb21_verify_data(&sig_buffer[sizeof(struct evb21_signature)], evb2_sig_hdr->data_size,
+ (struct evb21_signature *)&sig_buffer, &key, &wb)) {
printk(BIOS_ERR, "ERROR: Signature verification failed for hash table\n");
goto fail;
}
--
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Gerrit-Change-Id: Iae58a0c42161ddfec9908f9867286e3dc1f055a2
Gerrit-Change-Number: 37654
Gerrit-PatchSet: 1
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4
12
Change in coreboot[master]: soc/intel/common/systemagent: Add SOC_INTEL_COMMON_BLOCK_SA_VERSION_2
by Subrata Banik (Code Review) 07 Aug '23
by Subrata Banik (Code Review) 07 Aug '23
07 Aug '23
Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38456 )
Change subject: soc/intel/common/systemagent: Add SOC_INTEL_COMMON_BLOCK_SA_VERSION_2
......................................................................
soc/intel/common/systemagent: Add SOC_INTEL_COMMON_BLOCK_SA_VERSION_2
System Agent (SA) register 0x60:PCIEXBAR register LENGTH offset definition has
been changed for newer SoC. This change provides a new Kconfig option that
can be selected by SoCs using these new bit definitions of LENGTH. Common code
takes care of setting the right value for pciex length depending upon the version
selected by SOC.
TEST=DSDT dump shows PCIEXBAR.LENGTH offset (3:1) for TGL
Change-Id: Ifa00c4e6b872896ace975f1c6bd56c6efb172410
Signed-off-by: Subrata Banik <subrata.banik(a)intel.com>
---
M src/soc/intel/common/block/acpi/acpi/northbridge.asl
M src/soc/intel/common/block/systemagent/Kconfig
M src/soc/intel/common/block/systemagent/systemagent_def.h
M src/soc/intel/common/block/systemagent/systemagent_early.c
4 files changed, 62 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/38456/1
diff --git a/src/soc/intel/common/block/acpi/acpi/northbridge.asl b/src/soc/intel/common/block/acpi/acpi/northbridge.asl
index d271dda..ac9e843 100644
--- a/src/soc/intel/common/block/acpi/acpi/northbridge.asl
+++ b/src/soc/intel/common/block/acpi/acpi/northbridge.asl
@@ -40,8 +40,13 @@
Offset(0x60), /* PCIEXBAR (0:0:0:60) */
PXEN, 1, /* Enable */
- PXSZ, 2, /* PCI Express Size */
+#if CONFIG(SOC_INTEL_COMMON_BLOCK_SA_VERSION_2)
+ PXSZ, 3, /* PCI Express Size */
+ , 22,
+#else
+ PXSZ, 2, /* PCI Express Size */
, 23,
+#endif
PXBR, 6, /* PCI Express BAR [31:26] */
Offset(0x68), /* DMIBAR (0:0:0:68) */
@@ -241,7 +246,15 @@
/* Get PCIe Length */
Method (GPCL, 0, Serialized)
{
+#if CONFIG(SOC_INTEL_COMMON_BLOCK_SA_VERSION_2)
+ If (LLess (\_SB.PCI0.MCHC.PXSZ, 3)) {
+ ShiftRight (0x10000000, \_SB.PCI0.MCHC.PXSZ, Local0)
+ } Else {
+ Store(0x10000000, Local0)
+ }
+#else
ShiftRight (0x10000000, \_SB.PCI0.MCHC.PXSZ, Local0)
+#endif
Return (Local0)
}
diff --git a/src/soc/intel/common/block/systemagent/Kconfig b/src/soc/intel/common/block/systemagent/Kconfig
index 1222573..017d85e 100644
--- a/src/soc/intel/common/block/systemagent/Kconfig
+++ b/src/soc/intel/common/block/systemagent/Kconfig
@@ -3,12 +3,24 @@
help
Intel Processor common System Agent support
+config SOC_INTEL_COMMON_BLOCK_SA_VERSION_2
+ bool
+ default n
+ select SOC_INTEL_COMMON_BLOCK_SA
+ help
+ Intel Processor Common System Agent support version 2 to handle
+ DRAM changes introduced in TGL.
+
config MMCONF_BASE_ADDRESS
hex
default 0xe0000000
config SA_PCIEX_LENGTH
hex
+ default 0x100000000 if (PCIEX_LENGTH_4096MB)
+ default 0x80000000 if (PCIEX_LENGTH_2048MB)
+ default 0x40000000 if (PCIEX_LENGTH_1024MB)
+ default 0x20000000 if (PCIEX_LENGTH_512MB)
default 0x10000000 if (PCIEX_LENGTH_256MB)
default 0x8000000 if (PCIEX_LENGTH_128MB)
default 0x4000000 if (PCIEX_LENGTH_64MB)
@@ -16,6 +28,22 @@
help
This option allows you to select length of PCIEX region.
+if SOC_INTEL_COMMON_BLOCK_SA_VERSION_2
+
+config PCIEX_LENGTH_4096MB
+ bool
+
+config PCIEX_LENGTH_2048MB
+ bool
+
+config PCIEX_LENGTH_1024MB
+ bool
+
+config PCIEX_LENGTH_512MB
+ bool
+
+endif
+
config PCIEX_LENGTH_256MB
bool
diff --git a/src/soc/intel/common/block/systemagent/systemagent_def.h b/src/soc/intel/common/block/systemagent/systemagent_def.h
index b89a10d..5f54c72 100644
--- a/src/soc/intel/common/block/systemagent/systemagent_def.h
+++ b/src/soc/intel/common/block/systemagent/systemagent_def.h
@@ -31,6 +31,12 @@
#define DPR_PRS (1 << 1)
#define DPR_SIZE_MASK 0xff0
+#if CONFIG(SOC_INTEL_COMMON_BLOCK_SA_VERSION_2)
+#define PCIEXBAR_LENGTH_4096MB 6
+#define PCIEXBAR_LENGTH_2048MB 5
+#define PCIEXBAR_LENGTH_1024MB 4
+#define PCIEXBAR_LENGTH_512MB 3
+#endif
#define PCIEXBAR_LENGTH_64MB 2
#define PCIEXBAR_LENGTH_128MB 1
#define PCIEXBAR_LENGTH_256MB 0
diff --git a/src/soc/intel/common/block/systemagent/systemagent_early.c b/src/soc/intel/common/block/systemagent/systemagent_early.c
index d6f129d..f0a867a 100644
--- a/src/soc/intel/common/block/systemagent/systemagent_early.c
+++ b/src/soc/intel/common/block/systemagent/systemagent_early.c
@@ -40,6 +40,20 @@
/* Get PCI Express Region Length */
switch (CONFIG_SA_PCIEX_LENGTH) {
+#if CONFIG(SOC_INTEL_COMMON_BLOCK_SA_VERSION_2)
+ case 4096 * MiB:
+ pciexbar_length = PCIEXBAR_LENGTH_4096MB;
+ break;
+ case 2048 * MiB:
+ pciexbar_length = PCIEXBAR_LENGTH_2048MB;
+ break;
+ case 1024 * MiB:
+ pciexbar_length = PCIEXBAR_LENGTH_1024MB;
+ break;
+ case 512 * MiB:
+ pciexbar_length = PCIEXBAR_LENGTH_512MB;
+ break;
+#endif
case 256 * MiB:
pciexbar_length = PCIEXBAR_LENGTH_256MB;
break;
--
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Gerrit-Change-Id: Ifa00c4e6b872896ace975f1c6bd56c6efb172410
Gerrit-Change-Number: 38456
Gerrit-PatchSet: 1
Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>
Gerrit-MessageType: newchange
7
41
Change in coreboot[master]: Helios: Add fan speed control for TSR3 sensor with DPTF settings
by Sumeet R Pawnikar (Code Review) 07 Aug '23
by Sumeet R Pawnikar (Code Review) 07 Aug '23
07 Aug '23
Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41425 )
Change subject: Helios: Add fan speed control for TSR3 sensor with DPTF settings
......................................................................
Helios: Add fan speed control for TSR3 sensor with DPTF settings
Add granular fan speed control for TSR3 sensor which is used for CPU cooling.
Update passive temperature threshold from 44C to 62C for the same TSR3 sensor.
BRANCH=firmware-hatch-12672.B
BUG=b:155347298
TEST=Built and test on Helios system
Change-Id: Ia545ce2c072d48a9a351fe3ad7ea66fe55f80e64
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com>
---
M src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl
1 file changed, 9 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/41425/1
diff --git a/src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl
index 886e519..8ac1c0b 100644
--- a/src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl
+++ b/src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl
@@ -26,8 +26,15 @@
#define DPTF_TSR3_SENSOR_ID 3
#define DPTF_TSR3_SENSOR_NAME "CPU"
-#define DPTF_TSR3_PASSIVE 44
+#define DPTF_TSR3_PASSIVE 62
#define DPTF_TSR3_CRITICAL 90
+#define DPTF_TSR3_ACTIVE_AC0 60
+#define DPTF_TSR3_ACTIVE_AC1 57
+#define DPTF_TSR3_ACTIVE_AC2 55
+#define DPTF_TSR3_ACTIVE_AC3 52
+#define DPTF_TSR3_ACTIVE_AC4 50
+#define DPTF_TSR3_ACTIVE_AC5 48
+#define DPTF_TSR3_ACTIVE_AC6 45
#define DPTF_ENABLE_CHARGER
#define DPTF_ENABLE_FAN_CONTROL
@@ -83,7 +90,7 @@
0, 0, 0
},
Package () {
- \_SB.DPTF.TFN1, \_SB.DPTF.TSR3, 100, 0, 0, 0, 0, 0, 0, 0,
+ \_SB.DPTF.TFN1, \_SB.DPTF.TSR3, 100, 90, 80, 60, 40, 30, 20, 10,
0, 0, 0
}
})
--
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Gerrit-Branch: master
Gerrit-Change-Id: Ia545ce2c072d48a9a351fe3ad7ea66fe55f80e64
Gerrit-Change-Number: 41425
Gerrit-PatchSet: 1
Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com>
Gerrit-MessageType: newchange
7
14
Change in coreboot[master]: security/intel/txt: Remove SINIT ACM alignment
by Arthur Heymans (Code Review) 07 Aug '23
by Arthur Heymans (Code Review) 07 Aug '23
07 Aug '23
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48735 )
Change subject: security/intel/txt: Remove SINIT ACM alignment
......................................................................
security/intel/txt: Remove SINIT ACM alignment
This binary must be decompressed anyway so there is no need for
alignment.
Change-Id: Ia46207cce992ccd602da575ced643cc04ea1c8b3
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/security/intel/txt/Makefile.inc
1 file changed, 0 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/48735/1
diff --git a/src/security/intel/txt/Makefile.inc b/src/security/intel/txt/Makefile.inc
index 77a5f69..577dba2 100644
--- a/src/security/intel/txt/Makefile.inc
+++ b/src/security/intel/txt/Makefile.inc
@@ -22,7 +22,6 @@
cbfs-files-y += $(CONFIG_INTEL_TXT_CBFS_SINIT_ACM)
$(CONFIG_INTEL_TXT_CBFS_SINIT_ACM)-file := $(CONFIG_INTEL_TXT_SINITACM_FILE)
$(CONFIG_INTEL_TXT_CBFS_SINIT_ACM)-type := raw
-$(CONFIG_INTEL_TXT_CBFS_SINIT_ACM)-align := 0x10
$(CONFIG_INTEL_TXT_CBFS_SINIT_ACM)-compression := lzma
endif
--
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Gerrit-Change-Id: Ia46207cce992ccd602da575ced643cc04ea1c8b3
Gerrit-Change-Number: 48735
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-MessageType: newchange
2
1