coreboot-gerrit June 2022

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Change in coreboot[master]: nb/intel/ironlake: Account for TSEG alignment
by Angel Pons (Code Review) 07 Aug '23

07 Aug '23

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45920 ) Change subject: nb/intel/ironlake: Account for TSEG alignment ...................................................................... nb/intel/ironlake: Account for TSEG alignment The TSEGMB register has 1 MiB granularity, but do not rely on reserved bits being zero. Raminit aligns TSEG to a 8 MiB boundary, anyway. Change-Id: Iedb63f7c7a29172da187030e33197fc6e4ee23f8 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/ironlake/memmap.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/45920/1 diff --git a/src/northbridge/intel/ironlake/memmap.c b/src/northbridge/intel/ironlake/memmap.c index 78fbae8..221ae92 100644 --- a/src/northbridge/intel/ironlake/memmap.c +++ b/src/northbridge/intel/ironlake/memmap.c @@ -14,7 +14,7 @@ static uintptr_t northbridge_get_tseg_base(void) { /* Base of TSEG is top of usable DRAM */ - return pci_read_config32(PCI_DEV(0, 0, 0), TSEG); + return ALIGN_DOWN(pci_read_config32(PCI_DEV(0, 0, 0), TSEG), 1 * MiB); } static size_t northbridge_get_tseg_size(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/45920 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iedb63f7c7a29172da187030e33197fc6e4ee23f8 Gerrit-Change-Number: 45920 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 1

Change in coreboot[master]: [TESTONLY] .checkpatch.conf: Check SPDX license headers
by Angel Pons (Code Review) 07 Aug '23

07 Aug '23

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46320 ) Change subject: [TESTONLY] .checkpatch.conf: Check SPDX license headers ...................................................................... [TESTONLY] .checkpatch.conf: Check SPDX license headers Change-Id: Ie6d4e019dde23c8d8c3211fff1c19967b0ce7c8a Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M .checkpatch.conf 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/46320/1 diff --git a/.checkpatch.conf b/.checkpatch.conf index c294e7b..ac2e530 100644 --- a/.checkpatch.conf +++ b/.checkpatch.conf @@ -17,7 +17,6 @@ --ignore CONFIG_DESCRIPTION --ignore MISSING_SPACE --ignore CORRUPTED_PATCH ---ignore SPDX_LICENSE_TAG --ignore UNDOCUMENTED_DT_STRING --ignore PRINTK_WITHOUT_KERN_LEVEL -- To view, visit https://review.coreboot.org/c/coreboot/+/46320 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie6d4e019dde23c8d8c3211fff1c19967b0ce7c8a Gerrit-Change-Number: 46320 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: mb/google/dedede: Enable PCI device 14.2
by Meera Ravindranath (Code Review) 07 Aug '23

07 Aug '23

Meera Ravindranath has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46550 ) Change subject: mb/google/dedede: Enable PCI device 14.2 ...................................................................... mb/google/dedede: Enable PCI device 14.2 Enable PCI device 14.2 to align with kernel Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com> Change-Id: I3eb32218041263f0abef8b9dd4c52efb17289fd7 --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/46550/1 diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index b7aa11d..7236547 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -304,7 +304,7 @@ end end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) - device pci 14.2 off end # PMC SRAM + device pci 14.2 on end # PMC SRAM chip drivers/wifi/generic register "wake" = "GPE0_PME_B0" device pci 14.3 on end # CNVi wifi -- To view, visit https://review.coreboot.org/c/coreboot/+/46550 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3eb32218041263f0abef8b9dd4c52efb17289fd7 Gerrit-Change-Number: 46550 Gerrit-PatchSet: 1 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-MessageType: newchange

7 22

Change in coreboot[master]: mb/prodrive/hermes: Clean header files
by Patrick Rudolph (Code Review) 07 Aug '23

07 Aug '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46564 ) Change subject: mb/prodrive/hermes: Clean header files ...................................................................... mb/prodrive/hermes: Clean header files Change-Id: I79655a262d92a2e870d131ba7907bd0e94b98071 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/prodrive/hermes/eeprom.c M src/mainboard/prodrive/hermes/mainboard.c M src/mainboard/prodrive/hermes/variants/baseboard/include/eeprom.h 3 files changed, 7 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/46564/1 diff --git a/src/mainboard/prodrive/hermes/eeprom.c b/src/mainboard/prodrive/hermes/eeprom.c index 763f8bd..5aee54a 100644 --- a/src/mainboard/prodrive/hermes/eeprom.c +++ b/src/mainboard/prodrive/hermes/eeprom.c @@ -4,6 +4,9 @@ #include <console/console.h> #include <device/smbus_host.h> #include <crc_byte.h> +#include <soc/intel/common/block/smbus/smbuslib.h> +#include <soc/pci_devs.h> +#include <string.h> #include "variants/baseboard/include/eeprom.h" /* @@ -63,7 +66,7 @@ #endif u32 smb_ctrl_reg = pci_read_config32(dev, HOSTC); - pci_write_config32(dev, HOSTC, smb_ctrl_reg | HOSTC_I2C_EN); + pci_write_config32(dev, HOSTC, smb_ctrl_reg | I2C_EN); printk(BIOS_SPEW, "%s\tOffset: %04zx\tSize: %02zx\n", __func__, read_offset, size); diff --git a/src/mainboard/prodrive/hermes/mainboard.c b/src/mainboard/prodrive/hermes/mainboard.c index d9d89a1..9c263ee 100644 --- a/src/mainboard/prodrive/hermes/mainboard.c +++ b/src/mainboard/prodrive/hermes/mainboard.c @@ -2,6 +2,7 @@ #include <acpi/acpigen.h> #include <device/device.h> +#include <soc/soc_chip.h> #include "variants/baseboard/include/eeprom.h" #include "gpio.h" diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/include/eeprom.h b/src/mainboard/prodrive/hermes/variants/baseboard/include/eeprom.h index 17d55a4..787830e 100644 --- a/src/mainboard/prodrive/hermes/variants/baseboard/include/eeprom.h +++ b/src/mainboard/prodrive/hermes/variants/baseboard/include/eeprom.h @@ -1,10 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include <soc/ramstage.h> +#include <fsp/api.h> +#include <fsp/util.h> -#define HOSTC 0x40 -#define SMBUS_IO_BASE 0xefa0 -#define HOSTC_I2C_EN (1 << 2) #define I2C_ADDR_EEPROM 0x57 struct eeprom_board_settings { -- To view, visit https://review.coreboot.org/c/coreboot/+/46564 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I79655a262d92a2e870d131ba7907bd0e94b98071 Gerrit-Change-Number: 46564 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/jasperlake: Enable microcode update
by Sugnan Prabhu S (Code Review) 07 Aug '23

07 Aug '23

Sugnan Prabhu S has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46845 ) Change subject: mb/google/jasperlake: Enable microcode update ...................................................................... mb/google/jasperlake: Enable microcode update Adds flashmap descriptor with RW_UCODE_STAGED to enable microcode update with the top swap. Change-Id: I4afcbc0bf5f9e703260192ef7e1c6575bb5633cf Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> --- M src/mainboard/intel/jasperlake_rvp/Kconfig A src/mainboard/intel/jasperlake_rvp/chromeos-ucode.fmd M src/soc/intel/jasperlake/Kconfig M src/soc/intel/jasperlake/bootblock/report_platform.c 4 files changed, 58 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/46845/1 diff --git a/src/mainboard/intel/jasperlake_rvp/Kconfig b/src/mainboard/intel/jasperlake_rvp/Kconfig index 1125a9b..bb31330 100644 --- a/src/mainboard/intel/jasperlake_rvp/Kconfig +++ b/src/mainboard/intel/jasperlake_rvp/Kconfig @@ -73,4 +73,12 @@ config TPM_TIS_ACPI_INTERRUPT int default 45 # GPE0_DW1_13 (GPP_H13) + +config FMDFILE + string "fmap description file with RW_UCODE_STAGED area in fmd format" + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-ucode.fmd" \ + if INTEL_TOP_SWAP_MULTI_FIT_UCODE_UPDATE + help + Top swap requires a fmap file with the RW_UCODE_STAGED area. + endif diff --git a/src/mainboard/intel/jasperlake_rvp/chromeos-ucode.fmd b/src/mainboard/intel/jasperlake_rvp/chromeos-ucode.fmd new file mode 100644 index 0000000..1cf3c72 --- /dev/null +++ b/src/mainboard/intel/jasperlake_rvp/chromeos-ucode.fmd @@ -0,0 +1,44 @@ +FLASH@0xff000000 0x1000000 { + SI_ALL@0x0 0x600000 { + SI_DESC@0x0 0x1000 + SI_EC@0x1000 0x80000 + SI_ME@0x81000 0x57F000 + } + SI_BIOS@0x600000 0xA00000 { + RW_SECTION_A@0x0 0x2cc000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x2bbfc0 + RW_FWID_A@0x2cbfc0 0x40 + } + RW_SECTION_B@0x2cc000 0x2cc000 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS)@0x10000 0x2bbfc0 + RW_FWID_B@0x2cbfc0 0x40 + } + RW_MISC@0x598000 0x38000 { + RW_UCODE_STAGED(PRESERVE)@0x0 0x8000 + UNIFIED_MRC_CACHE@0x8000 0x20000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + } + RW_ELOG(PRESERVE)@0x28000 0x4000 + RW_SHARED@0x2c000 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_VPD(PRESERVE)@0x30000 0x2000 + RW_NVRAM(PRESERVE)@0x32000 0x6000 + } + RW_LEGACY(CBFS)@0x5d0000 0x30000 + WP_RO@0x600000 0x400000 { + RO_VPD(PRESERVE)@0x0 0x4000 + RO_SECTION@0x4000 0x3fc000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + GBB@0x1000 0x3000 + COREBOOT(CBFS)@0x4000 0x3f8000 + } + } + } +} diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index 8efa361..0ff4734 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -23,6 +23,7 @@ select IDT_IN_EVERY_STAGE select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP + select INTEL_TOP_SWAP_MULTI_FIT_UCODE_UPDATE select IOAPIC select MRC_SETTINGS_PROTECT select PARALLEL_MP @@ -35,6 +36,7 @@ select PMC_LOW_POWER_MODE_PROGRAM select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE + select SOC_INTEL_COMMON_BASECODE select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_ACPI select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG diff --git a/src/soc/intel/jasperlake/bootblock/report_platform.c b/src/soc/intel/jasperlake/bootblock/report_platform.c index beab782..c5e037f 100644 --- a/src/soc/intel/jasperlake/bootblock/report_platform.c +++ b/src/soc/intel/jasperlake/bootblock/report_platform.c @@ -8,6 +8,7 @@ #include <cpu/x86/name.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <intelbasecode/ucode_update.h> #include <intelblocks/mp_init.h> #include <soc/bootblock.h> #include <soc/pch.h> @@ -82,6 +83,9 @@ printk(BIOS_DEBUG, "CPU: ID %x, %s, ucode: %08x\n", cpu_id, cpu_type, get_current_microcode_rev()); + if (CONFIG(INTEL_TOP_SWAP_MULTI_FIT_UCODE_UPDATE)) + check_ucode_and_update_top_swap(); + cpu_feature_flag = cpu_get_feature_flags_ecx(); aes = (cpu_feature_flag & CPUID_AES) ? 1 : 0; txt = (cpu_feature_flag & CPUID_SMX) ? 1 : 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/46845 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4afcbc0bf5f9e703260192ef7e1c6575bb5633cf Gerrit-Change-Number: 46845 Gerrit-PatchSet: 1 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: herobrine: resolve herobrine stanadalone compilation error due to bel...
by Ravi kumar (Code Review) 07 Aug '23

07 Aug '23

Ravi kumar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46976 ) Change subject: herobrine: resolve herobrine stanadalone compilation error due to below upstream changes for trogdor ...................................................................... herobrine: resolve herobrine stanadalone compilation error due to below upstream changes for trogdor error causing with this trogdor upstream commit: "afaa3d0356d5a518442701875505901e5806bb61" trogdor: Modify DDR training to use mrc_cache Change-Id: I84552daec00519f856bf3fd19e197ebd2eec54e4 --- M src/mainboard/google/herobrine/chromeos.fmd M src/soc/qualcomm/sc7280/Kconfig 2 files changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/46976/1 diff --git a/src/mainboard/google/herobrine/chromeos.fmd b/src/mainboard/google/herobrine/chromeos.fmd index a44a638..0db83ec 100644 --- a/src/mainboard/google/herobrine/chromeos.fmd +++ b/src/mainboard/google/herobrine/chromeos.fmd @@ -11,13 +11,12 @@ RO_FRID 0x100 } RO_VPD(PRESERVE) 228K - RO_DDR_TRAINING(PRESERVE) 8K RO_LIMITS_CFG(PRESERVE) 4K } RW_VPD(PRESERVE) 32K RW_NVRAM(PRESERVE) 16K - RW_DDR_TRAINING(PRESERVE) 8K + RW_MRC_CACHE(PRESERVE) 8K RW_LIMITS_CFG(PRESERVE) 4K RW_ELOG(PRESERVE) 4K RW_SHARED 4K { diff --git a/src/soc/qualcomm/sc7280/Kconfig b/src/soc/qualcomm/sc7280/Kconfig index fc2f34b..3b1678a 100644 --- a/src/soc/qualcomm/sc7280/Kconfig +++ b/src/soc/qualcomm/sc7280/Kconfig @@ -11,6 +11,7 @@ select HAVE_MONOTONIC_TIMER select ARM64_USE_ARCH_TIMER select SOC_QUALCOMM_COMMON + select CACHE_MRC_SETTINGS if SOC_QUALCOMM_SC7280 @@ -23,5 +24,6 @@ select VBOOT_RETURN_FROM_VERSTAGE select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_BOOTBLOCK + select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN endif -- To view, visit https://review.coreboot.org/c/coreboot/+/46976 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I84552daec00519f856bf3fd19e197ebd2eec54e4 Gerrit-Change-Number: 46976 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/broadwell/northbridge.c: Use TXT DPR definition
by Angel Pons (Code Review) 07 Aug '23

07 Aug '23

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46988 ) Change subject: soc/intel/broadwell/northbridge.c: Use TXT DPR definition ...................................................................... soc/intel/broadwell/northbridge.c: Use TXT DPR definition Taken directly from Haswell. Change-Id: I06b2348e379b61af60336ea1c4722bcddd953ebc Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/northbridge.c 1 file changed, 11 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/46988/1 diff --git a/src/soc/intel/broadwell/northbridge.c b/src/soc/intel/broadwell/northbridge.c index eb8b5f0..4e75721 100644 --- a/src/soc/intel/broadwell/northbridge.c +++ b/src/soc/intel/broadwell/northbridge.c @@ -8,6 +8,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <security/intel/txt/txt_register.h> #include <vendorcode/google/chromeos/chromeos.h> #include <soc/intel/broadwell/memmap.h> #include <cpu/intel/haswell/haswell.h> @@ -266,8 +267,6 @@ unsigned long base_k, size_k, touud_k, index; struct resource *resource; uint64_t mc_values[NUM_MAP_ENTRIES]; - unsigned long dpr_size = 0; - u32 dpr_reg; /* Read in the MAP registers and report their values */ mc_read_map_entries(dev, &mc_values[0]); @@ -275,15 +274,14 @@ /* * DMA Protected Range can be reserved below TSEG for PCODE patch - * or TXT/BootGuard related data. Rather than report a base address + * or TXT/BootGuard related data. Rather than report a base address, * the DPR register reports the TOP of the region, which is the same - * as TSEG base. The region size is reported in MiB in bits 11:4. + * as TSEG base. The region size is reported in MiB in bits 11:4. */ - dpr_reg = pci_read_config32(dev, DPR); - if (dpr_reg & DPR_EPM) { - dpr_size = (dpr_reg & DPR_SIZE_MASK) << 16; - printk(BIOS_INFO, "DPR SIZE: 0x%lx\n", dpr_size); - } + const union dpr_register dpr = { + .raw = pci_read_config32(dev, DPR), + }; + printk(BIOS_DEBUG, "MC MAP: DPR: 0x%x\n", dpr.raw); /* * These are the host memory ranges that should be added: @@ -321,16 +319,15 @@ /* 0xc0000 -> TSEG - DPR */ base_k = 0xc0000 >> 10; size_k = (unsigned long)(mc_values[TSEG_REG] >> 10) - base_k; - size_k -= dpr_size >> 10; + size_k -= dpr.size >> 10; ram_resource(dev, index++, base_k, size_k); /* TSEG - DPR -> BGSM */ resource = new_resource(dev, index++); - resource->base = mc_values[TSEG_REG] - dpr_size; + resource->base = mc_values[TSEG_REG] - dpr.size; resource->size = mc_values[BGSM_REG] - resource->base; - resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | - IORESOURCE_STORED | IORESOURCE_RESERVE | - IORESOURCE_ASSIGNED | IORESOURCE_CACHEABLE; + resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | + IORESOURCE_RESERVE | IORESOURCE_ASSIGNED | IORESOURCE_CACHEABLE; /* BGSM -> TOLUD */ resource = new_resource(dev, index++); -- To view, visit https://review.coreboot.org/c/coreboot/+/46988 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I06b2348e379b61af60336ea1c4722bcddd953ebc Gerrit-Change-Number: 46988 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/common: Add ABAR helpers
by Angel Pons (Code Review) 07 Aug '23

07 Aug '23

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47023 ) Change subject: sb/intel/common: Add ABAR helpers ...................................................................... sb/intel/common: Add ABAR helpers These can be used instead of bit twiddling for clarity. Change-Id: Iffca4533f418340462fc773c2432e30a5abed6ac Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- A src/southbridge/intel/common/abar.h 1 file changed, 119 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/47023/1 diff --git a/src/southbridge/intel/common/abar.h b/src/southbridge/intel/common/abar.h new file mode 100644 index 0000000..ccfaa01 --- /dev/null +++ b/src/southbridge/intel/common/abar.h @@ -0,0 +1,119 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SERIAL_ATA_ABAR_H__ +#define __SERIAL_ATA_ABAR_H__ + +#include <arch/mmio.h> +#include <types.h> + +/* Per-port register offset helper */ +#define _ABAR_PORT_OFFSET(x) (0x100 + (x) * 0x80) + +/* Register definitions */ + +#define ABAR_REG_CAP 0x00 +#define ABAR_REG_GHC 0x04 +#define ABAR_REG_IS 0x08 +#define ABAR_REG_PI 0x0c +#define ABAR_REG_AHCI_VER 0x10 +#define ABAR_REG_CCC_CTL 0x14 +#define ABAR_REG_CCC_PORTS 0x18 +#define ABAR_REG_EM_LOC 0x1c +#define ABAR_REG_EM_CTL 0x20 +#define ABAR_REG_CAP_2 0x24 +#define ABAR_REG_BOHC 0x28 + +#define ABAR_REG_PxCLB(x) (0x00 + _ABAR_PORT_OFFSET(x)) +#define ABAR_REG_PxCLBU(x) (0x04 + _ABAR_PORT_OFFSET(x)) +#define ABAR_REG_PxFB(x) (0x08 + _ABAR_PORT_OFFSET(x)) +#define ABAR_REG_PxFBU(x) (0x0c + _ABAR_PORT_OFFSET(x)) +#define ABAR_REG_PxIS(x) (0x10 + _ABAR_PORT_OFFSET(x)) +#define ABAR_REG_PxIE(x) (0x14 + _ABAR_PORT_OFFSET(x)) +#define ABAR_REG_PxCMD(x) (0x18 + _ABAR_PORT_OFFSET(x)) +/* Note that this port register (0x1c + _ABAR_PORT_OFFSET(x)) is not in the AHCI spec */ +#define ABAR_REG_PxTFD(x) (0x20 + _ABAR_PORT_OFFSET(x)) +#define ABAR_REG_PxSIG(x) (0x24 + _ABAR_PORT_OFFSET(x)) +#define ABAR_REG_PxSSTS(x) (0x28 + _ABAR_PORT_OFFSET(x)) +#define ABAR_REG_PxSCTL(x) (0x2c + _ABAR_PORT_OFFSET(x)) +#define ABAR_REG_PxSERR(x) (0x30 + _ABAR_PORT_OFFSET(x)) +#define ABAR_REG_PxSACT(x) (0x34 + _ABAR_PORT_OFFSET(x)) +#define ABAR_REG_PxCI(x) (0x38 + _ABAR_PORT_OFFSET(x)) +#define ABAR_REG_PxSNTF(x) (0x3c + _ABAR_PORT_OFFSET(x)) +#define ABAR_REG_PxFBS(x) (0x40 + _ABAR_PORT_OFFSET(x)) +#define ABAR_REG_PxDEVSLP(x) (0x44 + _ABAR_PORT_OFFSET(x)) + +/* Bitfield definitions */ +union abar_reg_cap { + struct { + uint32_t number_of_ports : 5; // Bits 4: 0 + uint32_t external_sata : 1; // Bits 5: 5 + uint32_t enclosure_management : 1; // Bits 6: 6 + uint32_t cmd_cmpl_coalescing : 1; // Bits 7: 7 + uint32_t num_command_slots : 5; // Bits 12: 8 + uint32_t partial_state : 1; // Bits 13:13 + uint32_t slumber_state : 1; // Bits 14:14 + uint32_t pio_multiple_drq : 1; // Bits 15:15 + uint32_t fis_based_switching : 1; // Bits 16:16 + uint32_t port_multiplier : 1; // Bits 17:17 + uint32_t ahci_mode_only : 1; // Bits 18:18 + uint32_t : 1; // Bits 19:19 + uint32_t interface_speed : 4; // Bits 23:20 + uint32_t cmd_list_override : 1; // Bits 24:24 + uint32_t activity_led : 1; // Bits 25:25 + uint32_t aggressive_link_pm : 1; // Bits 26:26 + uint32_t staggered_spinup : 1; // Bits 27:27 + uint32_t interlock_switch : 1; // Bits 28:28 + uint32_t snotification_reg : 1; // Bits 29:29 + uint32_t native_cmd_queuing : 1; // Bits 30:30 + uint32_t addressing_64bit : 1; // Bits 31:31 + }; + uint32_t raw; +}; + +union abar_reg_cap_2 { + struct { + uint32_t bios_os_handoff : 1; // Bits 0: 0 + uint32_t nvm_hci_present : 1; // Bits 1: 1 + uint32_t auto_partial_to_slumber : 1; // Bits 2: 2 + uint32_t supports_device_sleep : 1; // Bits 3: 3 + uint32_t aggressive_devslp_mgmt : 1; // Bits 4: 4 + uint32_t devslp_entry_slumber_only : 1; // Bits 5: 5 + uint32_t : 26; // Bits 31: 6 + }; + uint32_t raw; +}; + +union abar_reg_px_devslp { + struct { + uint32_t aggressive_devslp_enable : 1; // Bits 0: 0 + uint32_t device_sleep_present : 1; // Bits 1: 1 + uint32_t device_sleep_exit_timeout : 8; // Bits 9: 2 + uint32_t min_devslp_assertion_time : 5; // Bits 14:10 + uint32_t device_sleep_idle_timeout : 10; // Bits 24:15 + uint32_t dito_multiplier : 4; // Bits 28:25 + uint32_t : 3; // Bits 31:29 + }; + uint32_t raw; +}; + +/* Accessors */ +static inline uint32_t abar_read32(const uintptr_t abar, const size_t offset) +{ + return read32((void *)(abar + offset)); +} + +static inline void abar_write32(const uintptr_t abar, const size_t offset, const uint32_t value) +{ + write32((void *)(abar + offset), value); +} + +static inline void abar_write_ports_implemented(const uintptr_t abar, const uint32_t port_map) +{ + abar_write32(abar, ABAR_REG_PI, port_map); + + /* Read back twice */ + abar_read32(abar, ABAR_REG_PI); + abar_read32(abar, ABAR_REG_PI); +} + +#endif /* __SERIAL_ATA_ABAR_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/47023 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iffca4533f418340462fc773c2432e30a5abed6ac Gerrit-Change-Number: 47023 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

5 15

Change in coreboot[master]: Support for Zotac AD04 added (initial commit)
by Name of user not set (Code Review) 07 Aug '23

07 Aug '23

Name of user not set #1003174 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47056 ) Change subject: Support for Zotac AD04 added (initial commit) ...................................................................... Support for Zotac AD04 added (initial commit) Signed-off-by: moscovium-115 <3134c487(a)tutanota.com> Change-Id: I184fb55b184c7739824d801524e2a3d1d2573f11 --- A Documentation/mainboard/zotac/ad04/ad04.md A Documentation/mainboard/zotac/ad04/logs/acpidump.err.log A Documentation/mainboard/zotac/ad04/logs/acpidump.log A Documentation/mainboard/zotac/ad04/logs/biosdecode.err.log A Documentation/mainboard/zotac/ad04/logs/biosdecode.log A Documentation/mainboard/zotac/ad04/logs/codec#0 A Documentation/mainboard/zotac/ad04/logs/cpuinfo.err.log A Documentation/mainboard/zotac/ad04/logs/cpuinfo.log A Documentation/mainboard/zotac/ad04/logs/dmesg.err.log A Documentation/mainboard/zotac/ad04/logs/dmesg.log A Documentation/mainboard/zotac/ad04/logs/dmidecode.err.log A Documentation/mainboard/zotac/ad04/logs/dmidecode.log A Documentation/mainboard/zotac/ad04/logs/ectool.err.log A Documentation/mainboard/zotac/ad04/logs/ectool.log A Documentation/mainboard/zotac/ad04/logs/flashrom_info.err.log A Documentation/mainboard/zotac/ad04/logs/flashrom_info.log A Documentation/mainboard/zotac/ad04/logs/flashrom_read.err.log A Documentation/mainboard/zotac/ad04/logs/flashrom_read.log A Documentation/mainboard/zotac/ad04/logs/input_bustypes.log A Documentation/mainboard/zotac/ad04/logs/inteltool.err.log A Documentation/mainboard/zotac/ad04/logs/inteltool.log A Documentation/mainboard/zotac/ad04/logs/ioports.err.log A Documentation/mainboard/zotac/ad04/logs/ioports.log A Documentation/mainboard/zotac/ad04/logs/log.sh A Documentation/mainboard/zotac/ad04/logs/lspci.err.log A Documentation/mainboard/zotac/ad04/logs/lspci.log A Documentation/mainboard/zotac/ad04/logs/lsusb.err.log A Documentation/mainboard/zotac/ad04/logs/lsusb.log A Documentation/mainboard/zotac/ad04/logs/msrtool.err.log A Documentation/mainboard/zotac/ad04/logs/msrtool.log A Documentation/mainboard/zotac/ad04/logs/nvramtool.err.log A Documentation/mainboard/zotac/ad04/logs/nvramtool.log A Documentation/mainboard/zotac/ad04/logs/pin_hwC0D0 A Documentation/mainboard/zotac/ad04/logs/rom.bin A Documentation/mainboard/zotac/ad04/logs/superiotool.err.log A Documentation/mainboard/zotac/ad04/logs/superiotool.log A configs/config.zotac_ad04 A src/mainboard/zotac/Kconfig A src/mainboard/zotac/Kconfig.name A src/mainboard/zotac/ad04/BiosCallOuts.c A src/mainboard/zotac/ad04/Kconfig A src/mainboard/zotac/ad04/Kconfig.name A src/mainboard/zotac/ad04/Makefile.inc A src/mainboard/zotac/ad04/OemCustomize.c A src/mainboard/zotac/ad04/OptionsIds.h A src/mainboard/zotac/ad04/acpi/buttons.asl A src/mainboard/zotac/ad04/acpi/gpe.asl A src/mainboard/zotac/ad04/acpi/gpio.asl A src/mainboard/zotac/ad04/acpi/leds.asl A src/mainboard/zotac/ad04/acpi/mainboard.asl A src/mainboard/zotac/ad04/acpi/routing.asl A src/mainboard/zotac/ad04/acpi/sata.asl A src/mainboard/zotac/ad04/acpi/sleep.asl A src/mainboard/zotac/ad04/acpi/superio.asl A src/mainboard/zotac/ad04/acpi/usb_oc.asl A src/mainboard/zotac/ad04/acpi_tables.c A src/mainboard/zotac/ad04/board_info.txt A src/mainboard/zotac/ad04/bootblock.c A src/mainboard/zotac/ad04/buildOpts.c A src/mainboard/zotac/ad04/cmos.default A src/mainboard/zotac/ad04/cmos.layout A src/mainboard/zotac/ad04/devicetree.cb A src/mainboard/zotac/ad04/dsdt.asl A src/mainboard/zotac/ad04/gpio_ftns.c A src/mainboard/zotac/ad04/gpio_ftns.h A src/mainboard/zotac/ad04/irq_tables.c A src/mainboard/zotac/ad04/mainboard.c A src/mainboard/zotac/ad04/mptable.c A src/mainboard/zotac/ad04/platform_cfg.h A src/mainboard/zotac/ad04/romstage.c A src/mainboard/zotac/ad04/spd/HYNIX-H5TQ2G83CFR.spd.hex A src/mainboard/zotac/ad04/spd/HYNIX-H5TQ4G83MFR.spd.hex 72 files changed, 17,792 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/47056/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/47056 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I184fb55b184c7739824d801524e2a3d1d2573f11 Gerrit-Change-Number: 47056 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1003174 Gerrit-MessageType: newchange

4 7

Change in coreboot[master]: sb/intel/lynxpoint: Use common AHCI library
by Angel Pons (Code Review) 07 Aug '23

07 Aug '23

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47095 ) Change subject: sb/intel/lynxpoint: Use common AHCI library ...................................................................... sb/intel/lynxpoint: Use common AHCI library This avoids confusing and potentially dangerous pointer arithmetics. Behaviour before after this patch should be equivalent, too. Change-Id: I62a26d74fe78dc0158b383da9126c56746722c53 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/sata.c 1 file changed, 39 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/47095/1 diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c index d8eb2a8..e4aa083 100644 --- a/src/southbridge/intel/lynxpoint/sata.c +++ b/src/southbridge/intel/lynxpoint/sata.c @@ -7,6 +7,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <delay.h> +#include <southbridge/intel/common/ahci.h> #include "chip.h" #include "iobp.h" #include "pch.h" @@ -37,8 +38,6 @@ { u32 reg32; - u32 *abar; - /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -51,7 +50,7 @@ /* SATA configuration */ - /* Enable memory space decoding for ABAR */ + /* Enable memory space decoding for AHCI BAR */ pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_IO); printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n"); @@ -107,31 +106,47 @@ pci_write_config32(dev, 0x94, reg32); /* Initialize AHCI memory-mapped space */ - abar = (u32 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5); - printk(BIOS_DEBUG, "ABAR: %p\n", abar); - /* CAP (HBA Capabilities) : enable power management */ - reg32 = read32(abar + 0x00); - reg32 |= 0x0c006000; // set PSC+SSC+SALP+SSS - reg32 &= ~0x00020060; // clear SXS+EMS+PMS + const uintptr_t ahci_bar = pci_read_config32(dev, PCI_BASE_ADDRESS_5); + printk(BIOS_DEBUG, "AHCI BAR: %p\n", (void *)ahci_bar); + + union ahci_reg_cap ahci_cap = { + .raw = ahci_read32(ahci_bar, AHCI_REG_CAP), + }; + + ahci_cap.external_sata = 0; /* Should be configurable */ + ahci_cap.enclosure_management = 0; + ahci_cap.port_multiplier = 0; + + ahci_cap.partial_state = 1; + ahci_cap.slumber_state = 1; + ahci_cap.aggressive_link_pm = 1; + ahci_cap.staggered_spinup = 1; + if (pch_is_lp()) - reg32 |= (1 << 18); // SAM: SATA AHCI MODE ONLY - write32(abar + 0x00, reg32); - /* PI (Ports implemented) */ - write32(abar + 0x03, config->sata_port_map); - (void)read32(abar + 0x03); /* Read back 1 */ - (void)read32(abar + 0x03); /* Read back 2 */ - /* CAP2 (HBA Capabilities Extended)*/ - reg32 = read32(abar + 0x09); - /* Enable DEVSLP */ + ahci_cap.ahci_mode_only = 1; + + ahci_write32(ahci_bar, AHCI_REG_CAP, ahci_cap.raw); + + ahci_write_ports_implemented(ahci_bar, config->sata_port_map); + + union ahci_reg_cap_2 ahci_cap_2 = { + .raw = ahci_read32(ahci_bar, AHCI_REG_CAP_2), + }; + if (pch_is_lp()) { - if (config->sata_devslp_disable) - reg32 &= ~(1 << 3); - else - reg32 |= (1 << 5)|(1 << 4)|(1 << 3)|(1 << 2); + if (config->sata_devslp_disable) { + ahci_cap_2.supports_device_sleep = 0; + } else { + ahci_cap_2.auto_partial_to_slumber = 1; + ahci_cap_2.supports_device_sleep = 1; + ahci_cap_2.aggressive_devslp_mgmt = 1; + ahci_cap_2.devslp_entry_slumber_only = 1; + } } else { - reg32 &= ~0x00000002; + ahci_cap_2.nvm_hci_present = 0; } - write32(abar + 0x09, reg32); + + ahci_write32(ahci_bar, AHCI_REG_CAP_2, ahci_cap_2.raw); /* Set Gen3 Transmitter settings if needed */ if (config->sata_port0_gen3_tx) -- To view, visit https://review.coreboot.org/c/coreboot/+/47095 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62a26d74fe78dc0158b383da9126c56746722c53 Gerrit-Change-Number: 47095 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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