coreboot-gerrit April 2022

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Change in coreboot[master]: mb/google/brya/var/osiris: Generate SPD ID for supported parts
by Felix Held (Code Review) 21 Apr '22

21 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63706 ) Change subject: mb/google/brya/var/osiris: Generate SPD ID for supported parts ...................................................................... mb/google/brya/var/osiris: Generate SPD ID for supported parts Add supported memory parts in mem_parts_used.txt, and generate SPD id for these parts. MT53E512M32D1NP-046 WT:B (Micron) MT53E1G32D2NP-046 WT:B (Micron) H54G46CYRBX267 (Hynix) H54G56CYRBX247 (Hynix) K4U6E3S4AB-MGCL (Samsung) K4UBE3D4AB-MGCL (Samsung) BUG=None TEST=build pass Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: I1fbdce203afd282cef9fcd7aebbace69d19fbbf1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63706 Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/variants/osiris/memory/Makefile.inc M src/mainboard/google/brya/variants/osiris/memory/dram_id.generated.txt M src/mainboard/google/brya/variants/osiris/memory/mem_parts_used.txt 3 files changed, 22 insertions(+), 13 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/osiris/memory/Makefile.inc b/src/mainboard/google/brya/variants/osiris/memory/Makefile.inc index eace2e4..eb91988 100644 --- a/src/mainboard/google/brya/variants/osiris/memory/Makefile.inc +++ b/src/mainboard/google/brya/variants/osiris/memory/Makefile.inc @@ -1,5 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! -# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. +# Generated by: +# util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/osiris/memory/ src/mainboard/google/brya/variants/osiris/memory/mem_parts_used.txt -SPD_SOURCES = placeholder +SPD_SOURCES = +SPD_SOURCES += spd/lp4x/set-0/spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D1NP-046 WT:B, H54G46CYRBX267, K4U6E3S4AB-MGCL +SPD_SOURCES += spd/lp4x/set-0/spd-3.hex # ID = 1(0b0001) Parts = MT53E1G32D2NP-046 WT:B, H54G56CYRBX247, K4UBE3D4AB-MGCL diff --git a/src/mainboard/google/brya/variants/osiris/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/osiris/memory/dram_id.generated.txt index fa24790..1135950 100644 --- a/src/mainboard/google/brya/variants/osiris/memory/dram_id.generated.txt +++ b/src/mainboard/google/brya/variants/osiris/memory/dram_id.generated.txt @@ -1 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/osiris/memory/ src/mainboard/google/brya/variants/osiris/memory/mem_parts_used.txt + DRAM Part Name ID to assign +MT53E512M32D1NP-046 WT:B 0 (0000) +MT53E1G32D2NP-046 WT:B 1 (0001) +H54G46CYRBX267 0 (0000) +H54G56CYRBX247 1 (0001) +K4U6E3S4AB-MGCL 0 (0000) +K4UBE3D4AB-MGCL 1 (0001) diff --git a/src/mainboard/google/brya/variants/osiris/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/osiris/memory/mem_parts_used.txt index 9621137..a188982 100644 --- a/src/mainboard/google/brya/variants/osiris/memory/mem_parts_used.txt +++ b/src/mainboard/google/brya/variants/osiris/memory/mem_parts_used.txt @@ -1,11 +1,6 @@ -# This is a CSV file containing a list of memory parts used by this variant. -# One part per line with an optional fixed ID in column 2. -# Only include a fixed ID if it is required for legacy reasons! -# Generated IDs are dependent on the order of parts in this file, -# so new parts must always be added at the end of the file! -# -# Generate an updated Makefile.inc and dram_id.generated.txt by running the -# part_id_gen tool from util/spd_tools. -# See util/spd_tools/README.md for more details and instructions. - -# Part Name +MT53E512M32D1NP-046 WT:B +MT53E1G32D2NP-046 WT:B +H54G46CYRBX267 +H54G56CYRBX247 +K4U6E3S4AB-MGCL +K4UBE3D4AB-MGCL -- To view, visit https://review.coreboot.org/c/coreboot/+/63706 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fbdce203afd282cef9fcd7aebbace69d19fbbf1 Gerrit-Change-Number: 63706 Gerrit-PatchSet: 3 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya: Create osiris variant
by Felix Held (Code Review) 21 Apr '22

21 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63650 ) Change subject: mb/google/brya: Create osiris variant ...................................................................... mb/google/brya: Create osiris variant Create the osiris variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:229352299 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_OSIRIS Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: I41e088a3415add86cba87c919af23494f816bb24 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63650 Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/Kconfig.name A src/mainboard/google/brya/variants/osiris/include/variant/ec.h A src/mainboard/google/brya/variants/osiris/include/variant/gpio.h A src/mainboard/google/brya/variants/osiris/memory/Makefile.inc A src/mainboard/google/brya/variants/osiris/memory/dram_id.generated.txt A src/mainboard/google/brya/variants/osiris/memory/mem_parts_used.txt A src/mainboard/google/brya/variants/osiris/overridetree.cb 8 files changed, 46 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 122e992..724da6c 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -118,6 +118,7 @@ default 0x0 if BOARD_GOOGLE_CRAASK default 0x1 if BOARD_GOOGLE_CROTA default 0x1 if BOARD_GOOGLE_MOLI + default 0x1 if BOARD_GOOGLE_OSIRIS config DRIVER_TPM_I2C_ADDR hex @@ -171,6 +172,7 @@ default "Moli" if BOARD_GOOGLE_MOLI default "Kinox" if BOARD_GOOGLE_KINOX default "Craask" if BOARD_GOOGLE_CRAASK + default "Osiris" if BOARD_GOOGLE_OSIRIS config VARIANT_DIR default "brya0" if BOARD_GOOGLE_BRYA0 @@ -199,6 +201,7 @@ default "moli" if BOARD_GOOGLE_MOLI default "kinox" if BOARD_GOOGLE_KINOX default "craask" if BOARD_GOOGLE_CRAASK + default "osiris" if BOARD_GOOGLE_OSIRIS config VBOOT select VBOOT_EARLY_EC_SYNC diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index 3028aa1..66b2120 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -198,3 +198,7 @@ config BOARD_GOOGLE_CRAASK bool "-> Craask" select BOARD_GOOGLE_BASEBOARD_NISSA + +config BOARD_GOOGLE_OSIRIS + bool "-> Osiris" + select BOARD_GOOGLE_BASEBOARD_BRYA diff --git a/src/mainboard/google/brya/variants/osiris/include/variant/ec.h b/src/mainboard/google/brya/variants/osiris/include/variant/ec.h new file mode 100644 index 0000000..7a2a6ff --- /dev/null +++ b/src/mainboard/google/brya/variants/osiris/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/brya/variants/osiris/include/variant/gpio.h b/src/mainboard/google/brya/variants/osiris/include/variant/gpio.h new file mode 100644 index 0000000..c4fe342 --- /dev/null +++ b/src/mainboard/google/brya/variants/osiris/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +#endif diff --git a/src/mainboard/google/brya/variants/osiris/memory/Makefile.inc b/src/mainboard/google/brya/variants/osiris/memory/Makefile.inc new file mode 100644 index 0000000..eace2e4 --- /dev/null +++ b/src/mainboard/google/brya/variants/osiris/memory/Makefile.inc @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. + +SPD_SOURCES = placeholder diff --git a/src/mainboard/google/brya/variants/osiris/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/osiris/memory/dram_id.generated.txt new file mode 100644 index 0000000..fa24790 --- /dev/null +++ b/src/mainboard/google/brya/variants/osiris/memory/dram_id.generated.txt @@ -0,0 +1 @@ +DRAM Part Name ID to assign diff --git a/src/mainboard/google/brya/variants/osiris/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/osiris/memory/mem_parts_used.txt new file mode 100644 index 0000000..9621137 --- /dev/null +++ b/src/mainboard/google/brya/variants/osiris/memory/mem_parts_used.txt @@ -0,0 +1,11 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# part_id_gen tool from util/spd_tools. +# See util/spd_tools/README.md for more details and instructions. + +# Part Name diff --git a/src/mainboard/google/brya/variants/osiris/overridetree.cb b/src/mainboard/google/brya/variants/osiris/overridetree.cb new file mode 100644 index 0000000..4f2c04a --- /dev/null +++ b/src/mainboard/google/brya/variants/osiris/overridetree.cb @@ -0,0 +1,6 @@ +chip soc/intel/alderlake + + device domain 0 on + end + +end -- To view, visit https://review.coreboot.org/c/coreboot/+/63650 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41e088a3415add86cba87c919af23494f816bb24 Gerrit-Change-Number: 63650 Gerrit-PatchSet: 3 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: cpu/x86/fpu_enable.inc: Remove file used by romcc
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55008 ) Change subject: cpu/x86/fpu_enable.inc: Remove file used by romcc ...................................................................... cpu/x86/fpu_enable.inc: Remove file used by romcc Change-Id: I530bb217bb9a944990232dcf4e08f160b5267512 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55008 Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- D src/cpu/x86/fpu_enable.inc 1 file changed, 0 insertions(+), 22 deletions(-) Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve diff --git a/src/cpu/x86/fpu_enable.inc b/src/cpu/x86/fpu_enable.inc deleted file mode 100644 index 28d2063..0000000 --- a/src/cpu/x86/fpu_enable.inc +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -__fpu_start: - /* Preserve BIST. */ - movl %eax, %ebp - - /* - * Clear the CR0[2] bit (the "Emulation" flag, EM). - * - * This indicates that the processor has an (internal or external) - * x87 FPU, i.e. floating point operations will be executed by the - * hardware (and not emulated in software). - * - * Additionally, if this bit is not cleared, MMX/SSE instructions won't - * work, i.e., they will trigger an invalid opcode exception (#UD). - */ - movl %cr0, %eax - andl $~(1 << 2), %eax - movl %eax, %cr0 - - /* Restore BIST. */ - movl %ebp, %eax 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/55008 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I530bb217bb9a944990232dcf4e08f160b5267512 Gerrit-Change-Number: 55008 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: cpu/x86/fpu_enable.inc: Remove file used by romcc
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Attention is currently required from: Paul Menzel, Arthur Heymans. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55008 ) Change subject: cpu/x86/fpu_enable.inc: Remove file used by romcc ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/55008/comment/eca0be75_ac904689 PS1, Line 7: cpu/x86/fpu_enable.inc: Remove file > Maybe: […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/55008 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I530bb217bb9a944990232dcf4e08f160b5267512 Gerrit-Change-Number: 55008 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 21 Apr 2022 12:30:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/mp_init: Fix false error message on parking APs twice
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/55071 ) Change subject: cpu/x86/mp_init: Fix false error message on parking APs twice ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/55071 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60095cffcb9b31d965b0525ddc3018b592a3e52e Gerrit-Change-Number: 55071 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: soc/intel/xeon_sp: Remove PARALLEL_MP_AP_WORK
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/55099 ) Change subject: soc/intel/xeon_sp: Remove PARALLEL_MP_AP_WORK ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/55099 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36b72e908189b752013eaf898971808224630894 Gerrit-Change-Number: 55099 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rocky Phagura Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: TESTONLY: Link pagetables into programs instead of using a cbfs file
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/56096 ) Change subject: TESTONLY: Link pagetables into programs instead of using a cbfs file ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/56096 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice4fd15d131b8c91bc98afad7f459ce3485b786d Gerrit-Change-Number: 56096 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: mb/prodrive/hermes: Fix eeprom settings layout
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/52348 ) Change subject: mb/prodrive/hermes: Fix eeprom settings layout ...................................................................... Abandoned Fixed on the BMC -- To view, visit https://review.coreboot.org/c/coreboot/+/52348 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I61bf9803b538f19559a130737ea2f68355da9f5d Gerrit-Change-Number: 52348 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: soc/{amd,intel}: Don't select VBOOT_SEPARATE_VERSTAGE
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Attention is currently required from: Martin L Roth, Furquan Shaikh, Julius Werner, Arthur Heymans, Aaron Durbin, Patrick Rudolph, Karthik Ramasubramanian. Hello build bot (Jenkins), Furquan Shaikh, Martin L Roth, Tim Wawrzynczak, Julius Werner, Aaron Durbin, Patrick Rudolph, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52788 to look at the new patch set (#5). Change subject: soc/{amd,intel}: Don't select VBOOT_SEPARATE_VERSTAGE ...................................................................... soc/{amd,intel}: Don't select VBOOT_SEPARATE_VERSTAGE Now the bootblock is not limited to 64K so integrating vboot into the bootblock reduces the binary size. intel/apl is an exception since the bootblock size is limited to 32K. Change-Id: I5e02961183b5bcc37365458a3b10342e5bc2b525 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/amd/stoneyridge/Kconfig M src/soc/intel/alderlake/Kconfig M src/soc/intel/broadwell/Kconfig M src/soc/intel/cannonlake/Kconfig M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/icelake/Kconfig M src/soc/intel/jasperlake/Kconfig M src/soc/intel/skylake/Kconfig M src/soc/intel/tigerlake/Kconfig 9 files changed, 0 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/52788/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/52788 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5e02961183b5bcc37365458a3b10342e5bc2b525 Gerrit-Change-Number: 52788 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin L Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin L Roth <martinroth(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: cpu/x86: Test the GNVS pointer before actually setting it
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47014 ) Change subject: cpu/x86: Test the GNVS pointer before actually setting it ...................................................................... cpu/x86: Test the GNVS pointer before actually setting it Change-Id: I15f67a12dbdd2529572eebf354cfbcf67017ca6d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/baytrail/smihandler.c M src/soc/intel/braswell/smihandler.c M src/soc/intel/broadwell/pch/smihandler.c M src/soc/intel/common/block/smm/smihandler.c M src/soc/intel/denverton_ns/smihandler.c M src/southbridge/intel/bd82x6x/smihandler.c M src/southbridge/intel/ibexpeak/smihandler.c M src/southbridge/intel/lynxpoint/smihandler.c 8 files changed, 27 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/47014/1 diff --git a/src/soc/intel/baytrail/smihandler.c b/src/soc/intel/baytrail/smihandler.c index 1810821..e1387b2 100644 --- a/src/soc/intel/baytrail/smihandler.c +++ b/src/soc/intel/baytrail/smihandler.c @@ -320,11 +320,12 @@ state = smi_apmc_find_state_save(reg8); if (state) { /* EBX in the state save contains the GNVS pointer */ - gnvs = (struct global_nvs *)((uint32_t)state->rbx); - if (smm_points_to_smram(gnvs, sizeof(*gnvs))) { + void *test_gnvs = (void *)((u32)state->rbx); + if (smm_points_to_smram(test_gnvs, sizeof(*gnvs))) { printk(BIOS_ERR, "SMI#: ERROR: GNVS overlaps SMM\n"); return; } + gnvs = test_gnvs; smm_initialized = 1; printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } diff --git a/src/soc/intel/braswell/smihandler.c b/src/soc/intel/braswell/smihandler.c index 6e250d8..e422777 100644 --- a/src/soc/intel/braswell/smihandler.c +++ b/src/soc/intel/braswell/smihandler.c @@ -299,11 +299,12 @@ state = smi_apmc_find_state_save(reg8); if (state) { /* EBX in the state save contains the GNVS pointer */ - gnvs = (struct global_nvs *)((uint32_t)state->rbx); - if (smm_points_to_smram(gnvs, sizeof(*gnvs))) { + void *test_gnvs = (void *)((u32)state->rbx); + if (smm_points_to_smram(test_gnvs, sizeof(*gnvs))) { printk(BIOS_ERR, "SMI#: ERROR: GNVS overlaps SMM\n"); return; } + gnvs = test_gnvs; smm_initialized = 1; printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } diff --git a/src/soc/intel/broadwell/pch/smihandler.c b/src/soc/intel/broadwell/pch/smihandler.c index fd5d452..f3b0cd2 100644 --- a/src/soc/intel/broadwell/pch/smihandler.c +++ b/src/soc/intel/broadwell/pch/smihandler.c @@ -342,11 +342,12 @@ state = smi_apmc_find_state_save(reg8); if (state) { /* EBX in the state save contains the GNVS pointer */ - gnvs = (struct global_nvs *)((u32)state->rbx); - if (smm_points_to_smram(gnvs, sizeof(*gnvs))) { + void *test_gnvs = (void *)((u32)state->rbx); + if (smm_points_to_smram(test_gnvs, sizeof(*gnvs))) { printk(BIOS_ERR, "SMI#: ERROR: GNVS overlaps SMM\n"); return; } + gnvs = test_gnvs; smm_initialized = 1; printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c index 270b1aa..141f084 100644 --- a/src/soc/intel/common/block/smm/smihandler.c +++ b/src/soc/intel/common/block/smm/smihandler.c @@ -370,12 +370,12 @@ state = find_save_state(save_state_ops, reg8); if (state) { /* EBX in the state save contains the GNVS pointer */ - uint32_t reg_ebx = save_state_ops->get_reg(state, RBX); - gnvs = (struct global_nvs *)(uintptr_t)reg_ebx; - if (smm_points_to_smram(gnvs, sizeof(*gnvs))) { + void *test_gnvs = (void *)((u32)state->rbx); + if (smm_points_to_smram(test_gnvs, sizeof(*gnvs))) { printk(BIOS_ERR, "SMI#: ERROR: GNVS overlaps SMM\n"); return; } + gnvs = test_gnvs; smm_initialized = 1; printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } diff --git a/src/soc/intel/denverton_ns/smihandler.c b/src/soc/intel/denverton_ns/smihandler.c index 5eecba7..1e7d1e3 100644 --- a/src/soc/intel/denverton_ns/smihandler.c +++ b/src/soc/intel/denverton_ns/smihandler.c @@ -240,7 +240,12 @@ state = smi_apmc_find_state_save(reg8); if (state) { /* EBX in the state save contains the GNVS pointer */ - gnvs = (struct global_nvs *)((uint32_t)state->rbx); + void *test_gnvs = (void *)((u32)state->rbx); + if (smm_points_to_smram(test_gnvs, sizeof(*gnvs))) { + printk(BIOS_ERR, "SMI#: ERROR: GNVS overlaps SMM\n"); + return; + } + gnvs = test_gnvs; smm_initialized = 1; printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index 40672f8..f390d06 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -191,12 +191,12 @@ smi_apmc_find_state_save(apm_cnt); if (state) { /* EBX in the state save contains the GNVS pointer */ - gnvs = (struct global_nvs *)((u32)state->rbx); - struct region r = {(uintptr_t)gnvs, sizeof(struct global_nvs)}; - if (smm_region_overlaps_handler(&r)) { + void *test_gnvs = (void *)((u32)state->rbx); + if (smm_points_to_smram(test_gnvs, sizeof(*gnvs))) { printk(BIOS_ERR, "SMI#: ERROR: GNVS overlaps SMM\n"); return; } + gnvs = test_gnvs; *smm_done = 1; printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index 0c5e954..e53705a 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -153,11 +153,12 @@ smi_apmc_find_state_save(apm_cnt); if (state) { /* EBX in the state save contains the GNVS pointer */ - gnvs = (struct global_nvs *)(uintptr_t)((u32)state->rbx); - if (smm_points_to_smram(gnvs, sizeof(*gnvs))) { + void *test_gnvs = (void *)((u32)state->rbx); + if (smm_points_to_smram(test_gnvs, sizeof(*gnvs))) { printk(BIOS_ERR, "SMI#: ERROR: GNVS overlaps SMM\n"); return; } + gnvs = test_gnvs; *smm_done = 1; printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index 9a5e5c0..b6fe7bf 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -313,11 +313,12 @@ state = smi_apmc_find_state_save(reg8); if (state) { /* EBX in the state save contains the GNVS pointer */ - gnvs = (struct global_nvs *)((u32)state->rbx); - if (smm_points_to_smram(gnvs, sizeof(*gnvs))) { + void *test_gnvs = (void *)((u32)state->rbx); + if (smm_points_to_smram(test_gnvs, sizeof(*gnvs))) { printk(BIOS_ERR, "SMI#: ERROR: GNVS overlaps SMM\n"); return; } + gnvs = test_gnvs; smm_initialized = 1; printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } -- To view, visit https://review.coreboot.org/c/coreboot/+/47014 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15f67a12dbdd2529572eebf354cfbcf67017ca6d Gerrit-Change-Number: 47014 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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