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Change subject: mb/google/brya/variants/volmar: Disable the unused FP pads
......................................................................
Patch Set 3: Code-Review+2
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Change subject: soc/amd/picasso: Move AMD firmware from 0x420000 to 0x20000
......................................................................
Patch Set 2:
(4 comments)
File src/mainboard/amd/mandolin/Kconfig:
https://review.coreboot.org/c/coreboot/+/69428/comment/61d932f1_d8963241
PS2, Line 49: config CBFS_SIZE
: default 0x400000 if BOARD_AMD_MANDOLIN # Maximum size for the Mandolin FMAP
: default 0xfcf000 if BOARD_AMD_CEREME # Maximum size for the Cereme FMAP
These options are meaningless since you use an FMAP instead of generate a default one. Just remove everything.
File src/mainboard/amd/mandolin/variants/mandolin/board.fmd:
https://review.coreboot.org/c/coreboot/+/69428/comment/64fc121b_b3f70e8a
PS2, Line 7: @4M
this should not be needed.
File src/soc/amd/picasso/Kconfig:
https://review.coreboot.org/c/coreboot/+/69428/comment/8bb54bbf_78f4a102
PS2, Line 400: The AMDFW (PSP) is typically locatable in cbfs. Select this
: option to manually attach the generated amdfw.rom at an
: offset of 0x20000 from the bottom of the coreboot ROM image.
You are putting the amdfw at the "AMDFW" fmap region. The user needs to create that region at a valid offset. You might want to validate that somehow. e.g. Add a C file that does static asserts on FMAP regions.
File src/soc/amd/picasso/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/69428/comment/7c66bf34_b473f66c
PS2, Line 291: DD
You're not using DD.
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Hello build bot (Jenkins), Raul Rangel, Jason Nien, Matt DeVillier, Martin Roth, Eric Peers, Tim Van Patten, Jason Glenesk, Caveh Jalali, Tim Wawrzynczak, Fred Reitberger, Karthikeyan Ramasubramanian, Boris Mittelberg, Felix Held,
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Change subject: common/acpi/dptc: Implement DTTS Proposal
......................................................................
common/acpi/dptc: Implement DTTS Proposal
DTTS indicated Dynamic Thermal Table Switching.
The proposal would like to develop the schematic
for switching 6 thermal table by lid status,
machine body mode and temperature.
After entering the OS, the thermal table would be table A.
If the “Motion” or “Lid-status changement” is detected.
The thermal table would switch to laptop mode or lid-close
mode. Once the higher environment temperatures are detected,
the thermal table would switch to the corresponding power
throttle table(B, D or F). Based on these table switching
mechanisms, no matter how the end-user uses Chromebook,
they could enjoy more humanized thermal designs.
Release Over Over Release
Temp. Temp. Temp. Temp.
--------------------------------------------------------
Desktop mode Table A Table B 50C 45C
Lid open (Default)
--------------------------------------------------------
Desktop mode Table C Table D 55C 50C
Lid close
--------------------------------------------------------
Laptop mode Table E Table F 45C 40C
--------------------------------------------------------
On the proposal, the transmission rules are list below:
1. Table A is the default table after booting.
2. A, C, E can switch to each other.
3. B, D, F can switch to each other.
4. A and B, C and D, E and F can switch to each other.
5. Assume Table A is current table. When the temperature
reach 50C, than the table is switched from A to B.
6. Based on 4. The current table is B. When the temperature
is downgrade below 45C, the table is switched form B to A.
7. Based on 4 an 5, the same rule is for C and D, E and F.
BRANCH=none
BUG=b:232946420
TEST=emerge-skyrim coreboot
Signed-off-by: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com>
Change-Id: I866e5e497e2936984e713029b5f0b6d54cbc9622
---
A src/soc/amd/common/acpi/DTTS.asl
M src/soc/amd/mendocino/acpi/soc.asl
2 files changed, 171 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/68471/32
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Change subject: mb/google/brya/variants/volmar: Disable the unused FP pads
......................................................................
Patch Set 3:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/69465/comment/96cd32ca_ffba13f3
PS1, Line 9: GPO
> gpio
done!
File src/mainboard/google/brya/variants/volmar/fw_config.c:
https://review.coreboot.org/c/coreboot/+/69465/comment/aab12d06_200e0710
PS1, Line 94: offload
> pads?
Done! modified the comment.
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Change subject: mb/google/skyrim/var/winterhold: Update DPTC setting for EVT-SMT
......................................................................
Patch Set 10: Code-Review+1
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/68742/comment/69297a1a_8c86885e
PS10, Line 7: EVT-SMT
Please don't put phase on commit message or code.
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Change subject: aopen/dxplplusu: Add early GPIO settings
......................................................................
Patch Set 4: Code-Review+2
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Hello build bot (Jenkins), David Wu, Tarun Tuli, Eric Lai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/69465
to look at the new patch set (#2).
Change subject: mb/google/brya/variants/volmar: Disable the unused FP pads
......................................................................
mb/google/brya/variants/volmar: Disable the unused FP pads
Disable the unused fingerprinter(FP) gpio for zavala by fw_config
FPMCU_MASK field.
BUG=b:250807253
TEST=build firmware and veriify the FP function on volmar DUT
Signed-off-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com>
Change-Id: I0af1b7c3e4829ecab98525ead4f078c3eb6485d0
---
M src/mainboard/google/brya/variants/volmar/fw_config.c
1 file changed, 27 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/69465/2
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Change subject: cpu/intel/socket_mPGA604: Drop non-working SSE2 disablement
......................................................................
Patch Set 2: Code-Review+2
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Change subject: cpu/intel/socket_*: Clean up Kconfig files
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/69447/comment/798ba83a_33faa08c
PS3, Line 10: Move MAX_CPUS to mainboards.
why?
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