Attention is currently required from: Anil Kumar K.
Bora Guvendik has uploaded a new patch set (#3) to the change originally created by Anil Kumar K. ( https://review.coreboot.org/c/coreboot/+/56922 )
Change subject: [Test] adlrvp: Disable HD audio for pnp measurements
......................................................................
[Test] adlrvp: Disable HD audio for pnp measurements
Change-Id: I40ccf48c51c52d253b98a8ccbea294b65a2e306b
---
M src/mainboard/intel/adlrvp/Kconfig
M src/mainboard/intel/adlrvp/devicetree_m.cb
2 files changed, 4 insertions(+), 61 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/56922/3
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Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56919 )
Change subject: soc/amd/common: Skip psp_verstage on S0i3 resume
......................................................................
Patch Set 2:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/56919/comment/450322fb_a5423650
PS1, Line 8:
> Please add a reasoning, why psp_verstage is not needed.
Done
https://review.coreboot.org/c/coreboot/+/56919/comment/2606a962_bef10b63
PS1, Line 10: :
> =
Done
https://review.coreboot.org/c/coreboot/+/56919/comment/a2f779b2_b36b52c1
PS1, Line 10: S0i3
> psp_verstage
Done
File src/soc/amd/common/psp_verstage/psp_verstage.c:
https://review.coreboot.org/c/coreboot/+/56919/comment/75e1bfb6_24e2151e
PS1, Line 205: Currently, we want to skip running verstage on all S0i3 resumes. This relies
: on an assumption that the PSP will be checksumming all of its components.
> Thanks for the background, Karthik. […]
I don't think the plan was to drop this. You might want to talk to Eric about that, because the decision in yesterday's meeting was to do both. Let me know what's decided - I don't really care either way, but it's very difficult when I have two people pulling in different directions.
I'll update the commit message saying that the PSP shouldn't even load psp_verstage on resume though.
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Hello Jason Glenesk, build bot (Jenkins), Raul Rangel, Marshall Dawson, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/56919
to look at the new patch set (#2).
Change subject: soc/amd/common: Skip psp_verstage on S0i3 resume
......................................................................
soc/amd/common: Skip psp_verstage on S0i3 resume
PSP_Verstage will take almost the entire time to run that
is allotted to S0i3 resume. Since coreboot isn't running,
the PSP needs to handle any security requirements. The long-
term plan is that the PSP won't even load psp_verstage on S0i3
resume, but when it is loaded, this makes sure we exit
immediately
BUG=b:177064859
TEST=Verify that PSP_verstage doesn't run on S0i3 resume
Signed-off-by: Martin Roth <martinroth(a)chromium.org>
Change-Id: Ia7b2560ff3d7621922ec4bc0e8793961f5d7550f
---
M src/soc/amd/common/psp_verstage/psp_verstage.c
1 file changed, 7 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/56919/2
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Change subject: soc/intel/alderlake: set default PL4 values for different SKUs
......................................................................
Patch Set 3:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/56917/comment/feda4236_fc884ff6
PS2, Line 7: differnt
> different
Ack
https://review.coreboot.org/c/coreboot/+/56917/comment/bfc7145b_36ed4a08
PS2, Line 9: Set default PL4 values for various alderlake CPU SKUs.
> Please note, where you got these default values from.
Done
https://review.coreboot.org/c/coreboot/+/56917/comment/caa30ae8_3c78fed1
PS2, Line 9: alderlake
> Alder Lake
Ack
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Change subject: soc/intel/alderlake: set default PL4 values for differnt SKUs
......................................................................
Patch Set 2:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/56917/comment/fc2a0435_63048e22
PS2, Line 7: differnt
different
https://review.coreboot.org/c/coreboot/+/56917/comment/248f60e5_100059cc
PS2, Line 9: alderlake
Alder Lake
https://review.coreboot.org/c/coreboot/+/56917/comment/be70815d_e166e9c4
PS2, Line 9: Set default PL4 values for various alderlake CPU SKUs.
Please note, where you got these default values from.
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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56895 )
Change subject: mb/google/guybrush/var/baseboard: Set Clk request for WLAN/SD/WWAN/SSD device.
......................................................................
Patch Set 5:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/56895/comment/2097e9cc_9dd32103
PS5, Line 7: mb/google/guybrush/var/baseboard: Set Clk request for WLAN/SD/WWAN/SSD device.
Please remove the dot/period at the end of the git commit message summary.
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Change subject: mb/google/guybrush/var/baseboard: Set Clk request for WLAN/SD/WWAN/SSD device.
......................................................................
Patch Set 5:
(6 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/56895/comment/6db3401f_2a29f111
PS2, Line 7: src/mainboard/google/guybrush/variants/baseboard
> mb/google/guybrush/var/baseboard
Done
https://review.coreboot.org/c/coreboot/+/56895/comment/f7afa205_77d5c79c
PS2, Line 9: Set
> Setting
Done
https://review.coreboot.org/c/coreboot/+/56895/comment/4bad2d6f_a2b207c5
PS2, Line 9: deponds
> depends
Done
https://review.coreboot.org/c/coreboot/+/56895/comment/2c37dc3f_ac412f68
PS2, Line 9: Set the clock source deponds on clock request pin for WLAN/SD/SSD device. Also turn off the unused (4/5/6) clock sources.
: Currently in guybeush, clock source 0/1/2/3 are routed for WLAN/SD/WWAN/SSD device.
> Please reflow for 75 characters per line.
Done
https://review.coreboot.org/c/coreboot/+/56895/comment/7461d914_44a43e51
PS2, Line 10: guybeush
> guybrush
Done
https://review.coreboot.org/c/coreboot/+/56895/comment/4a8aee3b_eba9f70f
PS2, Line 14: TEST:
> TEST=
Done
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Hello build bot (Jenkins), Martin Roth, Felix Held,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#5).
Change subject: mb/google/guybrush/var/baseboard: Set Clk request for WLAN/SD/WWAN/SSD device.
......................................................................
mb/google/guybrush/var/baseboard: Set Clk request for WLAN/SD/WWAN/SSD device.
Setting the clock source depends on clock request pin for WLAN/SD/SSD device. Also turn off the unused (4/5/6) clock sources.
In guybrush, clock source 0/1/2/3 are routed for WLAN/SD/WWAN/SSD device.
BUG=b:186384256
BRANCH=none
TEST=Verify the config setting can update to the GPPCLKCONTROL registers.
Signed-off-by: Patrick Huang <patrick.huang(a)amd.corp-partner.google.com>
Change-Id: I240543e92cbc178cee034c37d7c26da0a6bbb7f6
---
M src/mainboard/google/guybrush/variants/baseboard/devicetree.cb
1 file changed, 9 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/56895/5
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Hello build bot (Jenkins), Martin Roth, Felix Held,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#4).
Change subject: mb/google/guybrush/var/baseboard: Set Clk request for WLAN/SD/WWAN/SSD device.
......................................................................
mb/google/guybrush/var/baseboard: Set Clk request for WLAN/SD/WWAN/SSD device.
Setting the clock source depends on clock request pin for WLAN/SD/SSD device. Also turn off the unused (4/5/6) clock sources.
Currently in guybrush, clock source 0/1/2/3 are routed for WLAN/SD/WWAN/SSD device.
BUG=b:186384256
BRANCH=none
TEST=Verify the config setting can update to the GPPCLKCONTROL registers.
Signed-off-by: Patrick Huang <patrick.huang(a)amd.corp-partner.google.com>
Change-Id: I240543e92cbc178cee034c37d7c26da0a6bbb7f6
---
M src/mainboard/google/guybrush/variants/baseboard/devicetree.cb
1 file changed, 9 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/56895/4
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Hello build bot (Jenkins), Martin Roth, Felix Held,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#3).
Change subject: mb/google/guybrush/var/baseboard: Set Clk request for WLAN/SD/WWAN/SSD device.
......................................................................
mb/google/guybrush/var/baseboard: Set Clk request for WLAN/SD/WWAN/SSD device.
Set the clock source deponds on clock request pin for WLAN/SD/SSD device. Also turn off the unused (4/5/6) clock sources.
Currently in guybeush, clock source 0/1/2/3 are routed for WLAN/SD/WWAN/SSD device.
BUG=b:186384256
BRANCH=none
TEST:Verify the config setting can update to the GPPCLKCONTROL registers.
Signed-off-by: Patrick Huang <patrick.huang(a)amd.corp-partner.google.com>
Change-Id: I240543e92cbc178cee034c37d7c26da0a6bbb7f6
---
M src/mainboard/google/guybrush/variants/baseboard/devicetree.cb
1 file changed, 9 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/56895/3
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