Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54724 )
Change subject: mb/google/brya: Add two sensors for DPTF functionality
......................................................................
Patch Set 2:
(1 comment)
This change is ready for review.
Patchset:
PS2:
As per b:181271666 comment#34 and #36, we need this CL.
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Jakub Czapiga has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56601 )
Change subject: tests: Add lib/cbfs-verification-test test case
......................................................................
Patch Set 9:
(1 comment)
File tests/lib/cbfs-verification-test.c:
https://review.coreboot.org/c/coreboot/+/56601/comment/093a1036_d4fa41c0
PS2, Line 4: #define __noreturn
> Resolved?
I think so. die() from tests/stubs/die.c calls fail() which then calls either abort(), exit(-1), or longjmp(). All listed function are __noreturn (at least for my GCC and its headers). Do we really need to mark _fail() as __noreturn?
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Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57035 )
Change subject: soc/intel/alderlake: set power limits dynamically for thermal
......................................................................
Patch Set 2:
(2 comments)
File src/soc/intel/alderlake/systemagent.c:
https://review.coreboot.org/c/coreboot/+/57035/comment/cbbd732d_3bb4b007
PS1, Line 51: u8 get_cpu_tdp(void)
> should this go in common code?
Ack
https://review.coreboot.org/c/coreboot/+/57035/comment/671cb1cd_593d0285
PS1, Line 53: msr_t msr = rdmsr(MSR_PLATFORM_INFO);
> this value read from `rdmsr` looks unused (msr is reassigned on 57 and not read before that)
Done
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Felix Held has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/56816 )
Change subject: [TESTME] mb/amd/majolica,mb/google/guybrush,mancomb: add SPI config to devicetree
......................................................................
Abandoned
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56924 )
Change subject: mb/google/dedede/var/driblee: Generate RAM ID and SPD file
......................................................................
mb/google/dedede/var/driblee: Generate RAM ID and SPD file
Add the support RAM parts for Driblee.
Here is the ram part number list:
1. Hynix H9HCNNNBKMMLXR-NEE
2. Micron MT53E512M32D2NP-046 WT:F
3. Samsung K4U6E3S4AA-MGCR
4. Micron MT53E512M32D1NP-046 WT:B
BUG=b:195619346
BRANCH=keeby
TEST=emerge-keeby coreboot
Signed-off-by: Frank Wu <frank_wu(a)compal.corp-partner.google.com>
Change-Id: I683acb91ec13cbd772e732d7f81152ceb3cefc1c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56924
Reviewed-by: EricR Lai <ericr_lai(a)compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/mainboard/google/dedede/variants/driblee/memory/Makefile.inc
M src/mainboard/google/dedede/variants/driblee/memory/dram_id.generated.txt
M src/mainboard/google/dedede/variants/driblee/memory/mem_parts_used.txt
3 files changed, 10 insertions(+), 13 deletions(-)
Approvals:
build bot (Jenkins): Verified
EricR Lai: Looks good to me, approved
diff --git a/src/mainboard/google/dedede/variants/driblee/memory/Makefile.inc b/src/mainboard/google/dedede/variants/driblee/memory/Makefile.inc
index b0ca222..42c6cf4 100644
--- a/src/mainboard/google/dedede/variants/driblee/memory/Makefile.inc
+++ b/src/mainboard/google/dedede/variants/driblee/memory/Makefile.inc
@@ -1,5 +1,5 @@
## SPDX-License-Identifier: GPL-2.0-or-later
## This is an auto-generated file. Do not edit!!
-## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate.
-SPD_SOURCES = placeholder.spd.hex
+SPD_SOURCES =
+SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = H9HCNNNBKMMLXR-NEE, MT53E512M32D2NP-046 WT:F, K4U6E3S4AA-MGCR, MT53E512M32D1NP-046 WT:B
diff --git a/src/mainboard/google/dedede/variants/driblee/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/driblee/memory/dram_id.generated.txt
index fa24790..0dbc38e 100644
--- a/src/mainboard/google/dedede/variants/driblee/memory/dram_id.generated.txt
+++ b/src/mainboard/google/dedede/variants/driblee/memory/dram_id.generated.txt
@@ -1 +1,5 @@
DRAM Part Name ID to assign
+H9HCNNNBKMMLXR-NEE 0 (0000)
+MT53E512M32D2NP-046 WT:F 0 (0000)
+K4U6E3S4AA-MGCR 0 (0000)
+MT53E512M32D1NP-046 WT:B 0 (0000)
diff --git a/src/mainboard/google/dedede/variants/driblee/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/driblee/memory/mem_parts_used.txt
index e4258b5..c1e9e0c 100644
--- a/src/mainboard/google/dedede/variants/driblee/memory/mem_parts_used.txt
+++ b/src/mainboard/google/dedede/variants/driblee/memory/mem_parts_used.txt
@@ -1,11 +1,4 @@
-# This is a CSV file containing a list of memory parts used by this variant.
-# One part per line with an optional fixed ID in column 2.
-# Only include a fixed ID if it is required for legacy reasons!
-# Generated IDs are dependent on the order of parts in this file,
-# so new parts must always be added at the end of the file!
-#
-# Generate an updated Makefile.inc and dram_id.generated.txt by running the
-# gen_part_id tool from util/spd_tools/{ddr4,lp4x}.
-# See util/spd_tools/{ddr4,lp4x}/README.md for more details and instructions.
-
-# Part Name
+H9HCNNNBKMMLXR-NEE
+MT53E512M32D2NP-046 WT:F
+K4U6E3S4AA-MGCR
+MT53E512M32D1NP-046 WT:B
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57000 )
Change subject: mb/google/brya: set tcc_offset value to 10
......................................................................
mb/google/brya: set tcc_offset value to 10
Set tcc_offset value to 10 in devicetree for Thermal Control
Circuit (TCC) activation feature. This value is suggested by
Thermal team.
BUGb=b:195706434
BRANCH=None
TEST=Built for brya platform and verified the MSR value
Change-Id: I22573e8ca935d99a16b0876768df169db4e61c4d
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57000
Reviewed-by: EricR Lai <ericr_lai(a)compal.corp-partner.google.com>
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---
M src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
1 file changed, 2 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
EricR Lai: Looks good to me, approved
Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
index 3281902..762aa84 100644
--- a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
+++ b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
@@ -19,6 +19,8 @@
# DPTF enable
register "dptf_enable" = "1"
+ register "tcc_offset" = "10" # TCC of 90
+
# Enable heci communication
register "HeciEnabled" = "1"
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Change subject: soc/intel/alderlake: set power limits dynamically for thermal
......................................................................
Patch Set 2:
(2 comments)
File src/soc/intel/alderlake/systemagent.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-126400):
https://review.coreboot.org/c/coreboot/+/57035/comment/c8b40d21_6e174ed0
PS2, Line 89: soc_config = &config->power_limits_config[ADL_P_POWER_LIMITS_682_28W_CORE];
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-126400):
https://review.coreboot.org/c/coreboot/+/57035/comment/de73ee40_dc7fd2ce
PS2, Line 91: soc_config = &config->power_limits_config[ADL_P_POWER_LIMITS_682_45W_CORE];
line over 96 characters
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Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Patrick Rudolph, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/57035
to look at the new patch set (#2).
Change subject: soc/intel/alderlake: set power limits dynamically for thermal
......................................................................
soc/intel/alderlake: set power limits dynamically for thermal
Set power limit values dynamically based on TDP of SKU.
BUG=b:194745919
BRANCH=None
TEST=Build FW and test on brya0 board,
Change-Id: Ic331a3debb076ef08a312a31edc1468974fd4902
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com>
---
M src/soc/intel/alderlake/chip.h
M src/soc/intel/alderlake/chipset.cb
M src/soc/intel/alderlake/systemagent.c
M src/soc/intel/common/block/include/intelblocks/power_limit.h
M src/soc/intel/common/block/power_limit/power_limit.c
5 files changed, 35 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/57035/2
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