coreboot-gerrit July 2021

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Change in coreboot[master]: postcodes: replaced postcode values with their respective defined con...
by Sindhoor Tilak (Code Review) 10 Jun '23

10 Jun '23

Sindhoor Tilak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42503 ) Change subject: postcodes: replaced postcode values with their respective defined constants ...................................................................... postcodes: replaced postcode values with their respective defined constants - Replaced existing post_code() call values with the defined constants - Reorganized certain post_code calls to match their defines - Added few post_code() calls which were missing - Deleted certain duplicate post_code() calls Signed-off-by: Sindhoor Tilak <sindhoor(a)sin9yt.net> Change-Id: If32f43104a829bd1db0d5f5340cc94bf0c717c39 --- M src/arch/x86/postcar.c M src/arch/x86/postcar_loader.c M src/arch/x86/tables.c M src/cpu/intel/car/bootblock.c M src/cpu/intel/car/core2/cache_as_ram.S M src/cpu/intel/car/non-evict/cache_as_ram.S M src/cpu/intel/car/non-evict/exit_car.S M src/cpu/intel/car/p3/cache_as_ram.S M src/cpu/intel/car/p4-netburst/cache_as_ram.S M src/cpu/intel/car/p4-netburst/exit_car.S M src/cpu/intel/haswell/romstage.c M src/cpu/qemu-x86/bootblock.c M src/cpu/qemu-x86/cache_as_ram_bootblock.S M src/cpu/x86/mtrr/mtrr.c M src/device/pci_device.c M src/drivers/amd/agesa/cache_as_ram.S M src/drivers/amd/agesa/romstage.c M src/drivers/intel/fsp1_1/cache_as_ram.S M src/drivers/intel/fsp1_1/fsp_util.c M src/drivers/intel/fsp1_1/raminit.c M src/drivers/intel/fsp1_1/romstage.c M src/drivers/intel/fsp2_0/memory_init.c M src/lib/ramtest.c M src/mainboard/amd/thatcher/bootblock.c M src/mainboard/asus/f2a85-m/romstage.c M src/mainboard/bap/ode_e21XX/romstage.c M src/mainboard/msi/ms7721/romstage.c M src/northbridge/intel/pineview/romstage.c M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/sandybridge/raminit_mrc.c M src/northbridge/intel/sandybridge/romstage.c M src/soc/amd/picasso/bootblock/pre_c.S M src/soc/amd/picasso/romstage.c M src/soc/amd/stoneyridge/bootblock/bootblock.c M src/soc/amd/stoneyridge/chip.c M src/soc/amd/stoneyridge/romstage.c M src/soc/intel/apollolake/bootblock/bootblock.c M src/soc/intel/baytrail/romstage/raminit.c M src/soc/intel/broadwell/romstage/raminit.c M src/soc/intel/broadwell/romstage/romstage.c M src/soc/intel/common/block/cpu/car/cache_as_ram.S M src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S M src/soc/intel/quark/bootblock/esram_init.S M src/soc/intel/quark/romstage/fsp_params.c M src/soc/intel/skylake/bootblock/bootblock.c M src/soc/intel/tigerlake/bootblock/bootblock.c M src/soc/intel/xeon_sp/bootblock.c M src/soc/intel/xeon_sp/romstage.c 48 files changed, 160 insertions(+), 125 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/42503/1 diff --git a/src/arch/x86/postcar.c b/src/arch/x86/postcar.c index dcacc70..0a3698c 100644 --- a/src/arch/x86/postcar.c +++ b/src/arch/x86/postcar.c @@ -30,6 +30,8 @@ display_mtrrs(); + post_code(POST_ENTRY_RAMSTAGE); /* Load and run ramstage. */ run_ramstage(); + post_code(POST_RAMSTAGE_DIE); } diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c index 084384e..146a3b6 100644 --- a/src/arch/x86/postcar_loader.c +++ b/src/arch/x86/postcar_loader.c @@ -97,12 +97,14 @@ void prepare_and_run_postcar(struct postcar_frame *pcf) { if (postcar_frame_init(pcf, 0)) + post_code(POST_EXIT_CAR_INIT_FAIL); die("Unable to initialize postcar frame.\n"); fill_postcar_frame(pcf); postcar_frame_common_mtrrs(pcf); + post_code(POST_ENTRY_POST_CAR); run_postcar_phase(pcf); /* We do not return here. */ } diff --git a/src/arch/x86/tables.c b/src/arch/x86/tables.c index 492674c..8783925 100644 --- a/src/arch/x86/tables.c +++ b/src/arch/x86/tables.c @@ -17,7 +17,7 @@ unsigned long high_table_pointer; #define MAX_PIRQ_TABLE_SIZE (4 * 1024) - post_code(0x9a); + post_code(POST_TABLE_IRQ_WRITE); /* This table must be between 0x0f0000 and 0x100000 */ rom_table_end = write_pirq_routing_table(rom_table_end); @@ -49,7 +49,7 @@ unsigned long high_table_pointer; #define MAX_MP_TABLE_SIZE (4 * 1024) - post_code(0x9b); + post_code(POST_TABLE_MP_WRITE); /* The smp table must be in 0-1K, 639K-640K, or 960K-1M */ rom_table_end = write_smp_table(rom_table_end); @@ -78,7 +78,7 @@ unsigned long high_table_pointer; const size_t max_acpi_size = CONFIG_MAX_ACPI_TABLE_SIZE_KB * KiB; - post_code(0x9c); + post_code(POST_TABLE_ACPI_WRITE); /* Write ACPI tables to F segment and high tables area */ diff --git a/src/cpu/intel/car/bootblock.c b/src/cpu/intel/car/bootblock.c index dd9a772..1070a9b 100644 --- a/src/cpu/intel/car/bootblock.c +++ b/src/cpu/intel/car/bootblock.c @@ -3,6 +3,7 @@ #include <bootblock_common.h> #include <arch/bootblock.h> #include <cpu/x86/bist.h> +#include <console/console.h> static uint32_t saved_bist; @@ -22,6 +23,7 @@ bootblock_early_northbridge_init(); bootblock_early_southbridge_init(); bootblock_early_cpu_init(); + post_code(POST_BOOTBLOCK_SOC_EARLYINIT); } void bootblock_soc_init(void) diff --git a/src/cpu/intel/car/core2/cache_as_ram.S b/src/cpu/intel/car/core2/cache_as_ram.S index 837394c..2983257 100644 --- a/src/cpu/intel/car/core2/cache_as_ram.S +++ b/src/cpu/intel/car/core2/cache_as_ram.S @@ -12,7 +12,7 @@ bootblock_pre_c_entry: cache_as_ram: - post_code(0x20) + post_code(POST_BOOTBLOCK_PRE_C_EXIT) /* Send INIT IPI to all excluding ourself. */ movl $0x000C4500, %eax @@ -25,7 +25,7 @@ bt $12, %eax jc wait_for_sipi - post_code(0x22) + post_code(POST_CAR_INIT_IPI) /* Clear/disable fixed MTRRs */ mov $fixed_mtrr_list_size, %ebx @@ -38,6 +38,8 @@ wrmsr jnz clear_fixed_mtrr + post_code(POST_CAR_FIXED_MTRR) + /* Figure out how many MTRRs we have, and clear them out */ mov $MTRR_CAP_MSR, %ecx rdmsr @@ -54,7 +56,7 @@ dec %ebx jnz clear_var_mtrr - post_code(0x22) + post_code(POST_CAR_VARIABLE_MTRR) /* Configure the default memory type to uncacheable. */ movl $MTRR_DEF_TYPE_MSR, %ecx rdmsr @@ -79,7 +81,6 @@ movl $MTRR_PHYS_MASK(1), %ecx wrmsr - post_code(0x23) /* Set Cache-as-RAM base address. */ movl $(MTRR_PHYS_BASE(0)), %ecx movl $_car_mtrr_start, %eax @@ -87,7 +88,7 @@ xorl %edx, %edx wrmsr - post_code(0x24) + post_code(POST_CAR_BASE_ADDRESS) /* Set Cache-as-RAM mask. */ movl $(MTRR_PHYS_MASK(0)), %ecx rdmsr @@ -95,7 +96,7 @@ orl $MTRR_PHYS_MASK_VALID, %eax wrmsr - post_code(0x25) + post_code(POST_CAR_MTRR_ENABLE) /* Enable MTRR. */ movl $MTRR_DEF_TYPE_MSR, %ecx @@ -115,6 +116,7 @@ invd movl %eax, %cr0 + post_code(POST_CAR_CACHE_CLEAR) /* Clear the cache memory region. This will also fill up the cache. */ cld xorl %eax, %eax @@ -123,7 +125,7 @@ shr $2, %ecx rep stosl - post_code(0x26) + post_code(POST_CAR_CACHE_EVICTION) /* Enable Cache-as-RAM mode by disabling cache. */ movl %cr0, %eax orl $CR0_CacheDisable, %eax @@ -142,12 +144,13 @@ orl $MTRR_PHYS_MASK_VALID, %eax wrmsr - post_code(0x28) + post_code(POST_CAR_INIT_CACHE) /* Enable cache. */ movl %cr0, %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax movl %eax, %cr0 + post_code(POST_ENTRY_BOOTBLOCK_STACK) /* Setup the stack. */ mov $_ecar_stack, %esp @@ -165,7 +168,7 @@ pushl %eax /* tsc[31:0] */ before_c_entry: - post_code(0x29) + post_code(POST_ENTRY_C_BOOTBLOCK) call bootblock_c_entry_bist /* Should never see this postcode */ diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S index d087365..94bfeaa 100644 --- a/src/cpu/intel/car/non-evict/cache_as_ram.S +++ b/src/cpu/intel/car/non-evict/cache_as_ram.S @@ -17,7 +17,7 @@ jmp check_mtrr /* Check if CPU properly reset */ cache_as_ram: - post_code(0x20) + post_code(POST_BOOTBLOCK_PRE_C_EXIT) /* Send INIT IPI to all excluding ourself. */ movl $0x000C4500, %eax @@ -30,14 +30,13 @@ bt $12, %eax jc wait_for_sipi - post_code(0x21) + post_code(POST_CAR_INIT_IPI) /* Clean-up MTRR_DEF_TYPE_MSR. */ movl $MTRR_DEF_TYPE_MSR, %ecx xorl %eax, %eax xorl %edx, %edx wrmsr - post_code(0x22) /* Clear/disable fixed MTRRs */ mov $fixed_mtrr_list_size, %ebx xor %eax, %eax @@ -49,6 +48,8 @@ wrmsr jnz clear_fixed_mtrr + post_code(POST_CAR_FIXED_MTRR) + /* Zero out all variable range MTRRs. */ movl $MTRR_CAP_MSR, %ecx rdmsr @@ -64,6 +65,7 @@ dec %edi jnz clear_var_mtrrs + post_code(POST_CAR_VARIABLE_MTRR) /* Determine CPU_ADDR_BITS and load PHYSMASK high word to %edx. */ movl $0x80000008, %eax cpuid @@ -84,7 +86,6 @@ wrmsr - post_code(0x23) /* Set Cache-as-RAM base address. */ movl $(MTRR_PHYS_BASE(0)), %ecx movl $_car_mtrr_start, %eax @@ -92,7 +93,7 @@ xorl %edx, %edx wrmsr - post_code(0x24) + post_code(POST_CAR_BASE_ADDRESS) /* Set Cache-as-RAM mask. */ movl $(MTRR_PHYS_MASK(0)), %ecx rdmsr @@ -113,7 +114,7 @@ orl $MTRR_PHYS_MASK_VALID, %eax wrmsr - post_code(0x25) + post_code(POST_CAR_MTRR_ENABLE) /* Enable MTRR. */ movl $MTRR_DEF_TYPE_MSR, %ecx @@ -170,6 +171,7 @@ andl $~2, %eax wrmsr + post_code(POST_CAR_CACHE_CLEAR) /* Clear the cache memory region. This will also fill up the cache. */ cld xorl %eax, %eax @@ -178,13 +180,13 @@ shr $2, %ecx rep stosl + post_code(POST_CAR_CACHE_EVICTION) /* enable the 'no eviction run' state */ movl $NoEvictMod_MSR, %ecx rdmsr orl $3, %eax wrmsr - post_code(0x26) /* Enable Cache-as-RAM mode by disabling cache. */ movl %cr0, %eax orl $CR0_CacheDisable, %eax @@ -195,12 +197,13 @@ orl $MTRR_PHYS_MASK_VALID, %eax wrmsr - post_code(0x28) + post_code(POST_CAR_INIT_CACHE) /* Enable cache. */ movl %cr0, %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax movl %eax, %cr0 + post_code(POST_ENTRY_BOOTBLOCK_STACK) /* Setup the stack. */ mov $_ecar_stack, %esp @@ -218,7 +221,7 @@ pushl %eax /* tsc[31:0] */ before_c_entry: - post_code(0x29) + post_code(POST_ENTRY_C_BOOTBLOCK) call bootblock_c_entry_bist /* Should never see this postcode */ diff --git a/src/cpu/intel/car/non-evict/exit_car.S b/src/cpu/intel/car/non-evict/exit_car.S index 2834e76..260b90e 100644 --- a/src/cpu/intel/car/non-evict/exit_car.S +++ b/src/cpu/intel/car/non-evict/exit_car.S @@ -12,14 +12,14 @@ chipset_teardown_car: pop %esp - post_code(0x30) + post_code(POST_ENTRY_POST_CAR) /* Disable cache. */ movl %cr0, %eax orl $CR0_CacheDisable, %eax movl %eax, %cr0 - post_code(0x31) + post_code(POST_CAR_CACHE_EVICTION) /* Disable MTRR. */ movl $MTRR_DEF_TYPE_MSR, %ecx diff --git a/src/cpu/intel/car/p3/cache_as_ram.S b/src/cpu/intel/car/p3/cache_as_ram.S index 71e3447..8e5e6e7 100644 --- a/src/cpu/intel/car/p3/cache_as_ram.S +++ b/src/cpu/intel/car/p3/cache_as_ram.S @@ -12,7 +12,7 @@ bootblock_pre_c_entry: cache_as_ram: - post_code(0x20) + post_code(POST_BOOTBLOCK_PRE_C_EXIT) /* Clear/disable fixed MTRRs */ mov $fixed_mtrr_list_size, %ebx @@ -24,6 +24,7 @@ movzwl fixed_mtrr_list(%ebx), %ecx wrmsr jnz clear_fixed_mtrr + post_code(POST_CAR_FIXED_MTRR) /* Figure out how many MTRRs we have, and clear them out */ mov $MTRR_CAP_MSR, %ecx @@ -40,7 +41,7 @@ inc %ecx dec %ebx jnz clear_var_mtrr - post_code(0x21) + post_code(POST_CAR_VARIABLE_MTRR) /* Configure the default memory type to uncacheable. */ movl $MTRR_DEF_TYPE_MSR, %ecx @@ -48,8 +49,6 @@ andl $(~0x00000cff), %eax wrmsr - post_code(0x22) - /* Determine CPU_ADDR_BITS and load PHYSMASK high word to %edx. */ movl $1, %eax cpuid @@ -66,8 +65,6 @@ movl $MTRR_PHYS_MASK(1), %ecx wrmsr - post_code(0x2a) - /* Set Cache-as-RAM base address. */ movl $(MTRR_PHYS_BASE(0)), %ecx movl $_car_mtrr_start, %eax @@ -75,6 +72,8 @@ xorl %edx, %edx wrmsr + post_code(POST_CAR_BASE_ADDRESS) + /* Set Cache-as-RAM mask. */ movl $(MTRR_PHYS_MASK(0)), %ecx rdmsr @@ -82,7 +81,7 @@ orl $MTRR_PHYS_MASK_VALID, %eax wrmsr - post_code(0x2b) + post_code(POST_CAR_MTRR_ENABLE) /* Enable MTRR. */ movl $MTRR_DEF_TYPE_MSR, %ecx @@ -90,14 +89,13 @@ orl $MTRR_DEF_TYPE_EN, %eax wrmsr - post_code(0x2c) - /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ movl %cr0, %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax invd movl %eax, %cr0 + post_code(POST_CAR_CACHE_EVICTION) /* Read then clear the CAR region. This will also fill up the cache. * IMPORTANT: The read is mandatory. */ @@ -112,7 +110,6 @@ xorl %eax, %eax rep stosl - post_code(0x2d) /* Enable Cache-as-RAM mode by disabling cache. */ movl %cr0, %eax orl $CR0_CacheDisable, %eax @@ -131,12 +128,13 @@ orl $MTRR_PHYS_MASK_VALID, %eax wrmsr - post_code(0x2e) + post_code(POST_CAR_INIT_CACHE) /* Enable cache. */ movl %cr0, %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax movl %eax, %cr0 + post_code(POST_ENTRY_BOOTBLOCK_STACK) /* Setup the stack. */ mov $_ecar_stack, %esp @@ -154,7 +152,7 @@ pushl %eax /* tsc[31:0] */ before_c_entry: - post_code(0x29) + post_code(POST_ENTRY_C_BOOTBLOCK) call bootblock_c_entry_bist /* Should never see this postcode */ diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S index 4e36538..74ff544 100644 --- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S +++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S @@ -16,7 +16,7 @@ bootblock_pre_c_entry: cache_as_ram: - post_code(0x20) + post_code(POST_BOOTBLOCK_PRE_C_EXIT) movl $LAPIC_BASE_MSR, %ecx rdmsr @@ -33,6 +33,7 @@ movzwl fixed_mtrr_list(%ebx), %ecx wrmsr jnz clear_fixed_mtrr + post_code(POST_CAR_FIXED_MTRR) /* Figure out how many MTRRs we have, and clear them out */ mov $MTRR_CAP_MSR, %ecx @@ -49,7 +50,7 @@ inc %ecx dec %ebx jnz clear_var_mtrr - post_code(0x21) + post_code(POST_CAR_VARIABLE_MTRR) /* Configure the default memory type to uncacheable. */ movl $MTRR_DEF_TYPE_MSR, %ecx @@ -57,8 +58,6 @@ andl $(~0x00000cff), %eax wrmsr - post_code(0x22) - /* Determine CPU_ADDR_BITS and load PHYSMASK high * word to %edx. */ @@ -207,15 +206,14 @@ sipi_complete: - post_code(0x2a) - /* Set Cache-as-RAM base address. */ movl $(MTRR_PHYS_BASE(0)), %ecx movl $_car_mtrr_start, %eax orl $MTRR_TYPE_WRBACK, %eax xorl %edx, %edx wrmsr - + post_code(POST_CAR_BASE_ADDRESS) + /* Set Cache-as-RAM mask. */ movl $(MTRR_PHYS_MASK(0)), %ecx rdmsr @@ -223,7 +221,7 @@ orl $MTRR_PHYS_MASK_VALID, %eax wrmsr - post_code(0x2b) + post_code(POST_CAR_MTRR_ENABLE) /* Enable MTRR. */ movl $MTRR_DEF_TYPE_MSR, %ecx @@ -293,7 +291,7 @@ jmp update_bsp_microcode end_microcode_update: #endif - post_code(0x2d) + post_code(POST_CAR_CACHE_EVICTION) /* Disable caching to change MTRR's. */ movl %cr0, %eax orl $CR0_CacheDisable, %eax @@ -333,13 +331,14 @@ wrmsr fill_cache: - post_code(0x2e) + post_code(POST_CAR_INIT_CACHE) /* Enable cache. */ movl %cr0, %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax invd movl %eax, %cr0 + post_code(POST_CAR_CACHE_CLEAR) /* Clear the cache memory region. This will also fill up the cache. */ cld xorl %eax, %eax @@ -348,6 +347,7 @@ shr $2, %ecx rep stosl + post_code(POST_ENTRY_BOOTBLOCK_STACK) /* Setup the stack. */ mov $_ecar_stack, %esp @@ -365,7 +365,7 @@ pushl %eax /* tsc[31:0] */ before_c_entry: - post_code(0x2f) + post_code(POST_ENTRY_C_BOOTBLOCK) call bootblock_c_entry_bist /* Should never see this postcode */ diff --git a/src/cpu/intel/car/p4-netburst/exit_car.S b/src/cpu/intel/car/p4-netburst/exit_car.S index 108342f..0dec603 100644 --- a/src/cpu/intel/car/p4-netburst/exit_car.S +++ b/src/cpu/intel/car/p4-netburst/exit_car.S @@ -10,7 +10,7 @@ chipset_teardown_car: pop %esp - post_code(0x30) + post_code(POST_ENTRY_POST_CAR) /* Disable cache. */ movl %cr0, %eax diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 4b56301..04abdb2 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -19,7 +19,7 @@ int wake_from_s3; enable_lapic(); - + post_code(POST_ENTRY_ROMSTAGE); wake_from_s3 = early_pch_init(params->gpio_map, params->rcba_config); /* Perform some early chipset initialization required @@ -56,10 +56,11 @@ params->copy_spd(params->pei_data); sdram_initialize(params->pei_data); + post_code(POST_ROM_SDRAM_INIT); timestamp_add_now(TS_AFTER_INITRAM); - post_code(0x3b); + post_code(POST_RAM_INIT); intel_early_me_status(); @@ -80,5 +81,5 @@ romstage_handoff_init(wake_from_s3); - post_code(0x3f); + post_code(POST_ROM_STAGE_HANDOFF); } diff --git a/src/cpu/qemu-x86/bootblock.c b/src/cpu/qemu-x86/bootblock.c index 1b46403e..3675e4a 100644 --- a/src/cpu/qemu-x86/bootblock.c +++ b/src/cpu/qemu-x86/bootblock.c @@ -6,11 +6,12 @@ asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist) { - post_code(0x05); + post_code(POST_ENTRY_C_BOOTBLOCK); /* Halt if there was a built in self test failure */ if (bist) { console_init(); + post_code(POST_CONSOLE_READY); report_bist_failure(bist); } diff --git a/src/cpu/qemu-x86/cache_as_ram_bootblock.S b/src/cpu/qemu-x86/cache_as_ram_bootblock.S index 30f9f9c..ebe5de1 100644 --- a/src/cpu/qemu-x86/cache_as_ram_bootblock.S +++ b/src/cpu/qemu-x86/cache_as_ram_bootblock.S @@ -6,12 +6,13 @@ bootblock_pre_c_entry: cache_as_ram: - post_code(0x20) + post_code(POST_BOOTBLOCK_PRE_C_EXIT) /* * Nothing to do here on qemu, RAM works just fine without any * initialization. */ + post_code(POST_CAR_CACHE_CLEAR) /* Clear the cache memory region. This will also clear CAR GLOBAL */ movl $_car_region_start, %edi movl $_car_region_end, %ecx @@ -20,7 +21,7 @@ xorl %eax, %eax rep stosl - post_code(0x21) + post_code(POST_ENTRY_BOOTBLOCK_STACK) movl $_ecar_stack, %esp @@ -47,7 +48,7 @@ #endif before_c_entry: - post_code(0x29) + post_code(POST_ENTRY_C_BOOTBLOCK) call bootblock_c_entry_bist /* Never returns */ .Lhlt: diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index 77525a7..f961f41 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -826,7 +826,7 @@ printk(BIOS_DEBUG, "\n"); - post_code(0x93); + post_code(POST_BOOTBLOCK_MTRR_CHECK); } static bool put_back_original_solution; diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 032e15c..0ecf86a 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -1237,7 +1237,7 @@ max_devfn=0xff; } - post_code(0x24); + post_code(POST_PCI_SCAN_BUS); /* * Probe all devices/functions on this bus with some optimization for @@ -1317,7 +1317,7 @@ * side of any bridges that may be on this bus plus any devices. * Return how far we've got finding sub-buses. */ - post_code(0x55); + post_code(POST_PCI_SCAN_EXIT); } typedef enum { diff --git a/src/drivers/amd/agesa/cache_as_ram.S b/src/drivers/amd/agesa/cache_as_ram.S index 8e7ea29..8a39a2f 100644 --- a/src/drivers/amd/agesa/cache_as_ram.S +++ b/src/drivers/amd/agesa/cache_as_ram.S @@ -27,7 +27,7 @@ */ bootblock_pre_c_entry: - post_code(0xa0) + post_code(POST_BOOTBLOCK_PRE_C_EXIT) AMD_ENABLE_STACK @@ -42,6 +42,7 @@ test $LAPIC_BASE_MSR_BOOTSTRAP_PROCESSOR, %eax jz ap_entry + post_code(POST_ENTRY_BOOTBLOCK_STACK) mov $_ecar_stack, %esp /* Align the stack and keep aligned for call to bootblock_c_entry() */ @@ -53,7 +54,7 @@ movd %mm1, %eax pushl %eax /* tsc[31:0] */ - post_code(0xa2) + post_code(POST_ENTRY_C_BOOTBLOCK) call bootblock_c_entry diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c index 617416a..be45463 100644 --- a/src/drivers/amd/agesa/romstage.c +++ b/src/drivers/amd/agesa/romstage.c @@ -75,6 +75,7 @@ cbmem_initted = !cbmem_recovery(cb->s3resume); if (cb->s3resume && !cbmem_initted) { + post_code(POST_CBMEM_RECOVER_FAIL); printk(BIOS_EMERG, "Unable to recover CBMEM\n"); halt(); } @@ -84,6 +85,7 @@ postcar_frame_init(&pcf, HIGH_ROMSTAGE_STACK_SIZE); recover_postcar_frame(&pcf, cb->s3resume); + post_code(POST_ENTRY_POST_CAR); run_postcar_phase(&pcf); /* We do not return. */ } diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.S b/src/drivers/intel/fsp1_1/cache_as_ram.S index 31c3580..7691033 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.S +++ b/src/drivers/intel/fsp1_1/cache_as_ram.S @@ -32,10 +32,11 @@ movd %eax, %mm1 cache_as_ram: - post_code(0x20) + post_code(POST_BOOTBLOCK_PRE_C_EXIT) /* Cache the rom and update the microcode */ cache_rom: + POST_CAR_CACHE_EVICTION /* Disable cache */ movl %cr0, %eax orl $CR0_CacheDisable, %eax @@ -62,6 +63,7 @@ rdmsr orl $MTRR_DEF_TYPE_EN, %eax wrmsr + post_code(POST_CAR_MTRR_ENABLE) /* The Google FSP release for Braswell has broken microcode update code and FSP needs the installed microcode revision to be non zero. @@ -132,6 +134,7 @@ cmp $0, %eax jne halt2 + post_code(POST_ENTRY_BOOTBLOCK_STACK) /* Setup bootloader stack */ movl %edx, %esp @@ -167,7 +170,7 @@ pushl %eax /* tsc[31:0] */ before_romstage: - post_code(0x2A) + post_code(POST_ENTRY_C_BOOTBLOCK) /* Call bootblock_c_entry(uint64_t base_timestamp) */ call bootblock_c_entry diff --git a/src/drivers/intel/fsp1_1/fsp_util.c b/src/drivers/intel/fsp1_1/fsp_util.c index 9e7865d..1696df0 100644 --- a/src/drivers/intel/fsp1_1/fsp_util.c +++ b/src/drivers/intel/fsp1_1/fsp_util.c @@ -123,7 +123,7 @@ fsp_header_ptr = (void *)find_fsp(CONFIG_FSP_LOC); if ((u32)fsp_header_ptr < 0xff) { /* output something in case there is no serial */ - post_code(0x4F); + post_code(POST_FSP_FAILURE); die("Can't find the FSP!\n"); } } diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c index dfa3258..8ae4ff7 100644 --- a/src/drivers/intel/fsp1_1/raminit.c +++ b/src/drivers/intel/fsp1_1/raminit.c @@ -50,7 +50,7 @@ * set to NULL. This indicates that the FSP code will use the UPD * region in the FSP binary. */ - post_code(POST_MEM_PREINIT_PREP_START); + post_code(POST_RAM_INIT); fsp_header = params->chipset_context; vpd_ptr = (VPD_DATA_REGION *)(fsp_header->CfgRegionOffset + fsp_header->ImageBase); @@ -110,7 +110,7 @@ post_code(POST_FSP_MEMORY_INIT); status = fsp_memory_init(&fsp_memory_init_params); mainboard_after_memory_init(); - post_code(0x37); + post_code(POST_MAINBOARD_SOC_INIT_EXIT); timestamp_add_now(TS_FSP_MEMORY_INIT_END); printk(BIOS_DEBUG, "FspMemoryInit returned 0x%08x\n", status); @@ -146,6 +146,7 @@ } else if (cbmem_initialize_id_size(CBMEM_ID_FSP_RESERVED_MEMORY, fsp_reserved_bytes)) { #if CONFIG(HAVE_ACPI_RESUME) + post_code(POST_CBMEM_RECOVER_FAIL); printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n"); /* Failed S3 resume, reset to come up cleanly */ /* FIXME: A "system" reset is likely enough: */ diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c index 46df1c8..b8c8c76 100644 --- a/src/drivers/intel/fsp1_1/romstage.c +++ b/src/drivers/intel/fsp1_1/romstage.c @@ -25,7 +25,7 @@ bool s3wake; struct region_device rdev; - post_code(0x32); + post_code(POST_ENTRY_ROMSTAGE); timestamp_add_now(TS_BEFORE_INITRAM); @@ -35,7 +35,7 @@ /* Perform remaining SOC initialization */ soc_pre_ram_init(params); - post_code(0x33); + post_code(POST_SOC_RAM_PREINIT); /* Check recovery and MRC cache */ params->saved_data_size = 0; @@ -100,7 +100,7 @@ .chipset_context = fih, }; - post_code(0x30); + post_code(POST_ENTRY_ROMSTAGE); timestamp_add_now(TS_START_ROMSTAGE); @@ -126,13 +126,13 @@ /* Board initialization before and after RAM is enabled */ mainboard_pre_raminit(&params); - post_code(0x31); - + post_code(POST_MEM_PREINIT_EXIT); + post_code(POST_RAM_INIT); /* Initialize memory */ raminit_common(&params); soc_after_ram_init(&params); - post_code(0x38); + } /* Initialize the power state */ diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 7f5d389..59f84d7 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -72,6 +72,7 @@ } else if (cbmem_initialize_id_size(CBMEM_ID_FSP_RESERVED_MEMORY, range_entry_size(&fsp_mem))) { if (CONFIG(HAVE_ACPI_RESUME)) { + post_code(POST_CBMEM_RECOVER_FAIL); printk(BIOS_ERR, "Failed to recover CBMEM in S3 resume.\n"); /* Failed S3 resume, reset to come up cleanly */ diff --git a/src/lib/ramtest.c b/src/lib/ramtest.c index c6cd7a4..b357dc0 100644 --- a/src/lib/ramtest.c +++ b/src/lib/ramtest.c @@ -108,7 +108,7 @@ } } if (failures) { - post_code(0xea); + post_code(POST_RAM_TEST_FAIL); printk(BIOS_DEBUG, "\nDRAM did _NOT_ verify!\n"); return 1; } @@ -126,6 +126,7 @@ */ printk(BIOS_DEBUG, "Testing DRAM at: %08lx\n", start); if (ram_bitset_nodie(start)) + post_code(POST_RAM_FAILURE); die("DRAM ERROR"); printk(BIOS_DEBUG, "Done.\n"); } @@ -198,7 +199,7 @@ write_phys(dst, backup); if (fail) { - post_code(0xea); + post_code(POST_RAM_FAILURE); die("RAM INIT FAILURE!\n"); } phys_memory_barrier(); diff --git a/src/mainboard/amd/thatcher/bootblock.c b/src/mainboard/amd/thatcher/bootblock.c index 468c938..7411980 100644 --- a/src/mainboard/amd/thatcher/bootblock.c +++ b/src/mainboard/amd/thatcher/bootblock.c @@ -10,8 +10,7 @@ void bootblock_mainboard_early_init(void) { - post_code(0x30); - post_code(0x31); + post_code(POST_BOOTBLOCK_SOC_EARLYINIT); gpio_100_write8(0x1, 0x98); diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index d4b11fc..6883e13 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -10,7 +10,7 @@ { u8 byte; - post_code(0x30); + post_code(POST_ENTRY_ROMSTAGE); /* turn on secondary smbus at b20 */ pm_write8(0x28, pm_read8(0x28) | 1); diff --git a/src/mainboard/bap/ode_e21XX/romstage.c b/src/mainboard/bap/ode_e21XX/romstage.c index 6b116fd..1b4cf23 100644 --- a/src/mainboard/bap/ode_e21XX/romstage.c +++ b/src/mainboard/bap/ode_e21XX/romstage.c @@ -28,10 +28,10 @@ pm_io_write8(0xd2, 0); if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); + post_code(POST_ENTRY_ROMSTAGE); fintek_enable_serial(SERIAL_DEV1, CONFIG_TTYS0_BASE); - post_code(0x31); console_init(); + post_code(POST_CONSOLE_READY); } } diff --git a/src/mainboard/msi/ms7721/romstage.c b/src/mainboard/msi/ms7721/romstage.c index 8a1cc03..67eae9f 100644 --- a/src/mainboard/msi/ms7721/romstage.c +++ b/src/mainboard/msi/ms7721/romstage.c @@ -4,5 +4,5 @@ void board_BeforeAgesa(struct sysinfo *cb) { - post_code(0x30); + post_code(POST_ENTRY_ROMSTAGE); } diff --git a/src/northbridge/intel/pineview/romstage.c b/src/northbridge/intel/pineview/romstage.c index 22ed952..7cade85 100644 --- a/src/northbridge/intel/pineview/romstage.c +++ b/src/northbridge/intel/pineview/romstage.c @@ -37,7 +37,7 @@ i82801gx_early_init(); pineview_early_init(); - post_code(0x30); + post_code(POST_ENTRY_ROMSTAGE); s3resume = southbridge_detect_s3_resume(); @@ -58,7 +58,7 @@ timestamp_add_now(TS_AFTER_INITRAM); printk(BIOS_DEBUG, "Memory initialized\n"); - post_code(0x31); + post_code(POST_MEM_PREINIT_EXIT); mb_pirq_setup(); diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 72c284f..134bce4 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -391,7 +391,7 @@ void perform_raminit(int s3resume) { - post_code(0x3a); + post_code(POST_RAM_INIT); timestamp_add_now(TS_BEFORE_INITRAM); diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index 1ec54b3..41a92c8 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -335,7 +335,7 @@ devicetree_fill_pei_data(&pei_data); mainboard_fill_pei_data(&pei_data); - post_code(0x3a); + post_code(POST_ROM_PEI_DATA_FILL); /* Fill after mainboard_fill_pei_data as it might provide spd_data */ pei_data.dimm_channel0_disabled = @@ -364,6 +364,7 @@ pei_data.boot_mode = s3resume ? 2 : 0; timestamp_add_now(TS_BEFORE_INITRAM); sdram_initialize(&pei_data); + post_code(POST_ROM_SDRAM_INIT); /* Sanity check mrc_var location by verifying a known field */ mrc_var = (void *)DCACHE_RAM_MRC_VAR_BASE; diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index b9841b5..0dd7204 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -34,6 +34,7 @@ { int s3resume = 0; + post_code(POST_ENTRY_ROMSTAGE); if (MCHBAR16(SSKPD_HI) == 0xCAFE) system_reset(); @@ -55,11 +56,11 @@ elog_boot_notify(s3resume); - post_code(0x38); + post_code(POST_ROM_SOC_EARLY_INIT); mainboard_early_init(s3resume); - post_code(0x39); + post_code(POST_RAM_INIT); perform_raminit(s3resume); @@ -74,9 +75,9 @@ southbridge_rcba_config(); mainboard_late_rcba_config(); - post_code(0x3d); + post_code(POST_ROM_RCBA_CONFIG); northbridge_romstage_finalize(s3resume); - post_code(0x3f); + post_code(POST_ROM_STAGE_HANDOFF); } diff --git a/src/soc/amd/picasso/bootblock/pre_c.S b/src/soc/amd/picasso/bootblock/pre_c.S index 5c186f1..7d21cfe 100644 --- a/src/soc/amd/picasso/bootblock/pre_c.S +++ b/src/soc/amd/picasso/bootblock/pre_c.S @@ -10,7 +10,7 @@ .global bootblock_pre_c_entry bootblock_pre_c_entry: - post_code(0xa0) + post_code(POST_ENTRY_BOOTBLOCK_STACK) movl $_eearlyram_stack, %esp @@ -23,7 +23,7 @@ movd %mm1, %eax pushl %eax /* tsc[31:0] */ - post_code(0xa2) + post_code(POST_ENTRY_C_BOOTBLOCK) call bootblock_c_entry /* Never reached */ diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index 83243d3..bfe395a 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -75,10 +75,10 @@ { int s3_resume; - post_code(0x40); + post_code(POST_ENTRY_ROMSTAGE); console_init(); - post_code(0x41); + post_code(POST_CONSOLE_READY); s3_resume = acpi_s3_resume_allowed() && acpi_is_wakeup_s3(); mainboard_romstage_entry_s3(s3_resume); elog_boot_notify(s3_resume); @@ -87,14 +87,14 @@ u32 val = cpuid_eax(1); printk(BIOS_DEBUG, "Family_Model: %08x\n", val); - post_code(0x43); + post_code(POST_FSP_MEMORY_INIT); fsp_memory_init(s3_resume); soc_update_mrc_cache(); memmap_stash_early_dram_usage(); - post_code(0x44); + post_code(POST_ENTRY_RAMSTAGE); run_ramstage(); - post_code(0x50); /* Should never see this post code. */ + post_code(POST_RAMSTAGE_DIE); /* Should never see this post code. */ } diff --git a/src/soc/amd/stoneyridge/bootblock/bootblock.c b/src/soc/amd/stoneyridge/bootblock/bootblock.c index 4025f80..ba2fe08 100644 --- a/src/soc/amd/stoneyridge/bootblock/bootblock.c +++ b/src/soc/amd/stoneyridge/bootblock/bootblock.c @@ -85,7 +85,7 @@ */ sb_reset_i2c_slaves(); bootblock_fch_early_init(); - post_code(0x90); + post_code(POST_BOOTBLOCK_SOC_EARLYINIT); } void bootblock_soc_init(void) diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c index 909b847..b49b3af 100644 --- a/src/soc/amd/stoneyridge/chip.c +++ b/src/soc/amd/stoneyridge/chip.c @@ -145,11 +145,11 @@ if (CONFIG(SOC_AMD_PSP_SELECTABLE_SMU_FW)) psp_load_named_blob(BLOB_SMU_FW2, "smu_fw2"); - post_code(0x47); + post_code(POST_AGESA_INIT_ENV); do_agesawrapper(AMD_INIT_ENV, "amdinitenv"); } else { /* Complete the initial system restoration */ - post_code(0x46); + post_code(POST_AGESA_S3_RESTORE); do_agesawrapper(AMD_S3LATE_RESTORE, "amds3laterestore"); } } diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index 96103ef..c3baf46 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -33,10 +33,10 @@ static void agesa_call(void) { - post_code(0x37); + post_code(POST_ROM_SOC_INIT_RESET); do_agesawrapper(AMD_INIT_RESET, "amdinitreset"); - post_code(0x38); + post_code(POST_ROM_SOC_EARLY_INIT); /* APs will not exit amdinitearly */ do_agesawrapper(AMD_INIT_EARLY, "amdinitearly"); } @@ -58,6 +58,7 @@ int i; console_init(); + post_code(POST_CONSOLE_READY); soc_enable_psp_early(); if (CONFIG(SOC_AMD_PSP_SELECTABLE_SMU_FW)) @@ -111,8 +112,9 @@ post_code(0x42); psp_notify_dram(); - post_code(0x43); + post_code(POST_PSP_DRAM_NOTIFY); if (cbmem_recovery(s3_resume)) + post_code(POST_CBMEM_RECOVER_FAIL); printk(BIOS_CRIT, "Failed to recover cbmem\n"); if (romstage_handoff_init(s3_resume)) printk(BIOS_ERR, "Failed to set romstage handoff data\n"); @@ -120,8 +122,9 @@ if (CONFIG(SMM_TSEG)) smm_list_regions(); - post_code(0x44); + post_code(POST_ENTRY_POST_CAR); if (postcar_frame_init(&pcf, 0)) + post_code(POST_EXIT_CAR_INIT_FAIL); die("Unable to initialize postcar frame.\n"); /* @@ -139,10 +142,10 @@ /* Cache the TSEG region */ postcar_enable_tseg_cache(&pcf); - post_code(0x45); + post_code(POST_ENTRY_POST_CAR); run_postcar_phase(&pcf); - post_code(0x50); /* Should never see this post code. */ + post_code(POST_RAMSTAGE_DIE); /* Should never see this post code. */ } void SetMemParams(AMD_POST_PARAMS *PostParams) diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index 2137e49..6e57266 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -21,6 +21,7 @@ #include <soc/pci_devs.h> #include <soc/pm.h> #include <spi-generic.h> +#include <console/console.h> static const struct pad_config tpm_spi_configs[] = { #if CONFIG(SOC_INTEL_GLK) @@ -108,4 +109,5 @@ paging_set_default_pat(); paging_enable_for_car("pdpt", "pt"); } + post_code(POST_BOOTBLOCK_SOC_EARLYINIT); } diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c index 1d1bd30..a2c005c 100644 --- a/src/soc/intel/baytrail/romstage/raminit.c +++ b/src/soc/intel/baytrail/romstage/raminit.c @@ -167,6 +167,7 @@ cbmem_initialize_empty(); } else if (cbmem_initialize()) { #if CONFIG(HAVE_ACPI_RESUME) + post_code(POST_CBMEM_RECOVER_FAIL); printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n"); /* Failed S3 resume, reset to come up cleanly */ system_reset(); diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/soc/intel/broadwell/romstage/raminit.c index 8c194fc..c6e2549 100644 --- a/src/soc/intel/broadwell/romstage/raminit.c +++ b/src/soc/intel/broadwell/romstage/raminit.c @@ -92,6 +92,7 @@ cbmem_initialize_empty(); } else if (cbmem_initialize()) { #if CONFIG(HAVE_ACPI_RESUME) + post_code(POST_CBMEM_RECOVER_FAIL); printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n"); /* Failed S3 resume, reset to come up cleanly */ system_reset(); diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index 3b7aa40..2d4a033 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -34,7 +34,7 @@ { struct romstage_params rp = { 0 }; - post_code(0x30); + post_code(POST_ENTRY_ROMSTAGE); /* System Agent Early Initialization */ systemagent_early_init(); @@ -59,7 +59,7 @@ /* Fill in mainboard pei_date. */ mainboard_pre_raminit(&rp); - post_code(0x32); + post_code(POST_MEM_PREINIT_EXIT); timestamp_add_now(TS_BEFORE_INITRAM); diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index 69ed174..ae2a306 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -12,13 +12,11 @@ .global bootblock_pre_c_entry bootblock_pre_c_entry: - post_code(0x20) - movl $no_reset, %esp /* return address */ jmp check_mtrr /* Check if CPU properly reset */ no_reset: - post_code(0x21) + post_code(POST_BOOTBLOCK_PRE_C_EXIT) /* Clear/disable fixed MTRRs */ mov $fixed_mtrr_list_size, %ebx @@ -31,7 +29,7 @@ wrmsr jnz clear_fixed_mtrr - post_code(0x22) + post_code(POST_CAR_FIXED_MTRR) /* Figure put how many MTRRs we have, and clear them out */ mov $MTRR_CAP_MSR, %ecx @@ -49,7 +47,7 @@ dec %ebx jnz clear_var_mtrr - post_code(0x23) + post_code(POST_CAR_VARIABLE_MTRR) /* Configure default memory type to uncacheable (UC) */ mov $MTRR_DEF_TYPE_MSR, %ecx @@ -76,7 +74,7 @@ bts %eax, %esi dec %esi /* esi <- MTRR_PHYS_MASK_HIGH */ - post_code(0x24) + post_code(POST_CAR_MTRR_ENABLE) #if ((CONFIG_DCACHE_RAM_SIZE & (CONFIG_DCACHE_RAM_SIZE - 1)) == 0) /* Configure CAR region as write-back (WB) */ @@ -153,7 +151,7 @@ .global car_init_done car_init_done: - post_code(0x29) + post_code(POST_ENTRY_BOOTBLOCK_STACK) /* Setup bootblock stack */ mov $_ecar_stack, %esp @@ -170,7 +168,7 @@ pushl %eax /* tsc[31:0] */ before_carstage: - post_code(0x2A) + post_code(POST_ENTRY_C_BOOTBLOCK) call bootblock_c_entry /* Never reached */ @@ -203,7 +201,7 @@ or $0x1, %eax wrmsr - post_code(0x26) + post_code(POST_CAR_CACHE_CLEAR) /* Clear the cache memory region. This will also fill up the cache */ movl $CONFIG_DCACHE_RAM_BASE, %edi @@ -213,7 +211,7 @@ cld rep stosl - post_code(0x27) + post_code(POST_CAR_CACHE_EVICTION) /* Disable cache eviction (run stage) */ mov $MSR_EVICT_CTL, %ecx @@ -221,8 +219,7 @@ or $0x2, %eax wrmsr - post_code(0x28) - + post_code(POST_CAR_INIT_CACHE) jmp car_init_done #elif CONFIG(INTEL_CAR_CQOS) @@ -300,7 +297,7 @@ and %ebx, %eax wrmsr - post_code(0x26) + post_code(POST_CAR_CACHE_CLEAR) /* Clear the cache memory region. This will also fill up the cache */ movl $CONFIG_DCACHE_RAM_BASE, %edi @@ -325,19 +322,19 @@ and $~(PREFETCH_L1_DISABLE | PREFETCH_L2_DISABLE), %eax wrmsr - post_code(0x28) + post_code(POST_CAR_INIT_CACHE) jmp car_init_done #elif CONFIG(INTEL_CAR_NEM_ENHANCED) .global car_nem_enhanced car_nem_enhanced: + post_code(POST_CAR_CACHE_EVICTION) /* Disable cache eviction (setup stage) */ mov $MSR_EVICT_CTL, %ecx rdmsr or $0x1, %eax wrmsr - post_code(0x26) /* Create n-way set associativity of cache */ xorl %edi, %edi @@ -427,7 +424,7 @@ xorl %edx, %edx wrmsr - post_code(0x27) + post_code(POST_CAR_CACHE_EVICTION) /* * Enable No-Eviction Mode Run State by setting * NO_EVICT_MODE MSR 2E0h bit [1] = '1'. @@ -438,7 +435,6 @@ orl $0x02, %eax wrmsr - post_code(0x28) - + post_code(POST_CAR_INIT_CACHE) jmp car_init_done #endif diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S index b9daf08..1eb0751 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S @@ -17,7 +17,7 @@ .global cache_as_ram cache_as_ram: - post_code(0x21) + post_code(POST_BOOTBLOCK_PRE_C_EXIT) /* find fsp in cbfs */ lea fsp_name, %esi @@ -70,6 +70,7 @@ cmp $0, %eax jnz .halt_forever + post_code(POST_ENTRY_BOOTBLOCK_STACK) /* Setup bootblock stack */ mov %edx, %esp @@ -87,6 +88,7 @@ movd %mm1, %eax push %eax + post_code(POST_ENTRY_C_BOOTBLOCK) /* We can call into C functions now */ call bootblock_c_entry diff --git a/src/soc/intel/quark/bootblock/esram_init.S b/src/soc/intel/quark/bootblock/esram_init.S index fc1c7c9..10484545 100644 --- a/src/soc/intel/quark/bootblock/esram_init.S +++ b/src/soc/intel/quark/bootblock/esram_init.S @@ -473,11 +473,12 @@ * edi: High 32-bits of timestamp */ + post_code(POST_ENTRY_BOOTBLOCK_STACK) /* Setup bootblock stack */ movl $_ecar_stack, %esp before_carstage: - post_code(0x2b) + post_code(POST_ENTRY_C_BOOTBLOCK) /* Get the timestamp passed in bootblock_crt0.S */ push %edi diff --git a/src/soc/intel/quark/romstage/fsp_params.c b/src/soc/intel/quark/romstage/fsp_params.c index efe3c10..081eb14 100644 --- a/src/soc/intel/quark/romstage/fsp_params.c +++ b/src/soc/intel/quark/romstage/fsp_params.c @@ -17,8 +17,8 @@ { bool s3wake; - post_code(0x20); console_init(); + post_code(POST_CONSOLE_READY); if (CONFIG(STORAGE_TEST)) { uint32_t bar; diff --git a/src/soc/intel/skylake/bootblock/bootblock.c b/src/soc/intel/skylake/bootblock/bootblock.c index 6380db2..bdc2d2e 100644 --- a/src/soc/intel/skylake/bootblock/bootblock.c +++ b/src/soc/intel/skylake/bootblock/bootblock.c @@ -21,6 +21,7 @@ if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE)) uart_bootblock_init(); + post_code(POST_BOOTBLOCK_SOC_EARLYINIT); } void bootblock_soc_init(void) diff --git a/src/soc/intel/tigerlake/bootblock/bootblock.c b/src/soc/intel/tigerlake/bootblock/bootblock.c index 54ad85a..e0ecc03 100644 --- a/src/soc/intel/tigerlake/bootblock/bootblock.c +++ b/src/soc/intel/tigerlake/bootblock/bootblock.c @@ -4,6 +4,7 @@ #include <intelblocks/systemagent.h> #include <intelblocks/uart.h> #include <soc/bootblock.h> +#include <console/console.h> asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { @@ -19,6 +20,7 @@ pch_early_iorange_init(); if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE)) uart_bootblock_init(); + post_code(POST_BOOTBLOCK_SOC_EARLYINIT); } void bootblock_soc_init(void) diff --git a/src/soc/intel/xeon_sp/bootblock.c b/src/soc/intel/xeon_sp/bootblock.c index f6653e2..bcb516d 100644 --- a/src/soc/intel/xeon_sp/bootblock.c +++ b/src/soc/intel/xeon_sp/bootblock.c @@ -48,6 +48,7 @@ uint8_t p2sb_cmd = pci_mmio_read_config8(PCH_DEV_P2SB, PCI_COMMAND); pci_mmio_write_config8(PCH_DEV_P2SB, PCI_COMMAND, p2sb_cmd | PCI_COMMAND_MEMORY); pci_mmio_write_config32(PCH_DEV_P2SB, PCI_BASE_ADDRESS_0, CONFIG_PCR_BASE_ADDRESS); + post_code(POST_BOOTBLOCK_SOC_EARLYINIT); } void bootblock_soc_init(void) diff --git a/src/soc/intel/xeon_sp/romstage.c b/src/soc/intel/xeon_sp/romstage.c index 3db9ca9..c675213 100644 --- a/src/soc/intel/xeon_sp/romstage.c +++ b/src/soc/intel/xeon_sp/romstage.c @@ -25,6 +25,7 @@ unlock_pam_regions(); if (postcar_frame_init(&pcf, 1 * KiB)) + post_code(POST_EXIT_CAR_INIT_FAIL); die("Unable to initialize postcar frame.\n"); /* @@ -40,6 +41,7 @@ /* Cache the memory-mapped boot media. */ postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); + post_code(POST_ENTRY_POST_CAR); run_postcar_phase(&pcf); } -- To view, visit https://review.coreboot.org/c/coreboot/+/42503 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If32f43104a829bd1db0d5f5340cc94bf0c717c39 Gerrit-Change-Number: 42503 Gerrit-PatchSet: 1 Gerrit-Owner: Sindhoor Tilak <sindhoor(a)sin9yt.net> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

9 27

Change in coreboot[master]: configs/builder/config.ocp.sonorapass: Config for SonoraPass PO. src/...
by Ryback Hung (Code Review) 10 Jun '23

10 Jun '23

Ryback Hung has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40334 ) Change subject: configs/builder/config.ocp.sonorapass: Config for SonoraPass PO. src/mainboard/ocp/sonorapass/*.*: Preliminiary platform porting for SonoraPass PO. ...................................................................... configs/builder/config.ocp.sonorapass: Config for SonoraPass PO. src/mainboard/ocp/sonorapass/*.*: Preliminiary platform porting for SonoraPass PO. It can boot SonoraPass EVT board w/ ES1 CPX-SP and ES PCH. Due to IRQs issue, it has yet to boot into Linuxboot/u-root payload. Change-Id: I60452205d666fd19582780401ccd9d7773e68a5b --- A configs/builder/config.ocp.sonorapass A src/mainboard/ocp/sonorapass/Kconfig A src/mainboard/ocp/sonorapass/Kconfig.name A src/mainboard/ocp/sonorapass/Makefile.inc A src/mainboard/ocp/sonorapass/acpi/platform.asl A src/mainboard/ocp/sonorapass/board.fmd A src/mainboard/ocp/sonorapass/board_info.txt A src/mainboard/ocp/sonorapass/bootblock.c A src/mainboard/ocp/sonorapass/devicetree.cb A src/mainboard/ocp/sonorapass/dsdt.asl 10 files changed, 320 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/40334/1 diff --git a/configs/builder/config.ocp.sonorapass b/configs/builder/config.ocp.sonorapass new file mode 100644 index 0000000..c05dce2 --- /dev/null +++ b/configs/builder/config.ocp.sonorapass @@ -0,0 +1,21 @@ +# type this to get working .config: +# make defconfig KBUILD_DEFCONFIG=configs/builder/config.ocp.sonorapass + +CONFIG_VENDOR_OCP=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="site-local/cedarisland_crb/ucode-05-06-5a" +CONFIG_ADD_FSP_BINARIES=y +CONFIG_FSP_T_FILE="site-local/cedarisland_crb/Server_T.fd" +CONFIG_FSP_M_FILE="site-local/cedarisland_crb/Server_M.fd" +CONFIG_FSP_S_FILE="site-local/cedarisland_crb/Server_S.fd" +CONFIG_ME_BIN_PATH="site-local/sonorapass/me.bin" +CONFIG_IFD_BIN_PATH="site-local/sonorapass/descriptor.bin" +CONFIG_CONSOLE_SERIAL_57600=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y +CONFIG_PAYLOAD_LINUX=y +CONFIG_PAYLOAD_FILE="site-local/linuxboot_uroot_ttys0" +CONFIG_LINUX_COMMAND_LINE="earlyprintk=uart8250,io,0x3f8,57600n1 console=uart8250,io,0x3f8,57600n1 loglevel=7" diff --git a/src/mainboard/ocp/sonorapass/Kconfig b/src/mainboard/ocp/sonorapass/Kconfig new file mode 100644 index 0000000..34adf5f --- /dev/null +++ b/src/mainboard/ocp/sonorapass/Kconfig @@ -0,0 +1,43 @@ +## +## This file is part of the coreboot project. +## +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +if BOARD_OCP_SONORAPASS + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_65536 + select MAINBOARD_USES_FSP2_0 + select IPMI_KCS + select SOC_INTEL_COOPERLAKE_SP + select SUPERIO_ASPEED_AST2400 + select HAVE_ACPI_TABLES + +config MAINBOARD_DIR + string + default "ocp/sonorapass" + +config MAINBOARD_PART_NUMBER + string + default "SonoraPass" + +config MAINBOARD_FAMILY + string + default "SonoraPass" + +config FMDFILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd" + +endif diff --git a/src/mainboard/ocp/sonorapass/Kconfig.name b/src/mainboard/ocp/sonorapass/Kconfig.name new file mode 100644 index 0000000..90e7f3d --- /dev/null +++ b/src/mainboard/ocp/sonorapass/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_OCP_SONORAPASS + bool "SonoraPass" diff --git a/src/mainboard/ocp/sonorapass/Makefile.inc b/src/mainboard/ocp/sonorapass/Makefile.inc new file mode 100644 index 0000000..8501868 --- /dev/null +++ b/src/mainboard/ocp/sonorapass/Makefile.inc @@ -0,0 +1 @@ +bootblock-y += bootblock.c diff --git a/src/mainboard/ocp/sonorapass/acpi/platform.asl b/src/mainboard/ocp/sonorapass/acpi/platform.asl new file mode 100644 index 0000000..75c1b92 --- /dev/null +++ b/src/mainboard/ocp/sonorapass/acpi/platform.asl @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +/* The APM port can be used for generating software SMIs */ + +OperationRegion (APMP, SystemIO, 0xb2, 2) +Field (APMP, ByteAcc, NoLock, Preserve) +{ + APMC, 8, // APM command + APMS, 8 // APM status +} + +/* Port 80 POST */ + +OperationRegion (POST, SystemIO, 0x80, 1) +Field (POST, ByteAcc, Lock, Preserve) +{ + DBG0, 8 +} + +Name(\APC1, Zero) // IIO IOAPIC + +Name(\PICM, Zero) // IOAPIC/8259 + +Method(_PIC, 1) +{ + Store(Arg0, PICM) +} + +/* + * The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + Return(Package(){0,0}) +} diff --git a/src/mainboard/ocp/sonorapass/board.fmd b/src/mainboard/ocp/sonorapass/board.fmd new file mode 100644 index 0000000..e28bcf0 --- /dev/null +++ b/src/mainboard/ocp/sonorapass/board.fmd @@ -0,0 +1,10 @@ +FLASH@0xfc000000 64M { + SI_ALL@0x0 0x2fd8000 { + SI_DESC@0x0 0x1000 + SI_GBE@0x1000 0x2000 + SI_ME@0x3000 0x2fc5000 + } + FMAP@0x03000000 0x800 + RW_MRC_CACHE@0x3000800 0x10000 + COREBOOT(CBFS)@0x3010800 +} diff --git a/src/mainboard/ocp/sonorapass/board_info.txt b/src/mainboard/ocp/sonorapass/board_info.txt new file mode 100644 index 0000000..bbf3ee9 --- /dev/null +++ b/src/mainboard/ocp/sonorapass/board_info.txt @@ -0,0 +1,5 @@ +Board name: SonoraPass +Category: server +ROM protocol: SPI +ROM socketed: y +Flashrom support: y diff --git a/src/mainboard/ocp/sonorapass/bootblock.c b/src/mainboard/ocp/sonorapass/bootblock.c new file mode 100644 index 0000000..06f45c9 --- /dev/null +++ b/src/mainboard/ocp/sonorapass/bootblock.c @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <bootblock_common.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <device/pnp_ops.h> +#include <intelblocks/lpc_lib.h> +#include <intelblocks/pcr.h> +#include <soc/pci_devs.h> +#include <soc/pcr_ids.h> +#include <superio/aspeed/ast2400/ast2400.h> +#include <superio/aspeed/common/aspeed.h> + +/* these are defined in intelblocks/lpc_lib.h but we can't use them yet */ +#define PCR_DMI_LPCIOD 0x2770 +#define PCR_DMI_LPCIOE 0x2774 +#define ASPEED_CONFIG_INDEX 0x2E +#define ASPEED_CONFIG_DATA 0x2F + +void bootblock_mainboard_early_init(void) +{ + struct config_data port80[] = { + /* {Type, base, reg, and, or} */ + /* Set command source of GPIOH to LPC */ + {MEM, ASPEED_GPIO_BASE, 0x68, 0xFEFFFFFF, 0x01000000}, + {MEM, ASPEED_GPIO_BASE, 0x6C, 0xFEFFFFFF, 0x00000000}, + /* Unlock SCU Registers */ + {MEM, ASPEED_SCU_BASE, 0x00, 0x00000000, 0x1688A8A8}, + /* Program GPIOH multi-function to GPIO */ + {MEM, ASPEED_SCU_BASE, 0x90, 0xFFFFFF3F, 0x00000000}, + /* Program GPIOH as output */ + {MEM, ASPEED_GPIO_BASE, 0x24, 0x00FFFFFF, 0xFF000000}, + /* Set snooping address#0 as 80h */ + {MEM, ASPEED_LPC_BASE, 0x90, 0xFFFF0000, 0x00000080}, + /* Enable snooping address#0 */ + {MEM, ASPEED_LPC_BASE, 0x80, 0xFFFFFFFE, 0x00000001}, + /* Enable GPIO device */ + {SIO, 0, ASPEED_CONFIG_INDEX, 0x00, ASPEED_ENTRY_KEY}, + {SIO, 0, ASPEED_CONFIG_INDEX, 0x00, ASPEED_ENTRY_KEY}, + {SIO, 0, ASPEED_CONFIG_INDEX, 0x00, LDN_SEL}, + {SIO, 0, ASPEED_CONFIG_DATA, 0x00, AST2400_GPIO}, + {SIO, 0, ASPEED_CONFIG_INDEX, 0x00, ACT_REG}, + {SIO, 0, ASPEED_CONFIG_DATA, 0x00, PORT80_GPIO_EN | ACTIVATE_VALUE}, + /* Select GPIOH for port80 GPIO */ + {SIO, 0, ASPEED_CONFIG_INDEX, 0x00, PORT80_GPIO_SEL}, + {SIO, 0, ASPEED_CONFIG_DATA, 0x00, GPIOH_SEL}, + /* Disable GPIO Device */ + {SIO, 0, ASPEED_CONFIG_INDEX, 0x00, LDN_SEL}, + {SIO, 0, ASPEED_CONFIG_DATA, 0x00, AST2400_GPIO}, + {SIO, 0, ASPEED_CONFIG_INDEX, 0x00, ACT_REG}, + {SIO, 0, ASPEED_CONFIG_DATA, 0xFE, DEACTIVATE_VALUE}, + {SIO, 0, ASPEED_CONFIG_INDEX, 0x00, ASPEED_EXIT_KEY} + }; + struct config_data uart[] = { + /* {Type, base, reg, and, or} */ + /* Unlock SCU Registers */ + {MEM, ASPEED_SCU_BASE, 0x00, 0x00000000, 0x1688A8A8}, + /* SERIAL PORT1 */ + {MEM, ASPEED_SCU_BASE, 0x84, 0xFF00FFFF, 0x00C00000}, + {MEM, ASPEED_GPIO_BASE, 0x90, 0xFFFFFFCF, 0x00000000}, + /* SERIAL PORT2 */ + {MEM, ASPEED_SCU_BASE, 0x84, 0x00FFFFFF, 0xC0000000}, + {MEM, ASPEED_GPIO_BASE, 0x90, 0xFFFFFFCF, 0x00000000}, + }; + + /* Enable COM1 only */ + pcr_write32(PID_DMI, 0x2770, 0); + pcr_write32(PID_DMI, 0x2774, 1); + + /* Decode for SuperIO (0x2e) and COM1 (0x3f8) */ + pci_mmio_write_config32(PCH_DEV_LPC, 0x80, (1 << 28) | (1 << 16)); + + const pnp_devfn_t serial_dev = PNP_DEV(0x2e, AST2400_SUART1); + aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE); + + /* Port 80h direct to GPIO for LED display */ + aspeed_early_config(ASPEED_CONFIG_INDEX, port80, ARRAY_SIZE(port80)); + + /* Init UART */ + aspeed_early_config(ASPEED_CONFIG_INDEX, uart, ARRAY_SIZE(uart)); +} diff --git a/src/mainboard/ocp/sonorapass/devicetree.cb b/src/mainboard/ocp/sonorapass/devicetree.cb new file mode 100644 index 0000000..fff834a --- /dev/null +++ b/src/mainboard/ocp/sonorapass/devicetree.cb @@ -0,0 +1,53 @@ +chip soc/intel/xeon_sp/cpx + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host bridge + device pci 04.0 on end + device pci 04.1 on end + device pci 04.2 on end + device pci 04.3 on end + device pci 04.4 on end + device pci 04.5 on end + device pci 04.6 on end + device pci 04.7 on end + device pci 05.0 on end + device pci 05.2 on end + device pci 05.4 on end + device pci 08.0 on end + device pci 08.1 on end + device pci 08.2 on end + device pci 11.0 on end + device pci 11.1 on end + device pci 11.5 on end + device pci 14.0 on end + device pci 16.0 on end + device pci 16.1 on end + device pci 16.4 on end + device pci 17.0 on end + device pci 1c.0 on end + device pci 1c.4 on end + device pci 1f.2 on end + device pci 1f.4 on end + device pci 1f.5 on end + + device pci 1f.0 on # LPC/eSPI Interface + chip superio/common + device pnp 2e.0 on + chip superio/aspeed/ast2400 + device pnp 2e.2 on # SUART1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # SUART2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + end + end + end + end + + end +end diff --git a/src/mainboard/ocp/sonorapass/dsdt.asl b/src/mainboard/ocp/sonorapass/dsdt.asl new file mode 100644 index 0000000..3dc45d5 --- /dev/null +++ b/src/mainboard/ocp/sonorapass/dsdt.asl @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <arch/acpi.h> +#include <soc/iomap.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + #include "acpi/platform.asl" + + Name(_S0, Package() { 0x00, 0x00, 0x00, 0x00 }) + Name(_S5, Package() { 0x07, 0x00, 0x00, 0x00 }) + + Scope (\_SB) + { + Device (PCI0) + { + #include <soc/intel/xeon_sp/cpx/acpi/southcluster.asl> + #include <soc/intel/common/block/acpi/acpi/lpc.asl> + + } + + + Device (UNC0) + { + Name (_HID, EisaId ("PNP0A03")) + Name (_UID, 0x3F) + Method (_BBN, 0, NotSerialized) + { + Return (0xff) + } + + Method (_STA, 0, NotSerialized) + { + Return (0xf) + } + + Name (_CRS, ResourceTemplate () + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + 0x00FF, // Range Minimum + 0x00FF, // Range Maximum + 0x0000, // Translation Offset + 0x0001, // Length + ,, ) + }) + + } + } + +} -- To view, visit https://review.coreboot.org/c/coreboot/+/40334 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60452205d666fd19582780401ccd9d7773e68a5b Gerrit-Change-Number: 40334 Gerrit-PatchSet: 1 Gerrit-Owner: Ryback Hung <ryback.hung%quantatw.com(a)gtempaccount.com> Gerrit-MessageType: newchange

8 22

Change in coreboot[master]: soc/intel/tigerlake: move mainboard_silicon_init_params
by Shaunak Saha (Code Review) 10 Jun '23

10 Jun '23

Shaunak Saha has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44262 ) Change subject: soc/intel/tigerlake: move mainboard_silicon_init_params ...................................................................... soc/intel/tigerlake: move mainboard_silicon_init_params This patch arranges mainboard_silicon_init_params before fetching any config variables from devicetree. This would allow the variant specific devicetree overrides to get consumed so that FSP UPD parameters are initialized properly before SiliconInit. BUG=b:158573805 TEST=Test that UPD values are set properly with variant specific overrides of config's . Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> Change-Id: Idfce528efa7806e292071e092fb129b53a94a145 --- M src/soc/intel/tigerlake/fsp_params.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/44262/1 diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index a61a025..5178d91 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -107,6 +107,8 @@ if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI)) params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data(); + mainboard_silicon_init_params(params); + /* D3Hot and D3Cold for TCSS */ params->D3HotEnable = !config->TcssD3HotDisable; cpu_id = cpu_get_cpuid(); @@ -311,7 +313,6 @@ /* EnableMultiPhaseSiliconInit for running MultiPhaseSiInit */ params->EnableMultiPhaseSiliconInit = 1; - mainboard_silicon_init_params(params); } /* -- To view, visit https://review.coreboot.org/c/coreboot/+/44262 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idfce528efa7806e292071e092fb129b53a94a145 Gerrit-Change-Number: 44262 Gerrit-PatchSet: 1 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: mb/emulation/qemu-armv7/memlayout: Move regions
by Patrick Rudolph (Code Review) 10 Jun '23

10 Jun '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44395 ) Change subject: mb/emulation/qemu-armv7/memlayout: Move regions ...................................................................... mb/emulation/qemu-armv7/memlayout: Move regions Move pre RAM regions into SRAM. Tested using uImage/FIT, still boots into GNU/Linux 5.5.7. Change-Id: I32b3664f018eded576262cf7b52a94dcd6d4f346 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/mainboard/emulation/qemu-armv7/memlayout.ld 1 file changed, 9 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/44395/1 diff --git a/src/mainboard/emulation/qemu-armv7/memlayout.ld b/src/mainboard/emulation/qemu-armv7/memlayout.ld index b0408ed..c1e99eb 100644 --- a/src/mainboard/emulation/qemu-armv7/memlayout.ld +++ b/src/mainboard/emulation/qemu-armv7/memlayout.ld @@ -28,19 +28,19 @@ REGION(nor_flash1, 0x40000000, 0x4000000, 4K) REGION(nor_flash2, 0x44000000, 0x4000000, 4K) SRAM_START(0x48000000) + STACK(0x48000000, 64K) + FMAP_CACHE(0x48010000, 4K) + TIMESTAMP(0x48011000, 1K) + TTB_SUBTABLES(0x48012000, 4K) + TTB(0x48014000, 32K) + BOOTBLOCK(0x48020000, 128K) + ROMSTAGE(0x48040000, 128K) SRAM_END(0x4C000000) REGION(videoram, 0x4c000000, 0x1000000, 4K) REGION(ethernet, 0x4e000000, 0x1000000, 4K) REGION(usb, 0x4f000000, 0x1000000, 4K) DRAM_START(0x60000000) - STACK(0x60000000, 64K) - BOOTBLOCK(0x60010000, 128K) - FMAP_CACHE(0x60030000, 4K) - TIMESTAMP(0x60031000, 1K) - TTB_SUBTABLES(0x60032000, 4K) - TTB(0x60034000, 32K) - ROMSTAGE(0x60040000, 128K) - RAMSTAGE(0x60060000, 16M) - POSTRAM_CBFS_CACHE(0x61060000, 8M) + RAMSTAGE(0x60000000, 16M) + POSTRAM_CBFS_CACHE(0x61000000, 8M) } -- To view, visit https://review.coreboot.org/c/coreboot/+/44395 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32b3664f018eded576262cf7b52a94dcd6d4f346 Gerrit-Change-Number: 44395 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

2 1

Change in coreboot[master]: soc/intel/tigerlake: Clean up report_cpu_info() function
by Alexey Buyanov (Code Review) 10 Jun '23

10 Jun '23

Alexey Buyanov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44050 ) Change subject: soc/intel/tigerlake: Clean up report_cpu_info() function ...................................................................... soc/intel/tigerlake: Clean up report_cpu_info() function This patch uses the fill_processor_name function in order to fetch the CPU Name. BUG=none TEST=successfully built and booted TGLRVP Signed-off-by: Alexey Buyanov <alexey.buyanov(a)intel.com> Change-Id: I97be5d6b0a6fc5785c10ace3b78a1bc9c9f31230 --- M src/soc/intel/tigerlake/bootblock/report_platform.c 1 file changed, 4 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/44050/1 diff --git a/src/soc/intel/tigerlake/bootblock/report_platform.c b/src/soc/intel/tigerlake/bootblock/report_platform.c index 6acc0c3..d715725 100644 --- a/src/soc/intel/tigerlake/bootblock/report_platform.c +++ b/src/soc/intel/tigerlake/bootblock/report_platform.c @@ -10,6 +10,7 @@ #include <device/pci_ops.h> #include <console/console.h> #include <cpu/x86/msr.h> +#include <cpu/x86/name.h> #include <device/pci.h> #include <device/pci_ids.h> #include <intelblocks/mp_init.h> @@ -99,35 +100,14 @@ static void report_cpu_info(void) { - struct cpuid_result cpuidr; - u32 i, index, cpu_id, cpu_feature_flag; - const char cpu_not_found[] = "Platform info not available"; - const char *cpu_name = cpu_not_found; /* 48 bytes are reported */ + u32 i, cpu_id, cpu_feature_flag; + char cpu_name[49]; int vt, txt, aes; msr_t microcode_ver; static const char *const mode[] = {"NOT ", ""}; const char *cpu_type = "Unknown"; - u32 p[13]; - index = 0x80000000; - cpuidr = cpuid(index); - if (cpuidr.eax >= 0x80000004) { - int j = 0; - - for (i = 2; i <= 4; i++) { - cpuidr = cpuid(index + i); - p[j++] = cpuidr.eax; - p[j++] = cpuidr.ebx; - p[j++] = cpuidr.ecx; - p[j++] = cpuidr.edx; - } - p[12] = 0; - cpu_name = (char *)p; - - /* Skip leading spaces in CPU name string */ - while (cpu_name[0] == ' ' && strlen(cpu_name) > 0) - cpu_name++; - } + fill_processor_name(cpu_name); microcode_ver.lo = 0; microcode_ver.hi = 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/44050 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I97be5d6b0a6fc5785c10ace3b78a1bc9c9f31230 Gerrit-Change-Number: 44050 Gerrit-PatchSet: 1 Gerrit-Owner: Alexey Buyanov <alexey.buyanov(a)intel.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: mb/intel/tglrvp: Enable CSE Firmware Lite SKU
by Shreesh Chhabbi (Code Review) 10 Jun '23

10 Jun '23

Hello Jamie Ryu, Shreesh Chhabbi, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44853 to review the following change. Change subject: mb/intel/tglrvp: Enable CSE Firmware Lite SKU ...................................................................... mb/intel/tglrvp: Enable CSE Firmware Lite SKU BUG=None BRANCH=None TEST=Build and boot tglrvp with CSE Lite and Consumer SKU Change-Id: I78b2000acad24314d239d32ee60b5c6583aae363 Signed-off-by: Jamie Ryu <jamie.m.ryu(a)intel.com> --- M src/mainboard/intel/tglrvp/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/44853/1 diff --git a/src/mainboard/intel/tglrvp/Kconfig b/src/mainboard/intel/tglrvp/Kconfig index 3e55f56..2ad6e79 100644 --- a/src/mainboard/intel/tglrvp/Kconfig +++ b/src/mainboard/intel/tglrvp/Kconfig @@ -18,6 +18,7 @@ select DRIVERS_INTEL_ISH select EC_ACPI select PCIEXP_HOTPLUG + select SOC_INTEL_CSE_LITE_SKU config CHROMEOS bool -- To view, visit https://review.coreboot.org/c/coreboot/+/44853 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78b2000acad24314d239d32ee60b5c6583aae363 Gerrit-Change-Number: 44853 Gerrit-PatchSet: 1 Gerrit-Owner: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Gerrit-MessageType: newchange

2 1

Change in coreboot[master]: prodrive/hermes: Disable USB power on S5
by Patrick Rudolph (Code Review) 10 Jun '23

10 Jun '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44526 ) Change subject: prodrive/hermes: Disable USB power on S5 ...................................................................... prodrive/hermes: Disable USB power on S5 Change-Id: I9d78e8966b7ccc06b04045fda6bda36eab464051 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/prodrive/hermes/dsdt.asl 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/44526/1 diff --git a/src/mainboard/prodrive/hermes/dsdt.asl b/src/mainboard/prodrive/hermes/dsdt.asl index 4d8d170..c1bed5f 100644 --- a/src/mainboard/prodrive/hermes/dsdt.asl +++ b/src/mainboard/prodrive/hermes/dsdt.asl @@ -20,6 +20,16 @@ #include <soc/intel/common/block/acpi/acpi/northbridge.asl> #include <soc/intel/cannonlake/acpi/southbridge.asl> } + Method (MPTS,1) { + if (Arg0 == 5) { + /* Disable USB power on S5 */ + \_SB.PCI0.CTXS(GPP_G0) + \_SB.PCI0.CTXS(GPP_G1) + \_SB.PCI0.CTXS(GPP_G2) + \_SB.PCI0.CTXS(GPP_G3) + \_SB.PCI0.CTXS(GPP_G4) + } + } } #include <southbridge/intel/common/acpi/sleepstates.asl> -- To view, visit https://review.coreboot.org/c/coreboot/+/44526 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9d78e8966b7ccc06b04045fda6bda36eab464051 Gerrit-Change-Number: 44526 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mtrr.h: refine _POW2_MASK
by ky0ko (Code Review) 10 Jun '23

10 Jun '23

ky0ko has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44845 ) Change subject: mtrr.h: refine _POW2_MASK ...................................................................... mtrr.h: refine _POW2_MASK this patch adjusts _POW2_MASK to work with rom sizes between 64KiB and 512MiB, additionally fixing incorrectness for sizes 128MiB and above that previously were present. Change-Id: I0272c0c43cba44f6fbfb5dc539509b4ed9b92e75 Signed-off-by: ky0ko <ky0ko(a)disroot.org> --- M src/include/cpu/x86/mtrr.h 1 file changed, 4 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/44845/1 diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 42964b0..fd4159d 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -176,9 +176,11 @@ #endif /* !defined(__ASSEMBLER__) */ /* Align up/down to next power of 2, suitable for assembler - too. Range of result 256kB to 128MB is good enough here. */ + too. Range works from 64kB to 512MB. */ #define _POW2_MASK(x) ((x>>1)|(x>>2)|(x>>3)|(x>>4)|(x>>5)| \ - (x>>6)|(x>>7)|(x>>8)|((1<<18)-1)) + (x>>6)|(x>>7)|(x>>8)|(x>>9)|(x>>10)| \ + (x>>11)|(x>>12)|(x>>13)|((1<<16)-1)) + #define _ALIGN_UP_POW2(x) ((x + _POW2_MASK(x)) & ~_POW2_MASK(x)) #define _ALIGN_DOWN_POW2(x) ((x) & ~_POW2_MASK(x)) -- To view, visit https://review.coreboot.org/c/coreboot/+/44845 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0272c0c43cba44f6fbfb5dc539509b4ed9b92e75 Gerrit-Change-Number: 44845 Gerrit-PatchSet: 1 Gerrit-Owner: ky0ko <ky0ko(a)disroot.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP] 3rdparty/libgfxinit: Update submodule pointer
by Angel Pons (Code Review) 10 Jun '23

10 Jun '23

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44071 ) Change subject: [WIP] 3rdparty/libgfxinit: Update submodule pointer ...................................................................... [WIP] 3rdparty/libgfxinit: Update submodule pointer This brings in Bay Trail support. Change-Id: Ia4b265862e2a7cce8e3d272dee9d22aba8358fa5 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M 3rdparty/libgfxinit 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/44071/1 diff --git a/3rdparty/libgfxinit b/3rdparty/libgfxinit index 3318bf2..729fff7 160000 --- a/3rdparty/libgfxinit +++ b/3rdparty/libgfxinit @@ -1 +1 @@ -Subproject commit 3318bf26803c77d41b18bef6d7ae4e051b97f9f2 +Subproject commit 729fff7de5070bbfd2975065549b1f9fbf057976 -- To view, visit https://review.coreboot.org/c/coreboot/+/44071 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia4b265862e2a7cce8e3d272dee9d22aba8358fa5 Gerrit-Change-Number: 44071 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/volteer: Disable Precision Time Measurement for PCIe RP 9
by Shreesh Chhabbi (Code Review) 10 Jun '23

10 Jun '23

Hello Shreesh Chhabbi, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/45302 to review the following change. Change subject: mb/volteer: Disable Precision Time Measurement for PCIe RP 9 ...................................................................... mb/volteer: Disable Precision Time Measurement for PCIe RP 9 Change-Id: Id42d0485a5ff8cb2c1886c460e6ec2f1fb540516 Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/45302/1 diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 1b8b0d6..eb1f1a9 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -99,6 +99,9 @@ register "PcieClkSrcUsage[5]" = "0xFF" register "PcieClkSrcUsage[6]" = "0xFF" + # PCIe RP PTM + register "PciePtm[8]" = "0" + # Enable SATA register "SataEnable" = "1" register "SataMode" = "0" -- To view, visit https://review.coreboot.org/c/coreboot/+/45302 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id42d0485a5ff8cb2c1886c460e6ec2f1fb540516 Gerrit-Change-Number: 45302 Gerrit-PatchSet: 1 Gerrit-Owner: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Reviewer: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Gerrit-MessageType: newchange

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