coreboot-gerrit May 2021

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Change in coreboot[master]: drivers/intel/fsp2_0 - Change boot state notification Change boot sta...
by Rocky Phagura (Code Review) 16 Feb '22

16 Feb '22

Rocky Phagura has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43979 ) Change subject: drivers/intel/fsp2_0 - Change boot state notification Change boot state notification of FSP to before payload is loaded into memory. Currently the flow is as follows: 1. Load payload into memory 2. Notify FSP of boot state init 3. Jump to payload code ...................................................................... drivers/intel/fsp2_0 - Change boot state notification Change boot state notification of FSP to before payload is loaded into memory. Currently the flow is as follows: 1. Load payload into memory 2. Notify FSP of boot state init 3. Jump to payload code This patch changes the flow to: 1. Notify FSP of boot state 2. Load payload into memory 3. Jump to payload code This prevents code corruption of payload. At this stage of boot, there is no concept of memory management, therefore FSP can use any memory it needs. After making these changes, Tianocore payload is able to load properly where previously its memory was getting corrupted. TEST=build for Tiogapass platform under OCP mainboard and select Tianocore payload. Boot the system and ensure target OS loads. Change-Id: I122edc12abf992cb3e5ec53747a7cef9c94aee8e Signed-off-by: Rocky Phagura <rphagura(a)fb.com> --- M src/drivers/intel/fsp2_0/notify.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/43979/1 diff --git a/src/drivers/intel/fsp2_0/notify.c b/src/drivers/intel/fsp2_0/notify.c index 76cdf12..ba8ef9e 100644 --- a/src/drivers/intel/fsp2_0/notify.c +++ b/src/drivers/intel/fsp2_0/notify.c @@ -68,7 +68,7 @@ BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fsp_notify_dummy, (void *) AFTER_PCI_ENUM); -BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, fsp_notify_dummy, +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_ENTRY, fsp_notify_dummy, (void *) READY_TO_BOOT); BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, fsp_notify_dummy, (void *) READY_TO_BOOT); -- To view, visit https://review.coreboot.org/c/coreboot/+/43979 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I122edc12abf992cb3e5ec53747a7cef9c94aee8e Gerrit-Change-Number: 43979 Gerrit-PatchSet: 1 Gerrit-Owner: Rocky Phagura Gerrit-MessageType: newchange

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Change in coreboot[master]: TEST-ONLY: soc/mediatek/mt8192: disable emi bw threshold monitor
by Xi Chen (Code Review) 16 Feb '22

16 Feb '22

Xi Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47383 ) Change subject: TEST-ONLY: soc/mediatek/mt8192: disable emi bw threshold monitor ...................................................................... TEST-ONLY: soc/mediatek/mt8192: disable emi bw threshold monitor Signed-off-by: Xi Chen <xixi.chen(a)mediatek.com> Change-Id: I6053da10a1f41836cb455d30fd2bcd7a84047121 --- M src/soc/mediatek/mt8192/emi.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/47383/1 diff --git a/src/soc/mediatek/mt8192/emi.c b/src/soc/mediatek/mt8192/emi.c old mode 100644 new mode 100755 index d485131..4b971d0 --- a/src/soc/mediatek/mt8192/emi.c +++ b/src/soc/mediatek/mt8192/emi.c @@ -346,9 +346,11 @@ setbits32(&emi_mpu->mpu_ctrl_d[1], BIT(4)); setbits32(&emi_mpu->mpu_ctrl_d[7], BIT(4)); +#ifdef ENABLE_EMI_BW_THRESHOLD write32(&emi_reg->bwct0, 0x05008305); write32(&emi_reg->bwct0_6th, 0x08ff8705); write32(&emi_reg->bwct0_3rd, 0x0dff8a05); +#endif setbits32(&emi_reg->thro_ctrl1, 0x3 << 8); } -- To view, visit https://review.coreboot.org/c/coreboot/+/47383 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6053da10a1f41836cb455d30fd2bcd7a84047121 Gerrit-Change-Number: 47383 Gerrit-PatchSet: 1 Gerrit-Owner: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: TEST-ONLY: soc/mediatek/mt8192: add dram full scan
by Xi Chen (Code Review) 16 Feb '22

16 Feb '22

Xi Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48071 ) Change subject: TEST-ONLY: soc/mediatek/mt8192: add dram full scan ...................................................................... TEST-ONLY: soc/mediatek/mt8192: add dram full scan Used to check all dram address read/write is ok or not. Signed-off-by: Xi Chen <xixi.chen(a)mediatek.com> Change-Id: I4d1c7adfd49910287ceccf08d667acdc41b209d5 --- M src/soc/mediatek/common/memory_test.c M src/soc/mediatek/mt8192/include/soc/emi.h M src/soc/mediatek/mt8192/memory.c 3 files changed, 64 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/48071/1 diff --git a/src/soc/mediatek/common/memory_test.c b/src/soc/mediatek/common/memory_test.c index 51f3b23..b917341 100644 --- a/src/soc/mediatek/common/memory_test.c +++ b/src/soc/mediatek/common/memory_test.c @@ -1,6 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <soc/emi.h> +#include <console/console.h> + +#define LOGH printk(BIOS_ERR, "%s@%d\n", __func__, __LINE__); enum { /* test patterns */ @@ -22,6 +25,37 @@ PATTERNF = 0xFFFFFFFF }; +int mem_test_fullscan(u8 *start, unsigned long long len) +{ + unsigned int *mem32_base = (unsigned int *)start; + unsigned long long i, size; + + printk(BIOS_INFO, "Test length: 0x%llx\n", len); + LOGH; + size = len >> 2; + + /* verify the tied bits (tied high) */ + for (i = 0; i < size; i++) { + mem32_base[i] = (unsigned int)i; + if (i % 100000 == 0) + printk(BIOS_INFO, "mem write: pos: %llx\n", i); + } + + LOGH; + for (i = 0; i < size; i++) { + if (mem32_base[i] != (unsigned int)i) { + printk(BIOS_ERR, "%s failed at %llx, value: 0x%x, expected: 0x%x\n", + __func__, i, (unsigned int)i, mem32_base[i]); + return -1; + } + if (i % 100000 == 0) + printk(BIOS_INFO, "mem compare: pos: %llx\n", i); + } + + return 0; +} + + int complex_mem_test(u8 *start, unsigned int len) { unsigned char *mem8_base = (unsigned char *)start; @@ -34,12 +68,14 @@ unsigned int value; uintptr_t p; + LOGH; size = len >> 2; /* verify the tied bits (tied high) */ for (i = 0; i < size; i++) mem32_base[i] = PATTERN0; + LOGH; for (i = 0; i < size; i++) { if (mem32_base[i] != PATTERN0) return -1; @@ -47,6 +83,7 @@ mem32_base[i] = PATTERNF; } + LOGH; /* verify the tied bits (tied low) */ for (i = 0; i < size; i++) { if (mem32_base[i] != PATTERNF) @@ -58,11 +95,14 @@ pattern8 = PATTERN0; for (i = 0; i < len; i++) mem8_base[i] = pattern8++; + + LOGH; pattern8 = PATTERN0; for (i = 0; i < len; i++) { if (mem8_base[i] != pattern8++) return -3; } + LOGH; /* verify pattern 2 (0x00~0xff) */ pattern8 = PATTERN0; @@ -74,7 +114,8 @@ pattern8 += 2; } - + LOGH; + /* verify pattern 3 (0x00~0xffff) */ pattern16 = PATTERN0; for (i = 0; i < (len >> 1); i++) @@ -84,7 +125,7 @@ if (mem16_base[i] != pattern16++) return -5; } - + LOGH; /* verify pattern 4 (0x00~0xffffffff) */ pattern32 = PATTERN0; for (i = 0; i < (len >> 2); i++) @@ -94,7 +135,7 @@ if (mem32_base[i] != pattern32++) return -6; } - + LOGH; /* pattern 5: filling memory range with 0x12345678 */ for (i = 0; i < size; i++) mem32_base[i] = PATTERNE; @@ -106,7 +147,7 @@ mem32_base[i] = PATTERN2; } - + LOGH; /* read check then fill memory with 00 byte pattern at offset 0h */ for (i = 0; i < size; i++) { if (mem32_base[i] != PATTERN2) @@ -114,7 +155,7 @@ mem8_base[i * 4] = PATTERN0; } - + LOGH; /* read check then fill memory with 00 byte pattern at offset 2h */ for (i = 0; i < size; i++) { if (mem32_base[i] != PATTERN3) @@ -122,7 +163,7 @@ mem8_base[i * 4 + 2] = PATTERN0; } - + LOGH; /* read check then fill memory with 00 byte pattern at offset 1h */ for (i = 0; i < size; i++) { if (mem32_base[i] != PATTERN4) @@ -130,7 +171,7 @@ mem8_base[i * 4 + 1] = PATTERN0; } - + LOGH; /* read check then fill memory with 00 byte pattern at offset 3h */ for (i = 0; i < size; i++) { if (mem32_base[i] != PATTERN5) @@ -138,7 +179,7 @@ mem8_base[i * 4 + 3] = PATTERN0; } - + LOGH; /* read check then fill memory with ffff word pattern at offset 1h */ for (i = 0; i < size; i++) { if (mem32_base[i] != PATTERN0) @@ -146,7 +187,7 @@ mem16_base[i * 2 + 1] = PATTERN7; } - + LOGH; /* read check then fill memory with ffff word pattern at offset 0h */ for (i = 0; i < size; i++) { if (mem32_base[i] != PATTERN6) @@ -154,13 +195,13 @@ mem16_base[i * 2] = PATTERN7; } - + LOGH; /* read check */ for (i = 0; i < size; i++) { if (mem32_base[i] != PATTERNF) return -14; } - + LOGH; /* stage 1 => write 0 */ for (i = 0; i < size; i++) mem_base[i] = PATTERN1; @@ -174,7 +215,7 @@ mem_base[i] = PATTERN2; } - + LOGH; /* stage 3 => read 0xf, write 0 */ for (i = 0; i < size; i++) { value = mem_base[i]; @@ -183,7 +224,7 @@ mem_base[i] = PATTERN1; } - + LOGH; /* stage 4 => read 0, write 0xf */ for (i = 0; i < size; i++) { value = mem_base[i]; @@ -192,7 +233,7 @@ mem_base[i] = PATTERN2; } - + LOGH; /* stage 5 => read 0xf, write 0 */ for (i = 0; i < size; i++) { value = mem_base[i]; @@ -201,14 +242,14 @@ mem_base[i] = PATTERN1; } - + LOGH; /* stage 6 => read 0 */ for (i = 0; i < size; i++) { value = mem_base[i]; if (value != PATTERN1) return -19; } - + LOGH; /* 1/2/4-byte combination test */ p = (uintptr_t)mem_base; @@ -246,13 +287,13 @@ *((unsigned int *)p) = PATTERNE; p += 4; } - + LOGH; for (i = 0; i < size; i++) { value = mem_base[i]; if (value != PATTERNE) return -20; } - + LOGH; /* verify pattern 1 (0x00~0xff) */ pattern8 = PATTERN0; mem8_base[0] = pattern8; @@ -268,7 +309,7 @@ pattern8++; } - + LOGH; /* verify pattern 2 (0x00~0xffff) */ pattern16 = PATTERN0; mem16_base[0] = pattern16; @@ -280,7 +321,7 @@ pattern16++; } - + LOGH; /* verify pattern 3 (0x00~0xffffffff) */ pattern32 = PATTERN0; mem32_base[0] = pattern32; @@ -292,6 +333,6 @@ pattern32++; } - + LOGH; return 0; } diff --git a/src/soc/mediatek/mt8192/include/soc/emi.h b/src/soc/mediatek/mt8192/include/soc/emi.h old mode 100644 new mode 100755 index 02a90be..fee49ed --- a/src/soc/mediatek/mt8192/include/soc/emi.h +++ b/src/soc/mediatek/mt8192/include/soc/emi.h @@ -9,5 +9,6 @@ void mt_set_emi(const struct dramc_data *dparam); void mt_mem_init(struct dramc_param_ops *dparam_ops); int complex_mem_test(u8 *start, unsigned int len); +int mem_test_fullscan(u8 *start, unsigned long long len); #endif /* SOC_MEDIATEK_MT8192_EMI_H */ diff --git a/src/soc/mediatek/mt8192/memory.c b/src/soc/mediatek/mt8192/memory.c old mode 100644 new mode 100755 index 549dede..3f90d30 --- a/src/soc/mediatek/mt8192/memory.c +++ b/src/soc/mediatek/mt8192/memory.c @@ -16,7 +16,7 @@ const struct ddr_base_info *ddr_info = &dparam->ddr_info; for (u8 rank = RANK_0; rank < ddr_info->support_ranks; rank++) { - int result = complex_mem_test(addr, 0x2000); + int result = mem_test_fullscan(addr, (unsigned long long)sdram_size()); if (result != 0) { printk(BIOS_ERR, -- To view, visit https://review.coreboot.org/c/coreboot/+/48071 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d1c7adfd49910287ceccf08d667acdc41b209d5 Gerrit-Change-Number: 48071 Gerrit-PatchSet: 1 Gerrit-Owner: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: checkpatch: fix parsing xxx_for_each_xxx function declaration as list...
by Xi Chen (Code Review) 16 Feb '22

16 Feb '22

Xi Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48560 ) Change subject: checkpatch: fix parsing xxx_for_each_xxx function declaration as list macro style ...................................................................... checkpatch: fix parsing xxx_for_each_xxx function declaration as list macro style Originally[C, xxx_for_each_xxx style matches list style macro, it also matches function declaration. It will cause alert that '{' should be on the previous line. For example: static void set_vcore_voltage_for_each_freq(const struct ddr_cali *cali) { Signed-off-by: Xi Chen <xixi.chen(a)mediatek.com> Change-Id: Iacbfefc6c9a3c8b58ba77085890bc4239dac1858 --- M util/lint/checkpatch.pl 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/48560/1 diff --git a/util/lint/checkpatch.pl b/util/lint/checkpatch.pl old mode 100755 new mode 100644 index 1affdb7..9536147 --- a/util/lint/checkpatch.pl +++ b/util/lint/checkpatch.pl @@ -3471,7 +3471,8 @@ # if/while/etc brace do not go on next line, unless defining a do while loop, # or if that brace on the next line is for something else - if ($line =~ /(.*)\b((?:if|while|for|switch|(?:[a-z_]+|)for_each[a-z_]+)\s*\(|do\b|else\b)/ && $line !~ /^.\s*\#/) { + if ($line =~ /(.*)\b((?:if|while|for|switch)\s*\(|do\b|else\b)/ || $line =~ /^(?:[a-z_]+|)for_each[a-z_]+\s*\(|do\b|else\b/ + && $line !~ /^.\s*\#/) { my $pre_ctx = "$1$2"; my ($level, @ctx) = ctx_statement_level($linenr, $realcnt, 0); -- To view, visit https://review.coreboot.org/c/coreboot/+/48560 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iacbfefc6c9a3c8b58ba77085890bc4239dac1858 Gerrit-Change-Number: 48560 Gerrit-PatchSet: 1 Gerrit-Owner: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede/var/drawcia: Enable microcode in-field update
by Sugnan Prabhu S (Code Review) 14 Feb '22

14 Feb '22

Sugnan Prabhu S has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47199 ) Change subject: mb/google/dedede/var/drawcia: Enable microcode in-field update ...................................................................... mb/google/dedede/var/drawcia: Enable microcode in-field update This enables the top swap based microcode in-field update. BUG=b:149547271 TEST=Build and boot drawcia to OS. Check ucode staging area is updated with microcode in FW_MAIN_A/B and the top swap is enabled. Change-Id: I40f2a628d6408930d698756e2cb6f8c535623cf9 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> --- M src/mainboard/google/dedede/Kconfig.name 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/47199/1 diff --git a/src/mainboard/google/dedede/Kconfig.name b/src/mainboard/google/dedede/Kconfig.name index 31495a1..238b4ca 100644 --- a/src/mainboard/google/dedede/Kconfig.name +++ b/src/mainboard/google/dedede/Kconfig.name @@ -22,6 +22,8 @@ select DRIVERS_GENERIC_MAX98357A select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR select DRIVERS_INTEL_MIPI_CAMERA + select INTEL_TOP_SWAP_MULTI_FIT_UCODE_UPDATE + select SOC_INTEL_COMMON_BASECODE select SOC_INTEL_COMMON_BLOCK_IPU config BOARD_GOOGLE_DRAWCIA_LEGACY -- To view, visit https://review.coreboot.org/c/coreboot/+/47199 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40f2a628d6408930d698756e2cb6f8c535623cf9 Gerrit-Change-Number: 47199 Gerrit-PatchSet: 1 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer/var/terrador: Add gpio-keys ACPI node for PENH
by David Wu (Code Review) 08 Feb '22

08 Feb '22

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48522 ) Change subject: mb/google/volteer/var/terrador: Add gpio-keys ACPI node for PENH ...................................................................... mb/google/volteer/var/terrador: Add gpio-keys ACPI node for PENH Use gpio_keys driver to add ACPI node for pen eject event. Also setting gpio wake pin for wake events. BUG=None TEST=tested on a Terrador Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: I314d90200a508cba9ac144797fe20d4423820a4c --- M src/mainboard/google/volteer/variants/terrador/gpio.c M src/mainboard/google/volteer/variants/terrador/overridetree.cb 2 files changed, 14 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/48522/1 diff --git a/src/mainboard/google/volteer/variants/terrador/gpio.c b/src/mainboard/google/volteer/variants/terrador/gpio.c index a0267cc..738341b 100644 --- a/src/mainboard/google/volteer/variants/terrador/gpio.c +++ b/src/mainboard/google/volteer/variants/terrador/gpio.c @@ -111,7 +111,7 @@ /* E16 : ISH_GP7 ==> USB_A0_RT_RST_ODL */ PAD_CFG_GPO(GPP_E16, 1, DEEP), /* E17 : THC0_SPI1_INT# ==> PEN_DET_ODL */ - PAD_CFG_GPI_SCI_LOW(GPP_E1, NONE, DEEP, EDGE_SINGLE), + PAD_CFG_GPI(GPP_E17, NONE, DEEP), /* E19 : DDP1_CTRLDATA ==> USB0_C0_LSX_SOC_RX_STRAP */ PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF4), diff --git a/src/mainboard/google/volteer/variants/terrador/overridetree.cb b/src/mainboard/google/volteer/variants/terrador/overridetree.cb index 039dc85..e4c7824 100644 --- a/src/mainboard/google/volteer/variants/terrador/overridetree.cb +++ b/src/mainboard/google/volteer/variants/terrador/overridetree.cb @@ -113,6 +113,19 @@ register "hid_desc_reg_offset" = "0x01" device i2c 10 on end end + chip drivers/generic/gpio_keys + register "name" = ""PENH"" + # GPP_E17 is the IRQ source, and GPP_E1 is the wake source + register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_E17)" + register "key.wake_gpe" = "GPE0_DW2_01" + register "key.wakeup_route" = "WAKEUP_ROUTE_SCI" + register "key.wakeup_event_action" = "EV_ACT_DEASSERTED" + register "key.dev_name" = ""EJCT"" + register "key.linux_code" = "SW_PEN_INSERTED" + register "key.linux_input_type" = "EV_SW" + register "key.label" = ""pen_eject"" + device generic 0 on end + end end device ref i2c5 on chip drivers/i2c/hid -- To view, visit https://review.coreboot.org/c/coreboot/+/48522 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I314d90200a508cba9ac144797fe20d4423820a4c Gerrit-Change-Number: 48522 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/asus/p2b: list all unused Super I/O resources
by Keith Hui (Code Review) 03 Feb '22

03 Feb '22

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41459 ) Change subject: mb/asus/p2b: list all unused Super I/O resources ...................................................................... mb/asus/p2b: list all unused Super I/O resources Some Super I/O resources were unused and not listed, causing warnings during resource allocation. Suppress these warnings by setting them to zero. Change-Id: I28e37c3a58f3a6b5a613733f26ac18d6a7b3be2e Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/mainboard/asus/p2b/devicetree.cb 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/41459/1 diff --git a/src/mainboard/asus/p2b/devicetree.cb b/src/mainboard/asus/p2b/devicetree.cb index 9f7f63e..7ee69e4 100644 --- a/src/mainboard/asus/p2b/devicetree.cb +++ b/src/mainboard/asus/p2b/devicetree.cb @@ -18,6 +18,7 @@ device pnp 3f0.1 on # Parallel port io 0x60 = 0x378 irq 0x70 = 7 + drq 0x74 = 0 end device pnp 3f0.2 on # COM1 io 0x60 = 0x3f8 @@ -34,6 +35,9 @@ irq 0x72 = 12 # PS/2 mouse interrupt end device pnp 3f0.7 on # GPIO 1 + io 0x60 = 0 + io 0x62 = 0 + irq 0x70 = 0 end device pnp 3f0.8 on # GPIO 2 end -- To view, visit https://review.coreboot.org/c/coreboot/+/41459 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I28e37c3a58f3a6b5a613733f26ac18d6a7b3be2e Gerrit-Change-Number: 41459 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel: Introduce SCMI Kconfig options
by Keith Hui (Code Review) 03 Feb '22

03 Feb '22

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48921 ) Change subject: sb/intel: Introduce SCMI Kconfig options ...................................................................... sb/intel: Introduce SCMI Kconfig options Introduce two options for enabling SMBus Control Method Interface [1] support. 1. HAVE_SCMI is to be set by southbridges that implements SCMI in the DSDT. That implementation should be conditional on USE_SCMI. See below. 2. USE_SCMI is guarded by HAVE_SCMI and actually provides the option to the user in Kconfig. Enabling it adds the SCMI implementation to the DSDT and make it usable. Boards that require this support for board function should set it in their BOARD_SPECIFIC_OPTIONS, which will lock this option on. It will be used by CB:41735 but are designed for wider adoption e.g. by CB:44507 [1] http://smbus.org/specs/smbus_cmi10.pdf [41735] https://review.coreboot.org/c/coreboot/+/41735 [44507] https://review.coreboot.org/c/coreboot/+/44507 Change-Id: Ib1e176b6495fa673fd46cbb8f8fd7c5a41ababde Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/southbridge/intel/common/Kconfig 1 file changed, 19 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/48921/1 diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig index 3030d25..11ba094 100644 --- a/src/southbridge/intel/common/Kconfig +++ b/src/southbridge/intel/common/Kconfig @@ -105,3 +105,22 @@ hex depends on SOUTHBRIDGE_INTEL_COMMON_SMBUS default 0x400 + +config HAVE_SCMI + bool + help + Selected by southbridges that implements SCMI in their DSDT. + See http://smbus.org/specs/smbus_cmi10.pdf for details. + +config USE_SCMI + bool "Enable SMBus Control Method Interface (SCMI)" + depends on HAVE_SCMI && HAVE_ACPI_TABLES + help + Adds extra access methods conforming to the SMBus Control Method Interface (SCMI) + specification to the SMBus ACPI device. This provides alternate SMBus access if + regular means are unavailable due to e.g. resource conflicts. + + ASUS P3B-F mainboard is known to need this. + + If you say Y here, you will have to blacklist the native driver and instead use + i2c-scmi driver to access SMBus-connected devices. -- To view, visit https://review.coreboot.org/c/coreboot/+/48921 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib1e176b6495fa673fd46cbb8f8fd7c5a41ababde Gerrit-Change-Number: 48921 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 9

Change in ...coreboot[master]: soc/intel/apl: enable lpc at bootblock
by Thomas Heijligen (Code Review) 01 Feb '22

01 Feb '22

Hello Nico Huber, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/31371 to review the following change. Change subject: soc/intel/apl: enable lpc at bootblock ...................................................................... soc/intel/apl: enable lpc at bootblock Serial console can be attached to lpc bus. Enable it for early debug Change-Id: Ib3d09e4eb23655825b7603f49f0bad31116ac6e1 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Signed-off-by: Thomas Heijligen <thomas.heijligen(a)secunet.com> --- M src/soc/intel/apollolake/bootblock/bootblock.c M src/soc/intel/apollolake/chip.h M src/soc/intel/apollolake/lpc.c M src/soc/intel/common/block/lpc/lpc_lib.c 4 files changed, 21 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/31371/1 diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index cf3e839..e0217ef 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -20,6 +20,7 @@ #include <device/pci.h> #include <intelblocks/cpulib.h> #include <intelblocks/fast_spi.h> +#include <intelblocks/lpc_lib.h> #include <intelblocks/p2sb.h> #include <intelblocks/pcr.h> #include <intelblocks/rtc.h> @@ -120,4 +121,6 @@ paging_set_default_pat(); paging_enable_for_car("pdpt", "pt"); } + + pch_enable_lpc(); } diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index b8f9f8c..2f25a3b 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -44,6 +44,9 @@ /* Common structure containing soc config data required by common code*/ struct soc_intel_common_config common_soc_config; + /* Generic i/o decode ranges routed to LPC */ + uint32_t lpc_gen_dec[4]; + /* * Mapping from PCIe root port to CLKREQ input on the SOC. The SOC has * four CLKREQ inputs, but six root ports. Root ports without an diff --git a/src/soc/intel/apollolake/lpc.c b/src/soc/intel/apollolake/lpc.c index a20b82a..ffa4cf5 100644 --- a/src/soc/intel/apollolake/lpc.c +++ b/src/soc/intel/apollolake/lpc.c @@ -42,6 +42,18 @@ return apl_lpc_fixed_mmio_ranges; } +void soc_get_gen_io_dec_range(const struct device *dev, uint32_t *gen_io_dec) +{ + const struct soc_intel_apollolake_config *const config = dev->chip_info; + + if (!config) { + memset(gen_io_dec, 0x00, sizeof(config->lpc_gen_dec)); + return; + } + + memcpy(gen_io_dec, config->lpc_gen_dec, sizeof(config->lpc_gen_dec)); +} + static const struct pad_config lpc_gpios[] = { #if IS_ENABLED(CONFIG_SOC_INTEL_GLK) #if !IS_ENABLED(CONFIG_SOC_ESPI) diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c index fb50b74..d584d2c 100644 --- a/src/soc/intel/common/block/lpc/lpc_lib.c +++ b/src/soc/intel/common/block/lpc/lpc_lib.c @@ -24,6 +24,9 @@ #include <lib.h> #include "lpc_def.h" #include <soc/pci_devs.h> +#include <stdint.h> + +__weak void soc_setup_dmi_pcr_io_dec(uint32_t *gen_io_dec) {} uint16_t lpc_enable_fixed_io_ranges(uint16_t io_enables) { -- To view, visit https://review.coreboot.org/c/coreboot/+/31371 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib3d09e4eb23655825b7603f49f0bad31116ac6e1 Gerrit-Change-Number: 31371 Gerrit-PatchSet: 1 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

7 16

Change in coreboot[master]: sc7280: enable bl31
by Ravi kumar (Code Review) 28 Jan '22

28 Jan '22

Ravi kumar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47904 ) Change subject: sc7280: enable bl31 ...................................................................... sc7280: enable bl31 Developer/Reviewer, be aware of this patch from Napali: https://review.coreboot.org/c/coreboot/+/28014/44 Signed-off-by: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Change-Id: I61c695fb4fef3ae36ffc5a263236b9d40c299dc4 --- M src/soc/qualcomm/sc7280/Kconfig M src/soc/qualcomm/sc7280/memlayout.ld 2 files changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/47904/1 diff --git a/src/soc/qualcomm/sc7280/Kconfig b/src/soc/qualcomm/sc7280/Kconfig index d6f56ba..6882457 100644 --- a/src/soc/qualcomm/sc7280/Kconfig +++ b/src/soc/qualcomm/sc7280/Kconfig @@ -6,6 +6,7 @@ select ARCH_RAMSTAGE_ARMV8_64 select ARCH_ROMSTAGE_ARMV8_64 select ARCH_VERSTAGE_ARMV8_64 + select ARM64_USE_ARM_TRUSTED_FIRMWARE select GENERIC_GPIO_LIB select GENERIC_UDELAY select HAVE_MONOTONIC_TIMER diff --git a/src/soc/qualcomm/sc7280/memlayout.ld b/src/soc/qualcomm/sc7280/memlayout.ld index a3a785e..fed3a72 100644 --- a/src/soc/qualcomm/sc7280/memlayout.ld +++ b/src/soc/qualcomm/sc7280/memlayout.ld @@ -50,7 +50,7 @@ /* Various hardware/software subsystems make use of this area */ REGION(dram_aop, 0x80800000, 0x040000, 0x1000) REGION(dram_soc, 0x80900000, 0x200000, 0x1000) - BL31(0x80B00000, 1M) POSTRAM_CBFS_CACHE(0x9F800000, 16M) RAMSTAGE(0xA0800000, 16M) + BL31(0xC0000000, 1M) } -- To view, visit https://review.coreboot.org/c/coreboot/+/47904 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I61c695fb4fef3ae36ffc5a263236b9d40c299dc4 Gerrit-Change-Number: 47904 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

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