coreboot-gerrit December 2021

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Change in coreboot[master]: soc/intel/tigerlake: Hook up DPTF device to devicetree
by Felix Singer (Code Review) 09 Dec '21

09 Dec '21

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59886 ) Change subject: soc/intel/tigerlake: Hook up DPTF device to devicetree ...................................................................... soc/intel/tigerlake: Hook up DPTF device to devicetree Hook up `Device4Enable` FSP setting to devicetree state and drop its redundant devicetree setting `Device4Enable`. The following mainboards enable the DPTF device in the devicetree despite `Device4Enable` is not being set. * google/deltaur Thus, set it to off to keep the current state unchanged. Change-Id: Ic7636fc4f63d4beab92e742a6882ac55af2565bc Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59886 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/deltaur/variants/baseboard/devicetree.cb M src/mainboard/google/volteer/variants/baseboard/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb M src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb M src/mainboard/system76/darp7/devicetree.cb M src/mainboard/system76/galp5/devicetree.cb M src/mainboard/system76/gaze16/devicetree.cb M src/mainboard/system76/lemp10/devicetree.cb M src/mainboard/system76/oryp8/devicetree.cb M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/fsp_params.c 12 files changed, 8 insertions(+), 30 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb index 643bdc1..aeab2d4 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb @@ -130,7 +130,7 @@ device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Graphics - device pci 04.0 on end # DPTF + device pci 04.0 off end # DPTF device pci 05.0 off end # IPU device pci 06.0 off end # PEG60 device pci 07.0 on end # TBT_PCIe0 diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index ca9661f..1958e99 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -295,8 +295,6 @@ .tdp_pl4 = 83, }" - register "Device4Enable" = "1" - register "tcc_offset" = "10" # TCC of 90 register "CnviBtCore" = "true" diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 0e34eb2..47c4368 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -119,9 +119,6 @@ # Enable DPTF register "dptf_enable" = "1" - # Enable Processor Thermal Control - register "Device4Enable" = "1" - # Add PL1 and PL2 values register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ .tdp_pl1_override = 15, diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index 17af01a..cd5493b 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -123,9 +123,6 @@ # Enable DPTF register "dptf_enable" = "1" - # Enable Processor Thermal Control - register "Device4Enable" = "1" - # Add PL1 and PL2 values register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ .tdp_pl1_override = 9, diff --git a/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb b/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb index 5c55dce..a3fc715 100644 --- a/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb +++ b/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb @@ -76,9 +76,7 @@ device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 on # SA Thermal Device - register "Device4Enable" = "1" - end + device pci 04.0 on end # SA Thermal Device device pci 05.0 off end # IPU device pci 06.0 off end # PEG60 device pci 07.0 on end # TBT_PCIe0 diff --git a/src/mainboard/system76/darp7/devicetree.cb b/src/mainboard/system76/darp7/devicetree.cb index 7a3e072..dc369ad 100644 --- a/src/mainboard/system76/darp7/devicetree.cb +++ b/src/mainboard/system76/darp7/devicetree.cb @@ -105,9 +105,7 @@ register "gfx" = "GMA_DEFAULT_PANEL(0)" end - device ref dptf on - register "Device4Enable" = "1" - end + device ref dptf on end device ref peg on # PCIe PEG0 x4, Clock 0 (SSD1) register "PcieClkSrcUsage[0]" = "0x40" diff --git a/src/mainboard/system76/galp5/devicetree.cb b/src/mainboard/system76/galp5/devicetree.cb index aabeedb..3764d07 100644 --- a/src/mainboard/system76/galp5/devicetree.cb +++ b/src/mainboard/system76/galp5/devicetree.cb @@ -105,9 +105,7 @@ register "gfx" = "GMA_DEFAULT_PANEL(0)" end - device ref dptf on - register "Device4Enable" = "1" - end + device ref dptf on end device ref peg on # PCIe PEG0 x4, Clock 0 (SSD1) register "PcieClkSrcUsage[0]" = "0x40" diff --git a/src/mainboard/system76/gaze16/devicetree.cb b/src/mainboard/system76/gaze16/devicetree.cb index f5f216c..8b43202 100644 --- a/src/mainboard/system76/gaze16/devicetree.cb +++ b/src/mainboard/system76/gaze16/devicetree.cb @@ -96,9 +96,7 @@ register "DdiPortBHpd" = "1" register "DdiPortBDdc" = "1" end - device ref dptf on - register "Device4Enable" = "1" - end + device ref dptf on end device ref gna on end device ref north_xhci on # TODO: No TBT, but needed for USB 2.0 on Type-C port? diff --git a/src/mainboard/system76/lemp10/devicetree.cb b/src/mainboard/system76/lemp10/devicetree.cb index 2c03e60..21928ec 100644 --- a/src/mainboard/system76/lemp10/devicetree.cb +++ b/src/mainboard/system76/lemp10/devicetree.cb @@ -105,9 +105,7 @@ register "gfx" = "GMA_DEFAULT_PANEL(0)" end - device ref dptf on - register "Device4Enable" = "1" - end + device ref dptf on end device ref peg on # PCIe PEG0 x4, Clock 3 (SSD1) # Despite the name, SSD2_CLKREQ# is used for SSD1 diff --git a/src/mainboard/system76/oryp8/devicetree.cb b/src/mainboard/system76/oryp8/devicetree.cb index 4263806..e6372fd 100644 --- a/src/mainboard/system76/oryp8/devicetree.cb +++ b/src/mainboard/system76/oryp8/devicetree.cb @@ -110,9 +110,7 @@ register "DdiPortAHpd" = "1" register "DdiPortADdc" = "0" end - device ref dptf on - register "Device4Enable" = "1" - end + device ref dptf on end device ref peg0 on # PCIe PEG0 x4, Clock 7 (SSD1) register "PcieClkSrcUsage[7]" = "0x40" diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 09c8db1..fb0d827 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -274,8 +274,6 @@ /* Gfx related */ uint8_t SkipExtGfxScan; - uint8_t Device4Enable; - /* HeciEnabled decides the state of Heci1 at end of boot * Setting to 0 (default) disables Heci1 and hides the device from OS */ uint8_t HeciEnabled; diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index 89c8126..40676f1 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -474,7 +474,7 @@ params->SlowSlewRate[0] = config->SlowSlewRate; /* Enable TCPU for processor thermal control */ - params->Device4Enable = config->Device4Enable; + params->Device4Enable = is_devfn_enabled(SA_DEVFN_DPTF); /* Set TccActivationOffset */ params->TccActivationOffset = config->tcc_offset; 5 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/59886 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic7636fc4f63d4beab92e742a6882ac55af2565bc Gerrit-Change-Number: 59886 Gerrit-PatchSet: 7 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/tigerlake: Drop unused SataEnable setting
by Felix Singer (Code Review) 09 Dec '21

09 Dec '21

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59884 ) Change subject: soc/intel/tigerlake: Drop unused SataEnable setting ...................................................................... soc/intel/tigerlake: Drop unused SataEnable setting `SataEnable` is set by some boards, but it doesn't have any effect since its related FSP option is hooked up to the devicetree state. Thus, drop it. Change-Id: Id645bfcade7ca1d495fb8df538113b3d10392a82 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59884 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/google/deltaur/variants/baseboard/devicetree.cb M src/mainboard/google/volteer/variants/baseboard/devicetree.cb M src/soc/intel/tigerlake/chip.h 3 files changed, 0 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb index 9ed8fb2..643bdc1 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb @@ -25,7 +25,6 @@ # FSP configuration register "SaGv" = "SaGv_Disabled" - register "SataEnable" = "1" register "SataMode" = "0" register "SataSalpSupport" = "1" diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index eee29ef..ca9661f 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -146,7 +146,6 @@ register "PcieClkSrcUsage[6]" = "PCIE_CLK_NOTUSED" # Enable SATA - register "SataEnable" = "1" register "SataMode" = "0" register "SataSalpSupport" = "1" register "SataPortsEnable[0]" = "0" diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index e729e8c..09c8db1 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -215,7 +215,6 @@ uint8_t SlowSlewRate; /* SATA related */ - uint8_t SataEnable; uint8_t SataMode; uint8_t SataSalpSupport; uint8_t SataPortsEnable[8]; 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/59884 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id645bfcade7ca1d495fb8df538113b3d10392a82 Gerrit-Change-Number: 59884 Gerrit-PatchSet: 6 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/starlabs/labtop: Enable SMBus in Device Tree
by Felix Singer (Code Review) 09 Dec '21

09 Dec '21

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59926 ) Change subject: mb/starlabs/labtop: Enable SMBus in Device Tree ...................................................................... mb/starlabs/labtop: Enable SMBus in Device Tree Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I8bc3025331bb25b02712b5d2b654f7997f0aba4a Reviewed-on: https://review.coreboot.org/c/coreboot/+/59926 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved diff --git a/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb b/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb index c8abce9..5c55dce 100644 --- a/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb +++ b/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb @@ -232,7 +232,7 @@ subsystemid 0x10ec 0x1200 register "PchHdaAudioLinkHdaEnable" = "1" end - device pci 1f.4 off end # SMBus + device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI device pci 1f.6 off end # GbE device pci 1f.7 off end # TH -- To view, visit https://review.coreboot.org/c/coreboot/+/59926 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8bc3025331bb25b02712b5d2b654f7997f0aba4a Gerrit-Change-Number: 59926 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/starlabs/labtop: Enable SMBus in Device Tree
by Felix Singer (Code Review) 09 Dec '21

09 Dec '21

Attention is currently required from: Sean Rhodes. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59926 ) Change subject: mb/starlabs/labtop: Enable SMBus in Device Tree ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59926 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8bc3025331bb25b02712b5d2b654f7997f0aba4a Gerrit-Change-Number: 59926 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Comment-Date: Thu, 09 Dec 2021 21:52:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Hook up SMBus device to devicetree
by Felix Singer (Code Review) 09 Dec '21

09 Dec '21

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59883 ) Change subject: soc/intel/tigerlake: Hook up SMBus device to devicetree ...................................................................... soc/intel/tigerlake: Hook up SMBus device to devicetree Hook up `SmbusEnable` FSP setting to devicetree state and drop its redundant devicetree setting `SmbusEnable`. The following mainboards enable the SMBus device in the devicetree despite `SmbusEnable` is not being set. * google/deltaur * starlabs/laptop Thus, set it to off to keep the current state unchanged. Change-Id: I0789af20beb147fc1a6a7d046cdcea15cb44ce4c Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59883 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/deltaur/variants/baseboard/devicetree.cb M src/mainboard/google/volteer/variants/baseboard/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb M src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb M src/mainboard/system76/darp7/devicetree.cb M src/mainboard/system76/galp5/devicetree.cb M src/mainboard/system76/gaze16/devicetree.cb M src/mainboard/system76/lemp10/devicetree.cb M src/mainboard/system76/oryp8/devicetree.cb M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/romstage/fsp_params.c 12 files changed, 7 insertions(+), 22 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb index 72ed789..9ed8fb2 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb @@ -291,7 +291,7 @@ device pci 1f.1 off end # P2SB device pci 1f.2 hidden end # PMC device pci 1f.3 on end # Intel HDA - device pci 1f.4 on end # SMBus + device pci 1f.4 off end # SMBus device pci 1f.5 on end # PCH SPI Flash Controller device pci 1f.6 off end # GbE Controller device pci 1f.7 off end # Intel Trace Hub diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index b4c4f6a..eee29ef 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -92,7 +92,6 @@ # FSP configuration register "SaGv" = "SaGv_Enabled" - register "SmbusEnable" = "0" register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0 register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A1 diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index b84fddc..0e34eb2 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -13,7 +13,6 @@ # FSP configuration register "SaGv" = "SaGv_Enabled" - register "SmbusEnable" = "1" # CNVi BT enable/disable register "CnviBtCore" = "true" diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index fcadcee..17af01a 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -13,7 +13,6 @@ # FSP configuration register "SaGv" = "SaGv_Disabled" - register "SmbusEnable" = "1" # CNVi BT enable/disable register "CnviBtCore" = "true" diff --git a/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb b/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb index 5c55dce..c8abce9 100644 --- a/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb +++ b/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb @@ -232,7 +232,7 @@ subsystemid 0x10ec 0x1200 register "PchHdaAudioLinkHdaEnable" = "1" end - device pci 1f.4 on end # SMBus + device pci 1f.4 off end # SMBus device pci 1f.5 on end # PCH SPI device pci 1f.6 off end # GbE device pci 1f.7 off end # TH diff --git a/src/mainboard/system76/darp7/devicetree.cb b/src/mainboard/system76/darp7/devicetree.cb index 8c16d2a..7a3e072 100644 --- a/src/mainboard/system76/darp7/devicetree.cb +++ b/src/mainboard/system76/darp7/devicetree.cb @@ -329,9 +329,7 @@ device ref hda on register "PchHdaAudioLinkHdaEnable" = "1" end - device ref smbus on - register "SmbusEnable" = "1" - end + device ref smbus on end device ref fast_spi on end end end diff --git a/src/mainboard/system76/galp5/devicetree.cb b/src/mainboard/system76/galp5/devicetree.cb index b0fa524..aabeedb 100644 --- a/src/mainboard/system76/galp5/devicetree.cb +++ b/src/mainboard/system76/galp5/devicetree.cb @@ -333,9 +333,7 @@ device ref hda on register "PchHdaAudioLinkHdaEnable" = "1" end - device ref smbus on - register "SmbusEnable" = "1" - end + device ref smbus on end device ref fast_spi on end end end diff --git a/src/mainboard/system76/gaze16/devicetree.cb b/src/mainboard/system76/gaze16/devicetree.cb index 380bdc0..f5f216c 100644 --- a/src/mainboard/system76/gaze16/devicetree.cb +++ b/src/mainboard/system76/gaze16/devicetree.cb @@ -145,9 +145,7 @@ device ref hda on register "PchHdaAudioLinkHdaEnable" = "1" end - device ref smbus on - register "SmbusEnable" = "1" - end + device ref smbus on end device ref fast_spi on end end end diff --git a/src/mainboard/system76/lemp10/devicetree.cb b/src/mainboard/system76/lemp10/devicetree.cb index 5c702b9..2c03e60 100644 --- a/src/mainboard/system76/lemp10/devicetree.cb +++ b/src/mainboard/system76/lemp10/devicetree.cb @@ -294,9 +294,7 @@ device ref hda on register "PchHdaAudioLinkHdaEnable" = "1" end - device ref smbus on - register "SmbusEnable" = "1" - end + device ref smbus on end device ref fast_spi on end end end diff --git a/src/mainboard/system76/oryp8/devicetree.cb b/src/mainboard/system76/oryp8/devicetree.cb index 429ad62..4263806 100644 --- a/src/mainboard/system76/oryp8/devicetree.cb +++ b/src/mainboard/system76/oryp8/devicetree.cb @@ -212,7 +212,6 @@ register "PchHdaAudioLinkHdaEnable" = "1" end device ref smbus on - register "SmbusEnable" = "1" chip drivers/i2c/tas5825m register "id" = "0" device i2c 4e on end # (8bit address: 0x9c) diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index f0858db..e729e8c 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -272,9 +272,6 @@ /* PCIE RP Advanced Error Report: Enable (1) / Disable (0) */ uint8_t PcieRpAdvancedErrorReporting[CONFIG_MAX_ROOT_PORTS]; - /* SMBus */ - uint8_t SmbusEnable; - /* Gfx related */ uint8_t SkipExtGfxScan; diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c index 40683e2..24b8575 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -130,7 +130,7 @@ /* Channel Hash Mask:0x0001=BIT6 set(Minimal), 0x3FFF=BIT[19:6] set(Maximum) */ m_cfg->ChHashMask = 0x30CC; /* Enable SMBus controller based on config */ - m_cfg->SmbusEnable = config->SmbusEnable; + m_cfg->SmbusEnable = is_devfn_enabled(PCH_DEVFN_SMBUS); /* Set debug probe type */ m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_TIGERLAKE_DEBUG_CONSENT; -- To view, visit https://review.coreboot.org/c/coreboot/+/59883 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0789af20beb147fc1a6a7d046cdcea15cb44ce4c Gerrit-Change-Number: 59883 Gerrit-PatchSet: 10 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/tigerlake: Hook up DPTF device to devicetree
by Felix Singer (Code Review) 09 Dec '21

09 Dec '21

Attention is currently required from: Felix Singer, Jeremy Soller, Nick Vaccaro, Patrick Rudolph. Hello build bot (Jenkins), Tim Crawford, Jeremy Soller, Tim Wawrzynczak, Sumeet R Pawnikar, Nick Vaccaro, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59886 to look at the new patch set (#6). Change subject: soc/intel/tigerlake: Hook up DPTF device to devicetree ...................................................................... soc/intel/tigerlake: Hook up DPTF device to devicetree Hook up `Device4Enable` FSP setting to devicetree state and drop its redundant devicetree setting `Device4Enable`. The following mainboards enable the DPTF device in the devicetree despite `Device4Enable` is not being set. * google/deltaur Thus, set it to off to keep the current state unchanged. Change-Id: Ic7636fc4f63d4beab92e742a6882ac55af2565bc Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/google/deltaur/variants/baseboard/devicetree.cb M src/mainboard/google/volteer/variants/baseboard/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb M src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb M src/mainboard/system76/darp7/devicetree.cb M src/mainboard/system76/galp5/devicetree.cb M src/mainboard/system76/gaze16/devicetree.cb M src/mainboard/system76/lemp10/devicetree.cb M src/mainboard/system76/oryp8/devicetree.cb M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/fsp_params.c 12 files changed, 8 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/59886/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/59886 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic7636fc4f63d4beab92e742a6882ac55af2565bc Gerrit-Change-Number: 59886 Gerrit-PatchSet: 6 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: cbfstool: Do host space address conversion earlier when adding files
by Julius Werner (Code Review) 09 Dec '21

09 Dec '21

Attention is currently required from: Raul Rangel, Patrick Georgi, Tim Wawrzynczak. Hello Raul Rangel, Patrick Georgi, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60018 to look at the new patch set (#2). Change subject: cbfstool: Do host space address conversion earlier when adding files ...................................................................... cbfstool: Do host space address conversion earlier when adding files A simple code simplification where we can pull the call to convert_addr_space() in cbfs_add_component() earlier, so that we can avoid having to duplicate it in cbfstool_convert_fsp(). Host space addresses in this function can only occur if the user manually provided them via the --base-address flag -- all other functions (e.g. do_cbfs_locate()) already work in the flash address space anyway. This should also fix a tiny issue where --gen-attribute might have previously encoded the address as given in CBFS -- it probably makes more sense to always have it store a consistent format (i.e. always flash address). Also revert the unnecessary check for --base-address in add_topswap_bootblock(). On closer inspection, the function actually doesn't use the passed in *offset at all and uses it purely as an out-parameter. So while our current Makefile does pass --base-address when adding the bootblock, it actually has no effect and is redundant for the topswap case. Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: Idf4721c5b0700789ddb81c1618d740b3e7f486cb --- M util/cbfstool/cbfstool.c 1 file changed, 9 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/60018/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60018 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf4721c5b0700789ddb81c1618d740b3e7f486cb Gerrit-Change-Number: 60018 Gerrit-PatchSet: 2 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: cbfstool: Do host space address conversion earlier when adding files
by Julius Werner (Code Review) 09 Dec '21

09 Dec '21

Attention is currently required from: Patrick Georgi. Hello Patrick Georgi, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/60018 to review the following change. Change subject: cbfstool: Do host space address conversion earlier when adding files ...................................................................... cbfstool: Do host space address conversion earlier when adding files A simple code simplification where we can pull the call to convert_addr_space() in cbfs_add_component() earlier, so that we can avoid having to duplicate it in cbfstool_convert_fsp(). Host space addresses in this function can only occur if the user manually provided them via the --base-address flag -- all other functions (e.g. do_cbfs_locate()) already work in the flash address space anyway. This should also fix a tiny issue where --gen-attribute might have previously encoded the address as given in CBFS -- it probably makes more sense to always have it store a consistent format (i.e. always flash address). Also revert the unnecessary check for --base-address in add_topswap_bootblock(). On closer inspection, the function actually doesn't use the passed in *offset at all and uses it purely as an out-parameter. So while our current Makefile does pass --base-address when adding the bootblock, it actually has no effect and is redundant for the topswap case. Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: Idf4721c5b0700789ddb81c1618d740b3e7f486cb --- M util/cbfstool/cbfstool.c 1 file changed, 10 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/60018/1 diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index 87dcbb4..0f1bc9e 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -779,11 +779,6 @@ { size_t bb_buf_size = buffer_size(buffer); - if (!param.baseaddress_assigned) { - ERROR("--topswap-size must also have --base-address\n"); - return 1; - } - if (bb_buf_size > param.topswap_size) { ERROR("Bootblock bigger than the topswap boundary\n"); ERROR("size = %zd, ts = %d\n", bb_buf_size, @@ -841,6 +836,7 @@ uint32_t offset = param.baseaddress_assigned ? param.baseaddress : 0; size_t len_align = 0; + if (param.alignment && param.baseaddress_assigned) { ERROR("Cannot specify both alignment and base address\n"); return 1; @@ -909,6 +905,10 @@ if (add_topswap_bootblock(&buffer, &offset)) goto error; + /* With --base-address we allow host space addresses -- if so, convert it here. */ + if (IS_HOST_SPACE_ADDRESS(offset)) + offset = convert_addr_space(param.image_region, offset); + if (convert && convert(&buffer, &offset, header) != 0) { ERROR("Failed to parse file '%s'.\n", filename); goto error; @@ -975,9 +975,6 @@ goto error; } - if (IS_HOST_SPACE_ADDRESS(offset)) - offset = convert_addr_space(param.image_region, offset); - if (cbfs_add_entry(&image, &buffer, offset, header, len_align) != 0) { ERROR("Failed to add '%s' into ROM image.\n", filename); goto error; @@ -1079,10 +1076,7 @@ if (do_cbfs_locate(offset, 0)) return -1; } - if (!IS_HOST_SPACE_ADDRESS(*offset)) - address = convert_addr_space(param.image_region, *offset); - else - address = *offset; + address = *offset; } else { if (param.baseaddress_assigned == 0) { INFO("Honoring pre-linked FSP module, no relocation.\n"); @@ -1143,16 +1137,10 @@ return -1; if (param.stage_xip) { - /* - * Ensure the address is a memory mapped one. This assumes - * x86 semantics about the boot media being directly mapped - * below 4GiB in the CPU address space. - **/ - *offset = convert_addr_space(param.image_region, *offset); - - ret = parse_elf_to_xip_stage(buffer, &output, *offset, - param.ignore_section, - stageheader); + uint32_t host_space_address = convert_addr_space(param.image_region, *offset); + assert(IS_HOST_SPACE_ADDRESS(host_space_address)); + ret = parse_elf_to_xip_stage(buffer, &output, host_space_address, + param.ignore_section, stageheader); } else { ret = parse_elf_to_stage(buffer, &output, param.ignore_section, stageheader); -- To view, visit https://review.coreboot.org/c/coreboot/+/60018 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf4721c5b0700789ddb81c1618d740b3e7f486cb Gerrit-Change-Number: 60018 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/alderlake: Implement function to map physical port to EC port
by Tim Wawrzynczak (Code Review) 09 Dec '21

09 Dec '21

Attention is currently required from: Maulik V Vaghela, Subrata Banik, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59666 ) Change subject: soc/intel/alderlake: Implement function to map physical port to EC port ...................................................................... Patch Set 15: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59666 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3735b7c7794b46123aba3beac8c0268ce72d658c Gerrit-Change-Number: 59666 Gerrit-PatchSet: 15 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 09 Dec 2021 21:13:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/usb4/retimer: Add function to correct EC port mapping
by Tim Wawrzynczak (Code Review) 09 Dec '21

09 Dec '21

Attention is currently required from: Maulik V Vaghela, Sugnan Prabhu S, Subrata Banik, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59665 ) Change subject: drivers/intel/usb4/retimer: Add function to correct EC port mapping ...................................................................... Patch Set 10: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59665 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia7a5e63838e6529196bd211516e4d665b084f79e Gerrit-Change-Number: 59665 Gerrit-PatchSet: 10 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 09 Dec 2021 21:13:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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