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I'd like you to reexamine a change. Please visit
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Change subject: drivers/generic/bayhub_lv2: Work around known errata
......................................................................
drivers/generic/bayhub_lv2: Work around known errata
The Bayhub LV2 has a known errata wherein PCI config registers at
offsets 0x234, 0x238, and 0x24C will only correctly accept writes
when they are addressed via a DWORD (32-bit) wide write operation
on the PCIe bus. Offset 0x234 is the LTR max snoop and max no-snoop
latency register, therefore add a finalize callback to this driver
which will program the LTR max-snoop/no-snoop register with a 32-bit
write using the values from pciexp_get_ltr_max_latencies().
BUG=b:204343849
TEST=verified the PCI config space writes took effect on google/taeko
Change-Id: I1813f798faa534fb212cb1a074bc7bcadd17a517
Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
---
M src/drivers/generic/bayhub_lv2/lv2.c
1 file changed, 22 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/60016/3
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Change subject: mb/google/brya/var/vell: update overridetree
......................................................................
Patch Set 15:
(1 comment)
File src/mainboard/google/brya/variants/vell/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/59304/comment/8eaff704_13b0ed01
PS10, Line 146: 0
3
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Change subject: mb/google/brya/var/primus: Configure Acoustic noise mitigation
......................................................................
Patch Set 1: Code-Review+2
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/60071/comment/bd4ad165_f0d37c0f
PS1, Line 7: primus
Sometimes we use shell-like glob sequences to indicate we are modifying more than one board, in this case:
`mb/google/brya/var/primus{4es}`
shows you are modifying both
https://review.coreboot.org/c/coreboot/+/60071/comment/76e141e6_daff82d6
PS1, Line 8:
Maybe mention that this was verified to meet the audible noise specification (or is still in testing) ?
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Change subject: soc/intel/common/cse: Update help text for CSE_OEMP_FILE
......................................................................
Patch Set 3: Code-Review+2
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Hello Raul Rangel, Patrick Georgi,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/60085
to review the following change.
Change subject: cbfstool: Clean up remnants of locate action
......................................................................
cbfstool: Clean up remnants of locate action
`cbfstool locate` and the associated -T switch were removed a looong
time ago (2015 in CB:11671). However, getopt and the help text weren't
cleaned up correctly. Fix that.
Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Change-Id: Ib098278d68df65d348528fbfd2496b5737ca6246
---
M util/cbfstool/cbfstool.c
1 file changed, 1 insertion(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/60085/1
diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c
index a84601e..608cd32 100644
--- a/util/cbfstool/cbfstool.c
+++ b/util/cbfstool/cbfstool.c
@@ -1771,7 +1771,6 @@
{"pow2page", no_argument, 0, 'Q' },
{"ucode-region", required_argument, 0, 'q' },
{"size", required_argument, 0, 's' },
- {"top-aligned", required_argument, 0, 'T' },
{"type", required_argument, 0, 't' },
{"verbose", no_argument, 0, 'v' },
{"with-readonly", no_argument, 0, 'w' },
@@ -1927,9 +1926,6 @@
"Create a legacy ROM file with CBFS master header*\n"
" create -M flashmap [-r list,of,regions,containing,cbfses] "
"Create a new-style partitioned firmware image\n"
- " locate [-r image,regions] -f FILE -n NAME [-P page-size] \\\n"
- " [-a align] [-T] "
- "Find a place for a file of that size\n"
" layout [-w] "
"List mutable (or, with -w, readable) image regions\n"
" print [-r image,regions] [-k] "
@@ -1964,8 +1960,7 @@
" specifying the location of this FMAP itself and a '%s'\n"
" section describing the primary CBFS. It should also be noted\n"
" that, when working with such images, the -F and -r switches\n"
- " default to '%s' for convenience, and both the -b switch to\n"
- " CBFS operations and the output of the locate action become\n"
+ " default to '%s' for convenience, and the -b switch becomes\n"
" relative to the selected CBFS region's lowest address.\n"
" The one exception to this rule is the top-aligned address,\n"
" which is always relative to the end of the entire image\n"
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Hello Raul Rangel, Patrick Georgi,
I'd like you to do a code review. Please visit
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to review the following change.
Change subject: cbfstool: Use converted buffer size for do_cbfs_locate()
......................................................................
cbfstool: Use converted buffer size for do_cbfs_locate()
The whole point of moving do_cbfs_locate() later (CB:59877) was that it
could use the file size that is actually going to be inserted into CBFS,
rather than the on-disk file size. Unfortunately, after all that work I
forgot to actually make it do that. This patch fixes that.
Since there is no more use case for do_cbfs_locate() having to figure
out the file size on its own, and that generally seems to be a bad idea
(as the original issue shows), also remove that part of it completely
and make the data_size parameter mandatory.
Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Change-Id: I1af35e8e388f78aae3593c029afcfb4e510d2b8f
---
M util/cbfstool/cbfstool.c
1 file changed, 6 insertions(+), 18 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/60084/1
diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c
index 77460d1..a84601e 100644
--- a/util/cbfstool/cbfstool.c
+++ b/util/cbfstool/cbfstool.c
@@ -511,11 +511,6 @@
{
uint32_t metadata_size = 0;
- if (!param.filename) {
- ERROR("You need to specify -f/--filename.\n");
- return 1;
- }
-
if (!param.name) {
ERROR("You need to specify -n/--name.\n");
return 1;
@@ -530,17 +525,10 @@
WARN("'%s' already in CBFS.\n", param.name);
if (!data_size) {
- struct buffer buffer;
- if (buffer_from_file(&buffer, param.filename) != 0) {
- ERROR("Cannot load %s.\n", param.filename);
- return 1;
- }
- data_size = buffer.size;
- buffer_delete(&buffer);
+ ERROR("File '%s' is empty?\n", param.name);
+ return 1;
}
- DEBUG("File size is %zd (0x%zx)\n", data_size, data_size);
-
/* Compute required page size */
if (param.force_pow2_pagesize) {
param.pagesize = 1;
@@ -571,8 +559,8 @@
param.alignment, metadata_size);
if (address < 0) {
- ERROR("'%s' can't fit in CBFS for page-size %#x, align %#x.\n",
- param.name, param.pagesize, param.alignment);
+ ERROR("'%s'(%u + %zu) can't fit in CBFS for page-size %#x, align %#x.\n",
+ param.name, metadata_size, data_size, param.pagesize, param.alignment);
return 1;
}
@@ -917,7 +905,7 @@
/* This needs to run after convert() to take compression into account. */
if (!offset && param.alignment)
- if (do_cbfs_locate(&offset, 0))
+ if (do_cbfs_locate(&offset, buffer_size(&buffer)))
goto error;
/* This needs to run after convert() to hash the actual final file data. */
@@ -1076,7 +1064,7 @@
if (param.stage_xip) {
if (!param.baseaddress_assigned) {
param.alignment = 4*1024;
- if (do_cbfs_locate(offset, 0))
+ if (do_cbfs_locate(offset, buffer_size(buffer)))
return -1;
}
assert(!IS_HOST_SPACE_ADDRESS(*offset));
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Change subject: mb/google/guybrush: Set TPM to to be kernel power managed.
......................................................................
Patch Set 4:
(1 comment)
File src/mainboard/google/guybrush/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/60081/comment/53d7bdb6_7b6503c7
PS4, Line 346: KERNEL_POWER
> Is it FW_POWER_MANAGED?
When PSP_S0I3_RESUME_VERSTAGE is running it needs to be kernel managed to cause the shutdown command to be sent, this is skipped in firmware power managed case. See https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/thi…
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Change subject: amdfwtool: Use relative address for EFS gen2
......................................................................
Patch Set 24: Code-Review+2
(1 comment)
Patchset:
PS24:
Sorry to keep the CL waiting.
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Change subject: mb/google/guybrush: Set TPM to to be kernel power managed.
......................................................................
Patch Set 4:
(1 comment)
File src/mainboard/google/guybrush/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/60081/comment/c8feaf84_574306e1
PS4, Line 346: KERNEL_POWER
Is it FW_POWER_MANAGED?
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