coreboot-gerrit November 2021

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Change in coreboot[master]: util/cbfstool/flashmap/fmap.c: fix fmaptool endianness bugs on BE
by Sergii Dmytruk (Code Review) 21 Nov '21

21 Nov '21

Sergii Dmytruk has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/57073 ) Change subject: util/cbfstool/flashmap/fmap.c: fix fmaptool endianness bugs on BE ...................................................................... Abandoned Another commit duplicated uploaded with a different Change-Id. -- To view, visit https://review.coreboot.org/c/coreboot/+/57073 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id49843a10aae5586688140fc746e77e47a04a1e3 Gerrit-Change-Number: 57073 Gerrit-PatchSet: 1 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: ec/starlabs: Add standardised ITE EC support
by Andy Pont (Code Review) 21 Nov '21

21 Nov '21

Attention is currently required from: Sean Rhodes, Felix Held. Andy Pont has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58343 ) Change subject: ec/starlabs: Add standardised ITE EC support ...................................................................... Patch Set 57: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/58343 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8023c26de23c874c84106fda96e64dcfa0c5ba32 Gerrit-Change-Number: 58343 Gerrit-PatchSet: 57 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sun, 21 Nov 2021 08:47:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/{adl,ehl,jsl,tgl}: Remove unused header `thermal.h`
by EricR Lai (Code Review) 20 Nov '21

20 Nov '21

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Subrata Banik, Angel Pons, Patrick Rudolph. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59510 ) Change subject: soc/intel/{adl,ehl,jsl,tgl}: Remove unused header `thermal.h` ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59510 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9ac0ffb352686af22cc9d11b61f904238eef278 Gerrit-Change-Number: 59510 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sun, 21 Nov 2021 02:18:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/thermal: Refactor thermal block to improve reusability
by EricR Lai (Code Review) 20 Nov '21

20 Nov '21

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Subrata Banik, Angel Pons, Patrick Rudolph. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59509 ) Change subject: soc/intel/common/thermal: Refactor thermal block to improve reusability ...................................................................... Patch Set 4: Code-Review+1 (1 comment) Patchset: PS4: Great! -- To view, visit https://review.coreboot.org/c/coreboot/+/59509 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I14df5145629ef03f358b98e824bca6a5b8ebdfc6 Gerrit-Change-Number: 59509 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sun, 21 Nov 2021 02:15:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/thermal: Allow thermal configuration over PMC
by Subrata Banik (Code Review) 20 Nov '21

20 Nov '21

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59209 ) Change subject: soc/intel/common/thermal: Allow thermal configuration over PMC ...................................................................... Patch Set 14: (1 comment) File src/soc/intel/common/block/thermal/thermal_pmc.c: https://review.coreboot.org/c/coreboot/+/59209/comment/6ed21ed0_ceee6f75 PS13, Line 21: static uint8_t get_thermal_trip_temp(void) > Done @Eric: CB:59509 CL is here for review -- To view, visit https://review.coreboot.org/c/coreboot/+/59209 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c6ae72610da39fc18ff252c440d006e83c570a0 Gerrit-Change-Number: 59209 Gerrit-PatchSet: 14 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Sat, 20 Nov 2021 21:09:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Comment-In-Reply-To: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/{adl,ehl,jsl,tgl}: Remove unused header `thermal.h`
by Subrata Banik (Code Review) 20 Nov '21

20 Nov '21

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59510 ) Change subject: soc/intel/{adl,ehl,jsl,tgl}: Remove unused header `thermal.h` ...................................................................... soc/intel/{adl,ehl,jsl,tgl}: Remove unused header `thermal.h` This patch removes unused header inclusion as <intelblocks/thermal.h> from several SoC finalize.c files. Change-Id: Ic9ac0ffb352686af22cc9d11b61f904238eef278 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/alderlake/finalize.c M src/soc/intel/elkhartlake/finalize.c M src/soc/intel/jasperlake/finalize.c M src/soc/intel/tigerlake/finalize.c 4 files changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/59510/1 diff --git a/src/soc/intel/alderlake/finalize.c b/src/soc/intel/alderlake/finalize.c index aa136d4..589ea59 100644 --- a/src/soc/intel/alderlake/finalize.c +++ b/src/soc/intel/alderlake/finalize.c @@ -19,7 +19,6 @@ #include <intelblocks/pmclib.h> #include <intelblocks/systemagent.h> #include <intelblocks/tco.h> -#include <intelblocks/thermal.h> #include <intelpch/lockdown.h> #include <soc/p2sb.h> #include <soc/pci_devs.h> diff --git a/src/soc/intel/elkhartlake/finalize.c b/src/soc/intel/elkhartlake/finalize.c index d415a1d..ba1b2c4 100644 --- a/src/soc/intel/elkhartlake/finalize.c +++ b/src/soc/intel/elkhartlake/finalize.c @@ -11,7 +11,6 @@ #include <intelblocks/pmclib.h> #include <intelblocks/systemagent.h> #include <intelblocks/tco.h> -#include <intelblocks/thermal.h> #include <intelpch/lockdown.h> #include <soc/p2sb.h> #include <soc/pci_devs.h> diff --git a/src/soc/intel/jasperlake/finalize.c b/src/soc/intel/jasperlake/finalize.c index 40b5294..a3d4328 100644 --- a/src/soc/intel/jasperlake/finalize.c +++ b/src/soc/intel/jasperlake/finalize.c @@ -11,7 +11,6 @@ #include <intelblocks/pmclib.h> #include <intelblocks/systemagent.h> #include <intelblocks/tco.h> -#include <intelblocks/thermal.h> #include <intelpch/lockdown.h> #include <soc/p2sb.h> #include <soc/pci_devs.h> diff --git a/src/soc/intel/tigerlake/finalize.c b/src/soc/intel/tigerlake/finalize.c index 3bbd002..b50529b 100644 --- a/src/soc/intel/tigerlake/finalize.c +++ b/src/soc/intel/tigerlake/finalize.c @@ -17,7 +17,6 @@ #include <intelblocks/pmclib.h> #include <intelblocks/systemagent.h> #include <intelblocks/tco.h> -#include <intelblocks/thermal.h> #include <intelpch/lockdown.h> #include <soc/p2sb.h> #include <soc/pci_devs.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/59510 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9ac0ffb352686af22cc9d11b61f904238eef278 Gerrit-Change-Number: 59510 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/thermal: Refactor thermal block to improve reusability
by Subrata Banik (Code Review) 20 Nov '21

20 Nov '21

Attention is currently required from: Patrick Rudolph. Hello Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59509 to look at the new patch set (#3). Change subject: soc/intel/common/thermal: Refactor thermal block to improve reusability ...................................................................... soc/intel/common/thermal: Refactor thermal block to improve reusability This patch moves common thermal API between chipsets with thermal device as PCI device and thermal device behind PMC into common file (thermal_common.c). Introduce CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV to let SoC Kconfig to select as applicable for underlying chipset. +------------------------------------------------------+--------------+ | Thermal Kconfig | SoC | +------------------------------------------------------+--------------+ | CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV | SKL/KBL, CNL | | | till ICL | +------------------------------------------------------+--------------+ | CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC | TGL onwards | | | ICL | +------------------------------------------------------+--------------+ Either of these two Kconfig internally selects CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL to use common thermal APIs. BUG=b:193774296 TEST=Able to build and boot hatch and adlrvp platform. Change-Id: I14df5145629ef03f358b98e824bca6a5b8ebdfc6 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/common/block/include/intelblocks/thermal.h M src/soc/intel/common/block/thermal/Kconfig M src/soc/intel/common/block/thermal/Makefile.inc D src/soc/intel/common/block/thermal/thermal.c A src/soc/intel/common/block/thermal/thermal_common.c A src/soc/intel/common/block/thermal/thermal_pci.c M src/soc/intel/common/block/thermal/thermal_pmc.c M src/soc/intel/icelake/Kconfig M src/soc/intel/skylake/Kconfig 10 files changed, 108 insertions(+), 110 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/59509/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/59509 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I14df5145629ef03f358b98e824bca6a5b8ebdfc6 Gerrit-Change-Number: 59509 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/thermal: Refactor thermal block to improve reusability
by Subrata Banik (Code Review) 20 Nov '21

20 Nov '21

Attention is currently required from: Patrick Rudolph. Hello Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59509 to look at the new patch set (#2). Change subject: soc/intel/common/thermal: Refactor thermal block to improve reusability ...................................................................... soc/intel/common/thermal: Refactor thermal block to improve reusability This patch moves common thermal API between chipsets with thermal device as PCI device and thermal device behind PMC into common file (thermal_common.c). Introduce CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV to let SoC Kconfig to select as applicable for underlying chipset. +------------------------------------------------------+--------------+ | Thermal Kconfig | SoC | +------------------------------------------------------+--------------+ | CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV | SKL/KBL, CNL | | | till ICL | +------------------------------------------------------+--------------+ | CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC | TGL onwards | | | ICL | +------------------------------------------------------+--------------+ Either of these two Kconfig internally selects CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL to use common thermal APIs. BUG=b:193774296 TEST=Able to build and boot hatch and adlrvp platform. Change-Id: I14df5145629ef03f358b98e824bca6a5b8ebdfc6 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/common/block/include/intelblocks/thermal.h M src/soc/intel/common/block/thermal/Kconfig M src/soc/intel/common/block/thermal/Makefile.inc D src/soc/intel/common/block/thermal/thermal.c A src/soc/intel/common/block/thermal/thermal_common.c A src/soc/intel/common/block/thermal/thermal_pci.c M src/soc/intel/common/block/thermal/thermal_pmc.c M src/soc/intel/icelake/Kconfig M src/soc/intel/skylake/Kconfig 10 files changed, 107 insertions(+), 110 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/59509/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59509 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I14df5145629ef03f358b98e824bca6a5b8ebdfc6 Gerrit-Change-Number: 59509 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/thermal: Refactor thermal block to improve reusability
by Subrata Banik (Code Review) 20 Nov '21

20 Nov '21

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59509 ) Change subject: soc/intel/common/thermal: Refactor thermal block to improve reusability ...................................................................... soc/intel/common/thermal: Refactor thermal block to improve reusability This patch moves common thermal API between chipsets with thermal device as PCI device and thermal device behind PMC into common file (thermal_common.c). Introduce CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV to let SoC Kconfig to select as applicable for underlying chipset. +------------------------------------------------------+--------------+ | Thermal Kconfig | SoC | +------------------------------------------------------+--------------+ | CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV | SKL/KBL, CNL | | | till ICL | +------------------------------------------------------+--------------+ | CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC | TGL onwards | | | ICL | +------------------------------------------------------+--------------+ Either of these two Kconfig internally selects CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL to use common thermal APIs. BUG=b:193774296 TEST=Able to build and boot hatch and adlrvp platform. Change-Id: I14df5145629ef03f358b98e824bca6a5b8ebdfc6 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/common/block/include/intelblocks/thermal.h M src/soc/intel/common/block/thermal/Kconfig M src/soc/intel/common/block/thermal/Makefile.inc D src/soc/intel/common/block/thermal/thermal.c A src/soc/intel/common/block/thermal/thermal_common.c A src/soc/intel/common/block/thermal/thermal_pci.c M src/soc/intel/common/block/thermal/thermal_pmc.c M src/soc/intel/icelake/Kconfig M src/soc/intel/skylake/Kconfig 10 files changed, 107 insertions(+), 110 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/59509/1 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index ed0f5a3..8fed9e9 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -94,7 +94,7 @@ select SOC_INTEL_COMMON_BLOCK_SCS select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP - select SOC_INTEL_COMMON_BLOCK_THERMAL + select SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV select SOC_INTEL_COMMON_BLOCK_XHCI select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG select SOC_INTEL_COMMON_FSP_RESET diff --git a/src/soc/intel/common/block/include/intelblocks/thermal.h b/src/soc/intel/common/block/include/intelblocks/thermal.h index aa3318c..4f5cd62 100644 --- a/src/soc/intel/common/block/include/intelblocks/thermal.h +++ b/src/soc/intel/common/block/include/intelblocks/thermal.h @@ -3,6 +3,25 @@ #ifndef _SOC_INTEL_COMMON_BLOCK_THERMAL_H_ #define _SOC_INTEL_COMMON_BLOCK_THERMAL_H_ +#define MAX_TRIP_TEMP 205 +/* This is the safest default Trip Temp value */ +#define DEFAULT_TRIP_TEMP 50 + +#if CONFIG(SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV) + /* Trip Point Temp = (LTT / 2 - 50 degree C) */ + #define GET_LTT_VALUE(x) (((x) + 50) * (2)) +#elif CONFIG(SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC) + /* + * Trip Point = T2L | T1L | T0L where T2L > T1L > T0L + * T2L = Bit 28:20 + * T1L = Bit 18:10 + * T0L = Bit 8:0 + */ + #define GET_LTT_VALUE(x) ((x + 10) << 20 | (x + 5) << 10 | x) +#else + #error <Undefined: GET_LTT_VALUE macro> +#endif + /* Catastrophic Trip Point Enable */ #define PMC_PWRM_THERMAL_CTEN 0x150c /* Policy Lock-Down Bit */ @@ -30,6 +49,10 @@ /* PHL Lock */ #define PMC_PWRM_THERMAL_PHLC_PHLCLOCK (1 << 31) +/* Get PCH Thermal Trip from common chip config */ +uint8_t get_thermal_trip_temp(void); +/* PCH Low Temp Threshold (LTT) */ +uint32_t pch_get_ltt_value(void); /* Enable thermal sensor power management */ void pch_thermal_configuration(void); diff --git a/src/soc/intel/common/block/thermal/Kconfig b/src/soc/intel/common/block/thermal/Kconfig index b39c74c..c29ecb5 100644 --- a/src/soc/intel/common/block/thermal/Kconfig +++ b/src/soc/intel/common/block/thermal/Kconfig @@ -4,9 +4,18 @@ help This option allows to configure PCH thermal registers for supported PCH. +config SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV + bool + default n + select SOC_INTEL_COMMON_BLOCK_THERMAL + help + This option allows to configure PCH thermal registers using Thermal PCI device + for chipsets till Ice Lake PCH. + config SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC bool default n + select SOC_INTEL_COMMON_BLOCK_THERMAL help This option allows to configure PCH thermal registers using PMC PWRMBASE for chipsets since Tiger Lake PCH. diff --git a/src/soc/intel/common/block/thermal/Makefile.inc b/src/soc/intel/common/block/thermal/Makefile.inc index 2a65219..cd71032 100644 --- a/src/soc/intel/common/block/thermal/Makefile.inc +++ b/src/soc/intel/common/block/thermal/Makefile.inc @@ -1,3 +1,5 @@ -romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL) += thermal.c +romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL) += thermal_common.c +romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV) += thermal_pci.c romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC) += thermal_pmc.c -ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL) += thermal.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL) += thermal_common.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV) += thermal_pci.c diff --git a/src/soc/intel/common/block/thermal/thermal.c b/src/soc/intel/common/block/thermal/thermal.c deleted file mode 100644 index 6106c49..0000000 --- a/src/soc/intel/common/block/thermal/thermal.c +++ /dev/null @@ -1,68 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <console/console.h> -#include <device/mmio.h> -#include <intelblocks/cfg.h> -#include <intelblocks/thermal.h> -#include <soc/pci_devs.h> - -#define THERMAL_SENSOR_POWER_MANAGEMENT 0x1c -#define CATASTROPHIC_TRIP_POINT_MASK 0x1ff -#define MAX_TRIP_TEMP 205 -/* This is the safest default Trip Temp value */ -#define DEFAULT_TRIP_TEMP 50 -/* Trip Point Temp = (LTT / 2 - 50 degree C) */ -#define GET_LTT_VALUE(x) (((x) + 50) * (2)) - -static uint8_t get_thermal_trip_temp(void) -{ - const struct soc_intel_common_config *common_config; - common_config = chip_get_common_soc_structure(); - - return common_config->pch_thermal_trip; -} - -/* PCH Low Temp Threshold (LTT) */ -static uint32_t pch_get_ltt_value(void) -{ - uint8_t thermal_config; - - thermal_config = get_thermal_trip_temp(); - if (!thermal_config) - thermal_config = DEFAULT_TRIP_TEMP; - - if (thermal_config > MAX_TRIP_TEMP) - die("Input PCH temp trip is higher than allowed range!"); - - return GET_LTT_VALUE(thermal_config); -} - -/* Enable thermal sensor power management */ -void pch_thermal_configuration(void) -{ - uintptr_t thermalbar; - uintptr_t thermalbar_pm; - const struct device *dev; - struct resource *res; - - dev = pcidev_path_on_root(PCH_DEVFN_THERMAL); - if (!dev) { - printk(BIOS_ERR, "ERROR: PCH_DEVFN_THERMAL device not found!\n"); - return; - } - - res = probe_resource(dev, PCI_BASE_ADDRESS_0); - if (!res) { - printk(BIOS_ERR, "ERROR: PCH thermal device not found!\n"); - return; - } - - /* Get the base address of the resource */ - thermalbar = res->base; - - /* Get the required thermal address to write the register value */ - thermalbar_pm = thermalbar + THERMAL_SENSOR_POWER_MANAGEMENT; - - /* Set Low Temp Threshold (LTT) at TSPM offset 0x1c[8:0] */ - clrsetbits32((void *)thermalbar_pm, CATASTROPHIC_TRIP_POINT_MASK, pch_get_ltt_value()); -} diff --git a/src/soc/intel/common/block/thermal/thermal_common.c b/src/soc/intel/common/block/thermal/thermal_common.c new file mode 100644 index 0000000..ba1ab06 --- /dev/null +++ b/src/soc/intel/common/block/thermal/thermal_common.c @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <intelblocks/cfg.h> +#include <intelblocks/thermal.h> + +/* Get PCH Thermal Trip from common chip config */ +uint8_t get_thermal_trip_temp(void) +{ + const struct soc_intel_common_config *common_config; + common_config = chip_get_common_soc_structure(); + + return common_config->pch_thermal_trip; +} + +/* PCH Low Temp Threshold (LTT) */ +uint32_t pch_get_ltt_value(void) +{ + uint8_t thermal_config; + + thermal_config = get_thermal_trip_temp(); + if (!thermal_config) + thermal_config = DEFAULT_TRIP_TEMP; + + if (thermal_config > MAX_TRIP_TEMP) + die("Input PCH temp trip is higher than allowed range!"); + + return GET_LTT_VALUE(thermal_config); +} diff --git a/src/soc/intel/common/block/thermal/thermal_pci.c b/src/soc/intel/common/block/thermal/thermal_pci.c new file mode 100644 index 0000000..33f394b --- /dev/null +++ b/src/soc/intel/common/block/thermal/thermal_pci.c @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <device/mmio.h> +#include <intelblocks/thermal.h> +#include <soc/pci_devs.h> + +#define THERMAL_SENSOR_POWER_MANAGEMENT 0x1c +#define CATASTROPHIC_TRIP_POINT_MASK 0x1ff + +/* Enable thermal sensor power management */ +void pch_thermal_configuration(void) +{ + uintptr_t thermalbar; + uintptr_t thermalbar_pm; + const struct device *dev; + struct resource *res; + + dev = pcidev_path_on_root(PCH_DEVFN_THERMAL); + if (!dev) { + printk(BIOS_ERR, "ERROR: PCH_DEVFN_THERMAL device not found!\n"); + return; + } + + res = probe_resource(dev, PCI_BASE_ADDRESS_0); + if (!res) { + printk(BIOS_ERR, "ERROR: PCH thermal device not found!\n"); + return; + } + + /* Get the base address of the resource */ + thermalbar = res->base; + + /* Get the required thermal address to write the register value */ + thermalbar_pm = thermalbar + THERMAL_SENSOR_POWER_MANAGEMENT; + + /* Set Low Temp Threshold (LTT) at TSPM offset 0x1c[8:0] */ + clrsetbits32((void *)thermalbar_pm, CATASTROPHIC_TRIP_POINT_MASK, pch_get_ltt_value()); +} diff --git a/src/soc/intel/common/block/thermal/thermal_pmc.c b/src/soc/intel/common/block/thermal/thermal_pmc.c index d233e9d..3525b47 100644 --- a/src/soc/intel/common/block/thermal/thermal_pmc.c +++ b/src/soc/intel/common/block/thermal/thermal_pmc.c @@ -1,46 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <console/console.h> #include <device/mmio.h> -#include <intelblocks/cfg.h> #include <intelblocks/pmclib.h> #include <intelblocks/thermal.h> -#define MAX_TRIP_TEMP 205 -/* This is the safest default Trip Temp value */ -#define DEFAULT_TRIP_TEMP 50 - -/* - * Trip Point = T2L | T1L | T0L where T2L > T1L > T0L - * T2L = Bit 28:20 - * T1L = Bit 18:10 - * T0L = Bit 8:0 - */ -#define GET_LTT_VALUE(x) ((x + 10) << 20 | (x + 5) << 10 | x) - -static uint8_t get_thermal_trip_temp(void) -{ - const struct soc_intel_common_config *common_config; - common_config = chip_get_common_soc_structure(); - - return common_config->pch_thermal_trip; -} - -/* PCH Low Temp Threshold (LTT) */ -static uint32_t pch_get_ltt_value(void) -{ - uint8_t thermal_config; - - thermal_config = get_thermal_trip_temp(); - if (!thermal_config) - thermal_config = DEFAULT_TRIP_TEMP; - - if (thermal_config > MAX_TRIP_TEMP) - die("Input PCH temp trip is higher than allowed range!"); - - return GET_LTT_VALUE(thermal_config); -} - /* * Thermal configuration has evolved over time. With older platform the * thermal device is sitting over PCI and allow to configure its configuration diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index e99832d..999bc9d 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -50,7 +50,7 @@ select SOC_INTEL_COMMON_BLOCK_SCS select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP - select SOC_INTEL_COMMON_BLOCK_THERMAL + select SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV select SOC_INTEL_COMMON_FSP_RESET select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_RESET diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 0df1611..b90fdef 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -70,7 +70,7 @@ select SOC_INTEL_COMMON_BLOCK_SGX_LOCK_MEMORY select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP - select SOC_INTEL_COMMON_BLOCK_THERMAL + select SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV select SOC_INTEL_COMMON_BLOCK_UART select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG select SOC_INTEL_COMMON_FSP_RESET -- To view, visit https://review.coreboot.org/c/coreboot/+/59509 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I14df5145629ef03f358b98e824bca6a5b8ebdfc6 Gerrit-Change-Number: 59509 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: arch/x86: Remove spinlock dependency on threading
by Kyösti Mälkki (Code Review) 20 Nov '21

20 Nov '21

Attention is currently required from: Raul Rangel, Paul Menzel, Julius Werner, Rob Barnes, Karthik Ramasubramanian. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59322 ) Change subject: arch/x86: Remove spinlock dependency on threading ...................................................................... Patch Set 8: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59322/comment/0e8cc5e6_d27955cc PS8, Line 13: commit a98d302fe9dc ("x86/smp/spinlock: Disable thread coop when taking spinlock") IMO you should do a clean revert first, and not have printk() as a special case with spinlock, but use mutex there too. -- To view, visit https://review.coreboot.org/c/coreboot/+/59322 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I55d0cd2bcd82721098ca24ae2368bb6a16a07df4 Gerrit-Change-Number: 59322 Gerrit-PatchSet: 8 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Sat, 20 Nov 2021 18:03:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit November 2021