coreboot-gerrit November 2021

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Change in coreboot[master]: Revert commit bfb5c807e720761f4457d5106bb919f2aacb5535 binaryPI: Drop...
by Name of user not set (Code Review) 07 Aug '23

07 Aug '23

Name of user not set #1002701 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37533 ) Change subject: Revert commit bfb5c807e720761f4457d5106bb919f2aacb5535 binaryPI: Drop PSP Secure OS from build ...................................................................... Revert commit bfb5c807e720761f4457d5106bb919f2aacb5535 binaryPI: Drop PSP Secure OS from build For AMD Bettong board to boot these changes should be reverted. Change-Id: I903824019ebbe7934dbe12297b3a223cab3461c5 Signed-off-by: Jorge Fernandez <jorgefm(a)cirsa.com> --- M src/southbridge/amd/pi/hudson/Makefile.inc 1 file changed, 7 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/37533/1 diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index 0eccadb..33f59c7 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -85,10 +85,10 @@ FIRMWARE_TYPE= PSPBTLDR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspBootLoader.Bypass.sbin -#PSPRCVR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspRecovery.sbin -#PSPSCUREOS_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureOs.sbin -#PSPTRUSTLETS_FILE=$(top)/$(FIRMWARE_LOCATE)/trustlets.bin -#TRUSTLETKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/Trustlet.tkn.cert +PSPRCVR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspRecovery.sbin +PSPSCUREOS_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureOs.sbin +PSPTRUSTLETS_FILE=$(top)/$(FIRMWARE_LOCATE)/trustlets.bin +TRUSTLETKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/Trustlet.tkn.cert endif ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) @@ -103,12 +103,12 @@ SMUFIRMWARE2_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware2_prod_CZ.sbin endif -#PUBSIGNEDKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/RtmPubSigned$(FIRMWARE_TYPE).key -#PSPNVRAM_FILE=$(top)/$(FIRMWARE_LOCATE)/PspNvram$(FIRMWARE_TYPE).bin +PUBSIGNEDKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/RtmPubSigned$(FIRMWARE_TYPE).key +PSPNVRAM_FILE=$(top)/$(FIRMWARE_LOCATE)/PspNvram$(FIRMWARE_TYPE).bin SMUFWM_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware$(FIRMWARE_TYPE).sbin SMUFWM_FN_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware$(FIRMWARE_TYPE)_FN.sbin SMUSCS_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuScs$(FIRMWARE_TYPE).bin -#PSPSECUREDEBUG_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureDebug$(FIRMWARE_TYPE).Key +PSPSECUREDEBUG_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureDebug$(FIRMWARE_TYPE).Key endif -- To view, visit https://review.coreboot.org/c/coreboot/+/37533 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I903824019ebbe7934dbe12297b3a223cab3461c5 Gerrit-Change-Number: 37533 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1002701 Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Name of user not set #1002701 Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: utils/kconfig/nconf.c: Fix truncation warning in `item_add_str`
by Jude Rich (Code Review) 07 Aug '23

07 Aug '23

Jude Rich has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37939 ) Change subject: utils/kconfig/nconf.c: Fix truncation warning in `item_add_str` ...................................................................... utils/kconfig/nconf.c: Fix truncation warning in `item_add_str` While appending a string in `item_add_str`, there is a warning about truncating the string to 256 bytes due to unnecessary buffering. By removing the buffering and writing directly to the string, the warning is vanquished. Signed-off-by: Jude A Rich <juder11(a)gmail.com> Change-Id: Idb2dfad7e401954f4bb83d0409ab71dcd7277f47 --- M util/kconfig/nconf.c 1 file changed, 18 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/37939/1 diff --git a/util/kconfig/nconf.c b/util/kconfig/nconf.c index 905dcd1..4181c41 100644 --- a/util/kconfig/nconf.c +++ b/util/kconfig/nconf.c @@ -561,32 +561,33 @@ curses_menu_items[items_num] = NULL; } -/* very hackish. adds a string to the last item added */ +/* add a string to the last item added */ static void item_add_str(const char *fmt, ...) { va_list ap; - int index = items_num-1; - char new_str[256]; - char tmp_str[256]; + char *append_ptr; /* pointer to the free space in the target string */ + int index = items_num-1; /* index of item to append string */ + int kmi_str_len; /* length of initial string */ + int str_space; /* length of unused space in string */ + /* return if there's no item to work with */ if (index < 0) return; - va_start(ap, fmt); - vsnprintf(new_str, sizeof(new_str), fmt, ap); - va_end(ap); - snprintf(tmp_str, sizeof(tmp_str), "%s%s", - k_menu_items[index].str, new_str); - strncpy(k_menu_items[index].str, - tmp_str, - sizeof(k_menu_items[index].str)); + kmi_str_len = strlen(k_menu_items[index].str); + str_space = sizeof(k_menu_items[index].str) - kmi_str_len; + append_ptr = k_menu_items[index].str + kmi_str_len; + /* append the string */ + va_start(ap, fmt); + vsnprintf(append_ptr, str_space, fmt, ap); + va_end(ap); + + /* set menu item to new item string */ free_item(curses_menu_items[index]); - curses_menu_items[index] = new_item( - k_menu_items[index].str, - k_menu_items[index].str); - set_item_userptr(curses_menu_items[index], - &k_menu_items[index]); + curses_menu_items[index] = new_item(k_menu_items[index].str, + k_menu_items[index].str); + set_item_userptr(curses_menu_items[index], &k_menu_items[index]); } /* get the tag of the currently selected item */ -- To view, visit https://review.coreboot.org/c/coreboot/+/37939 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb2dfad7e401954f4bb83d0409ab71dcd7277f47 Gerrit-Change-Number: 37939 Gerrit-PatchSet: 1 Gerrit-Owner: Jude Rich <juder11(a)gmail.com> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: mainboard/asus/p10s-series: Initial port to ASUS P10S-I
by Kevin Cody-Little (Code Review) 07 Aug '23

07 Aug '23

Kevin Cody-Little has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37995 ) Change subject: mainboard/asus/p10s-series: Initial port to ASUS P10S-I ...................................................................... mainboard/asus/p10s-series: Initial port to ASUS P10S-I Adapt supermicro/x11-lga1151-series for the very similar ASUS P10S-I (and eventually P10S-M) Kaby Lake server boards. This is still very broken but boots to a serial console, and one of the onboard network ports works, so long as a known good kernel is used as the payload. Change-Id: Icd20e69f16421518143b9d80b2a0d821ec37703e Signed-off-by: Kevin Cody <kcodyjr(a)gmail.com> --- A src/mainboard/asus/p10s-series/Kconfig A src/mainboard/asus/p10s-series/Kconfig.name A src/mainboard/asus/p10s-series/Makefile.inc A src/mainboard/asus/p10s-series/acpi/ec.asl A src/mainboard/asus/p10s-series/acpi/mainboard.asl A src/mainboard/asus/p10s-series/acpi/superio.asl A src/mainboard/asus/p10s-series/acpi_tables.c A src/mainboard/asus/p10s-series/board_info.txt A src/mainboard/asus/p10s-series/bootblock.c A src/mainboard/asus/p10s-series/cmos.default A src/mainboard/asus/p10s-series/cmos.layout A src/mainboard/asus/p10s-series/devicetree.cb A src/mainboard/asus/p10s-series/dsdt.asl A src/mainboard/asus/p10s-series/include/mainboard.h A src/mainboard/asus/p10s-series/mainboard.c A src/mainboard/asus/p10s-series/ramstage.c A src/mainboard/asus/p10s-series/romstage.c A src/mainboard/asus/p10s-series/variants/p10s-i/board_info.txt A src/mainboard/asus/p10s-series/variants/p10s-i/include/variant/gpio.h A src/mainboard/asus/p10s-series/variants/p10s-i/overridetree.cb A src/mainboard/asus/p10s-series/variants/p10s-m/Makefile.inc A src/mainboard/asus/p10s-series/variants/p10s-m/board_info.txt A src/mainboard/asus/p10s-series/variants/p10s-m/include/variant/gpio.h A src/mainboard/asus/p10s-series/variants/p10s-m/mainboard.c A src/mainboard/asus/p10s-series/variants/p10s-m/overridetree.cb A src/mainboard/asus/p10s-series/vboot-ro-rwab.fmd 26 files changed, 1,452 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/37995/1 diff --git a/src/mainboard/asus/p10s-series/Kconfig b/src/mainboard/asus/p10s-series/Kconfig new file mode 100644 index 0000000..eac2272 --- /dev/null +++ b/src/mainboard/asus/p10s-series/Kconfig @@ -0,0 +1,89 @@ +config BOARD_ASUS_P10S_SERIES + def_bool n + select BOARD_ROMSIZE_KB_16384 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select SOC_INTEL_KABYLAKE + select SKYLAKE_SOC_PCH_H + select MAINBOARD_HAS_LPC_TPM + select DRIVERS_ASPEED_AST2050 + select SUPERIO_ASPEED_AST2400 + select GENERATE_SMBIOS_TABLES + select IPMI_KCS + select MAINBOARD_NO_FSP_GOP + select SUPERIO_ASPEED_HAS_UART_DELAY_WORKAROUND + select NO_FADT_8042 + +if BOARD_ASUS_P10S_SERIES + +config MAINBOARD_FAMILY + string + default "ASUS_P10S_SERIES" + +config MAINBOARD_PART_NUMBER + string + default "P10S-I" if BOARD_ASUS_P10S_I + default "P10S-M" if BOARD_ASUS_P10S_M + +config MAINBOARD_DIR + string + default "asus/p10s-series" + +config VARIANT_DIR + string + default "p10s-i" if BOARD_ASUS_P10S_I + default "p10s-m" if BOARD_ASUS_P10S_M + +config OVERRIDE_DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" + +config VBOOT + select VBOOT_NO_BOARD_SUPPORT + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + +if VBOOT + +config VBOOT_SLOTS_RW_AB + default y + +endif + +config VBOOT_VBNV_OFFSET + hex + default 0x2a + +config FMDFILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-ro-rwab.fmd" if VBOOT_SLOTS_RW_AB + +config CBFS_SIZE + hex + default 0xb00000 + +config IRQ_SLOT_COUNT + int + default 18 + +config MAX_CPUS + int + default 8 + +config CONSOLE_POST + bool + default y + +config POST_DEVICE + bool + default n + +config DIMM_SPD_SIZE + int + default 512 + +endif # BOARD_ASUS_P10S_SERIES diff --git a/src/mainboard/asus/p10s-series/Kconfig.name b/src/mainboard/asus/p10s-series/Kconfig.name new file mode 100644 index 0000000..bd696e9 --- /dev/null +++ b/src/mainboard/asus/p10s-series/Kconfig.name @@ -0,0 +1,7 @@ +config BOARD_ASUS_P10S_I + bool "P10S-I" + select BOARD_ASUS_P10S_SERIES + +#config BOARD_ASUS_P10S_M +# bool "P10S-M" +# select BOARD_ASUS_P10S_SERIES diff --git a/src/mainboard/asus/p10s-series/Makefile.inc b/src/mainboard/asus/p10s-series/Makefile.inc new file mode 100644 index 0000000..cab662a --- /dev/null +++ b/src/mainboard/asus/p10s-series/Makefile.inc @@ -0,0 +1,24 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## Copyright (C) 2016 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +bootblock-y += bootblock.c + +ramstage-y += ramstage.c + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include + +subdirs-y += variants/$(VARIANT_DIR) +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/asus/p10s-series/acpi/ec.asl b/src/mainboard/asus/p10s-series/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/asus/p10s-series/acpi/ec.asl diff --git a/src/mainboard/asus/p10s-series/acpi/mainboard.asl b/src/mainboard/asus/p10s-series/acpi/mainboard.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/asus/p10s-series/acpi/mainboard.asl diff --git a/src/mainboard/asus/p10s-series/acpi/superio.asl b/src/mainboard/asus/p10s-series/acpi/superio.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/asus/p10s-series/acpi/superio.asl diff --git a/src/mainboard/asus/p10s-series/acpi_tables.c b/src/mainboard/asus/p10s-series/acpi_tables.c new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/asus/p10s-series/acpi_tables.c diff --git a/src/mainboard/asus/p10s-series/board_info.txt b/src/mainboard/asus/p10s-series/board_info.txt new file mode 100644 index 0000000..cfa02bc --- /dev/null +++ b/src/mainboard/asus/p10s-series/board_info.txt @@ -0,0 +1,2 @@ +Category: server +Vendor name: ASUS diff --git a/src/mainboard/asus/p10s-series/bootblock.c b/src/mainboard/asus/p10s-series/bootblock.c new file mode 100644 index 0000000..75afd2e --- /dev/null +++ b/src/mainboard/asus/p10s-series/bootblock.c @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <soc/gpio.h> +#include <variant/gpio.h> +#include <superio/aspeed/common/aspeed.h> +#include <superio/aspeed/ast2400/ast2400.h> +#include <delay.h> +#include <console/uart.h> + +static void early_config_gpio(void) +{ + /* This is a hack for FSP because it does things in MemoryInit() + * which it shouldn't do. We have to prepare certain gpios here + * because of the brokenness in FSP. */ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} + +static void early_config_superio(void) +{ + const pnp_devfn_t serial_dev = PNP_DEV(0x2e, AST2400_SUART1); + aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE); +} + +void bootblock_mainboard_early_init(void) +{ + early_config_gpio(); + early_config_superio(); +} diff --git a/src/mainboard/asus/p10s-series/cmos.default b/src/mainboard/asus/p10s-series/cmos.default new file mode 100644 index 0000000..d564953 --- /dev/null +++ b/src/mainboard/asus/p10s-series/cmos.default @@ -0,0 +1,3 @@ +boot_option=Fallback +debug_level=Debug +power_on_after_fail=Enable diff --git a/src/mainboard/asus/p10s-series/cmos.layout b/src/mainboard/asus/p10s-series/cmos.layout new file mode 100644 index 0000000..03aea17 --- /dev/null +++ b/src/mainboard/asus/p10s-series/cmos.layout @@ -0,0 +1,73 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +0 120 r 0 reserved_memory + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 6 debug_level + +# ----------------------------------------------------------------- +# coreboot config options: cpu +400 1 e 2 hyper_threading + +# ----------------------------------------------------------------- +# coreboot config options: southbridge +409 2 e 7 power_on_after_fail + +# ----------------------------------------------------------------- +# coreboot config options: bootloader +448 128 r 0 vbnv + +# ----------------------------------------------------------------- +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/mainboard/asus/p10s-series/devicetree.cb b/src/mainboard/asus/p10s-series/devicetree.cb new file mode 100644 index 0000000..efb1585 --- /dev/null +++ b/src/mainboard/asus/p10s-series/devicetree.cb @@ -0,0 +1,174 @@ +chip soc/intel/skylake + + # Enable deep Sx states + register "deep_s5_enable_ac" = "0" + register "deep_s5_enable_dc" = "0" + register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + + # FSP Configuration + register "SmbusEnable" = "1" + register "ScsEmmcEnabled" = "0" + register "ScsEmmcHs400Enabled" = "0" + register "ScsSdCardEnabled" = "0" + register "SkipExtGfxScan" = "1" + register "Device4Enable" = "1" + register "SaGv" = "SaGv_Disabled" + + register "pirqa_routing" = "PCH_IRQ11" + register "pirqb_routing" = "PCH_IRQ10" + register "pirqc_routing" = "PCH_IRQ11" + register "pirqd_routing" = "PCH_IRQ11" + register "pirqe_routing" = "PCH_IRQ11" + register "pirqf_routing" = "PCH_IRQ11" + register "pirqg_routing" = "PCH_IRQ11" + register "pirqh_routing" = "PCH_IRQ11" + + # SATA configuration + register "SataMode" = "KBLFSP_SATA_MODE_AHCI" + register "EnableSata" = "1" + register "SataSalpSupport" = "1" + register "SataPortsEnable" = "{ \ + [0] = 1, \ + [1] = 1, \ + [2] = 1, \ + [3] = 1, \ + [4] = 1, \ + [5] = 1, \ + [6] = 1, \ + [7] = 1, \ + }" + + register "SataPortsDevSlp" = "{\ + [0] = 0, \ + [1] = 0, \ + [2] = 0, \ + [3] = 0, \ + [4] = 0, \ + [5] = 0, \ + [6] = 0, \ + [7] = 0, \ + }" + + # superspeed_inter-chip_supplement (SSIC) disabled + register "SsicPortEnable" = "0" + + # USB + register "usb2_ports" = "{ + [0] = USB2_PORT_EMPTY, + [1] = USB2_PORT_EMPTY, + [2] = USB2_PORT_EMPTY, + [3] = USB2_PORT_EMPTY, + [4] = USB2_PORT_EMPTY, + [5] = USB2_PORT_EMPTY, + [6] = USB2_PORT_EMPTY, + [7] = USB2_PORT_EMPTY, + [8] = USB2_PORT_EMPTY, + [9] = USB2_PORT_EMPTY, + [10] = USB2_PORT_EMPTY, + [11] = USB2_PORT_EMPTY, + [12] = USB2_PORT_EMPTY, + [13] = USB2_PORT_EMPTY, + }" + register "usb3_ports" = "{ + [0] = USB3_PORT_EMPTY, + [1] = USB3_PORT_EMPTY, + [2] = USB3_PORT_EMPTY, + [3] = USB3_PORT_EMPTY, + [4] = USB3_PORT_EMPTY, + [5] = USB3_PORT_EMPTY, + [6] = USB3_PORT_EMPTY, + [7] = USB3_PORT_EMPTY, + [8] = USB3_PORT_EMPTY, + [9] = USB3_PORT_EMPTY, + }" + + # LPC + register "serirq_mode" = "SERIRQ_CONTINUOUS" + + # Enabling SLP_S0, SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch + register "s0ix_enable" = "1" + register "PmConfigSlpS3MinAssert" = "SLP_S3_MIN_ASSERT_50MS" + register "PmConfigSlpS4MinAssert" = "SLP_S4_MIN_ASSERT_4S" + register "PmConfigSlpSusMinAssert" = "SLP_SUS_MIN_ASSERT_4S" + register "PmConfigSlpAMinAssert" = "SLP_A_MIN_ASSERT_2S" + + # No extra VR mailbox command + register "SendVrMbxCmd" = "0" + + # Lock Down + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 01.0 on end # CPU PCIe Port 10 (x16) + device pci 01.1 off end # CPU PCIe Port 11 (x8) + device pci 01.2 off end # CPU PCIe Port 12 (x4) + device pci 02.0 off end # Integrated Graphics Device (IGD) + device pci 04.0 off end # SA thermal subsystem + device pci 05.0 off end # Imaging Unit + device pci 08.0 off end # Gaussion Mixture Model (GMM) + device pci 13.0 off end # Integrated Sensor Hub + device pci 14.0 on end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 on end # Thermal Subsystem + device pci 15.0 off end # I2C #0 + device pci 15.1 off end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 on end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 17.0 on end # SATA + device pci 19.0 off end # UART #2 + device pci 19.1 off end # I2C #5 + device pci 19.2 off end # I2C #4 + device pci 1b.0 off end # PCH PCIe Port 17 + device pci 1b.1 off end # PCH PCIe Port 18 + device pci 1b.2 off end # PCH PCIe Port 19 + device pci 1b.3 off end # PCH PCIe Port 20 + device pci 1c.0 on end # PCH PCIe Port 1 + device pci 1c.1 off end # PCH PCIe Port 2 + device pci 1c.2 off end # PCH PCIe Port 3 + device pci 1c.3 off end # PCH PCIe Port 4 + device pci 1c.4 off end # PCH PCIe Port 5 + device pci 1c.5 on end # PCH PCIe Port 6 + device pci 1c.6 on end # PCH PCIe Port 7 + device pci 1c.7 off end # PCH PCIe Port 8 + device pci 1d.0 off end # PCH PCIe Port 9 + device pci 1d.1 off end # PCH PCIe Port 10 + device pci 1d.2 off end # PCH PCIe Port 11 + device pci 1d.3 off end # PCH PCIe Port 12 + device pci 1d.4 off end # PCH PCIe Port 13 + device pci 1d.5 off end # PCH PCIe Port 14 + device pci 1d.6 off end # PCH PCIe Port 15 + device pci 1d.7 off end # PCH PCIe Port 16 + device pci 1e.0 off end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # SPI #0 + device pci 1f.0 on # LPC Interface + chip superio/common + device pnp 2e.0 on end + end + chip drivers/pc80/tpm # TPM + device pnp 0c31.0 on end + end + end + device pci 1f.1 off end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 off end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 off end # SPI Controller + device pci 1f.6 off end # GbE + device pci 1f.7 off end # Intel Trace Hub + end +end diff --git a/src/mainboard/asus/p10s-series/dsdt.asl b/src/mainboard/asus/p10s-series/dsdt.asl new file mode 100644 index 0000000..b88b1d2 --- /dev/null +++ b/src/mainboard/asus/p10s-series/dsdt.asl @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2016 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + #include <soc/intel/skylake/acpi/platform.asl> + + // global NVS and variables + #include <soc/intel/skylake/acpi/globalnvs.asl> + + // CPU + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <soc/intel/skylake/acpi/systemagent.asl> + #include <soc/intel/skylake/acpi/pch.asl> + } + } + + // Chipset specific sleep states + #include <southbridge/intel/common/acpi/sleepstates.asl> + + // Mainboard specific + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/asus/p10s-series/include/mainboard.h b/src/mainboard/asus/p10s-series/include/mainboard.h new file mode 100644 index 0000000..ce84441 --- /dev/null +++ b/src/mainboard/asus/p10s-series/include/mainboard.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef _BOARD_ASUS_P10S_SERIES_H +#define _BOARD_ASUS_P10S_SERIES_H + +#include <device/device.h> + +void variant_mainboard_init(struct device *dev); + +#endif /* _OARD_ASUS_P10S_SERIES_H */ diff --git a/src/mainboard/asus/p10s-series/mainboard.c b/src/mainboard/asus/p10s-series/mainboard.c new file mode 100644 index 0000000..750c856 --- /dev/null +++ b/src/mainboard/asus/p10s-series/mainboard.c @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <mainboard.h> +#include <device/device.h> + +__weak void variant_mainboard_init(struct device *dev) +{ +} + +static void mainboard_init(struct device *dev) +{ + /* do common init */ + // placeholder for common mainboard initialization + + /* do variant init */ + variant_mainboard_init(dev); +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->init = mainboard_init; +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/asus/p10s-series/ramstage.c b/src/mainboard/asus/p10s-series/ramstage.c new file mode 100644 index 0000000..a16678e --- /dev/null +++ b/src/mainboard/asus/p10s-series/ramstage.c @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootstate.h> +#include <soc/ramstage.h> +#include <variant/gpio.h> + +void mainboard_silicon_init_params(FSP_SIL_UPD *params) +{ + /* Configure pads prior to SiliconInit() in case there's any + * dependencies during hardware initialization. */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/asus/p10s-series/romstage.c b/src/mainboard/asus/p10s-series/romstage.c new file mode 100644 index 0000000..cb1f105 --- /dev/null +++ b/src/mainboard/asus/p10s-series/romstage.c @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <fsp/api.h> +#include <soc/romstage.h> +#include <spd_bin.h> + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *mem_cfg; + mem_cfg = &mupd->FspmConfig; + + struct spd_block blk = { + .addr_map = { 0x50, 0x51, 0x52, 0x53, }, + }; + + mem_cfg->DqPinsInterleaved = 1; + get_spd_smbus(&blk); + mem_cfg->MemorySpdDataLen = blk.len; + mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; + mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[2]; + mem_cfg->MemorySpdPtr01 = (uintptr_t)blk.spd_array[1]; + mem_cfg->MemorySpdPtr11 = (uintptr_t)blk.spd_array[3]; + mem_cfg->UserBd = BOARD_TYPE_SERVER; + + mupd->FspmTestConfig.DmiVc1 = 1; +} diff --git a/src/mainboard/asus/p10s-series/variants/p10s-i/board_info.txt b/src/mainboard/asus/p10s-series/variants/p10s-i/board_info.txt new file mode 100644 index 0000000..adfd6c0 --- /dev/null +++ b/src/mainboard/asus/p10s-series/variants/p10s-i/board_info.txt @@ -0,0 +1,7 @@ +Category: server +Vendor name: ASUS +Board name: P10S-I +Board URL: https://www.asus.com/us/Commercial-Servers-Workstations/P10S-I/ +ROM protocol: SPI +ROM socketed: y +Flashrom support: y diff --git a/src/mainboard/asus/p10s-series/variants/p10s-i/include/variant/gpio.h b/src/mainboard/asus/p10s-series/variants/p10s-i/include/variant/gpio.h new file mode 100644 index 0000000..a08ea53 --- /dev/null +++ b/src/mainboard/asus/p10s-series/variants/p10s-i/include/variant/gpio.h @@ -0,0 +1,246 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef _GPIO_ASUS_P10S_I_H +#define _GPIO_ASUS_P10S_I_H + +#include <soc/gpe.h> +#include <soc/gpio.h> + +static const struct pad_config gpio_table[] = { +/* RCIN# */ _PAD_CFG_STRUCT(GPP_A0, 0x44000702, 0x00000000), +/* LAD0 */ _PAD_CFG_STRUCT(GPP_A1, 0x44000702, 0x00000000), +/* LAD1 */ _PAD_CFG_STRUCT(GPP_A2, 0x44000700, 0x00000000), +/* LAD2 */ _PAD_CFG_STRUCT(GPP_A3, 0x44000702, 0x00000000), +/* LAD3 */ _PAD_CFG_STRUCT(GPP_A4, 0x44000700, 0x00000000), +/* LFRAME# */ _PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x00000000), +/* SERIRQ */ _PAD_CFG_STRUCT(GPP_A6, 0x44000700, 0x00000000), +/* PIRQA# */ _PAD_CFG_STRUCT(GPP_A7, 0x44000702, 0x00000000), +/* CLKRUN# */ _PAD_CFG_STRUCT(GPP_A8, 0x44000700, 0x00000000), +/* CLKOUT_LPC0 */ _PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x00000000), +/* CLKOUT_LPC1 */ _PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x00000000), +/* PME# */ _PAD_CFG_STRUCT(GPP_A11, 0x44000702, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_A12, 0x80080201, 0x00000000), +/* SUSWARN# */ _PAD_CFG_STRUCT(GPP_A13, 0x44000700, 0x00000000), +/* SUS_STAT# */ _PAD_CFG_STRUCT(GPP_A14, 0x44000700, 0x00000000), +/* SUS_ACK# */ _PAD_CFG_STRUCT(GPP_A15, 0x44000702, 0x00000000), +/* CLKOUT_48 */ _PAD_CFG_STRUCT(GPP_A16, 0x44000700, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_A17, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_A18, 0x84000100, 0x00000000), +/* RESERVED */ //_PAD_CFG_STRUCT(GPP_A19, 0xffffffff, 0xffffff00), +/* GPIO */ _PAD_CFG_STRUCT(GPP_A20, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_A21, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_A22, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_A23, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B0, 0x44000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B1, 0x44000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B2, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B3, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B4, 0x44000301, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B5, 0x44000301, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B6, 0x84000301, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B7, 0x44000301, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B8, 0x44000301, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B9, 0x44000301, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B10, 0x44000301, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B11, 0x44000200, 0x00000000), +/* SLP_S0# */ _PAD_CFG_STRUCT(GPP_B12, 0x44000700, 0x00000000), +/* PLTRST# */ _PAD_CFG_STRUCT(GPP_B13, 0x44000700, 0x00000000), +/* SPKR */ _PAD_CFG_STRUCT(GPP_B14, 0x84000700, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B15, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B16, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B17, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B18, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B19, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B20, 0x84000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B21, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B22, 0x44000300, 0x00000000), +/* PCHHOT# */ _PAD_CFG_STRUCT(GPP_B23, 0x40000b00, 0x00000000), +/* RESERVED */ //_PAD_CFG_STRUCT(GPP_C0, 0xffffffff, 0xffffff00), +/* RESERVED */ //_PAD_CFG_STRUCT(GPP_C1, 0xffffffff, 0xffffff00), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C2, 0x44000300, 0x00000000), +/* RESERVED */ //_PAD_CFG_STRUCT(GPP_C3, 0xffffffff, 0xffffff00), +/* RESERVED */ //_PAD_CFG_STRUCT(GPP_C4, 0xffffffff, 0xffffff00), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C5, 0x44000201, 0x00000000), +/* RESERVED */ //_PAD_CFG_STRUCT(GPP_C6, 0xffffffff, 0xffffff00), +/* RESERVED */ //_PAD_CFG_STRUCT(GPP_C7, 0xffffffff, 0xffffff00), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C8, 0x84000102, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C9, 0x84000100, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C10, 0x84000102, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C11, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C12, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C13, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C14, 0x84000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C15, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C16, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C17, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C18, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C19, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C20, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C21, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C22, 0x42040102, 0x00003000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C23, 0x84000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D0, 0x84000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D1, 0x44000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D2, 0x42020102, 0x00003000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D3, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D4, 0x84000200, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D5, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D6, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D7, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D8, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D9, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D10, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D11, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D12, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D13, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D14, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D15, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D16, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D17, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D18, 0x84000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D19, 0x84000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D20, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D21, 0x44000200, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D22, 0x04000102, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D23, 0x44000300, 0x00000000), +/* SATAXPCIE0 */ _PAD_CFG_STRUCT(GPP_E0, 0x44000502, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_E1, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_E2, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_E3, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_E4, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_E5, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_E6, 0x82020102, 0x00003000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_E7, 0x44000300, 0x00000000), +/* SATA_LED# */ _PAD_CFG_STRUCT(GPP_E8, 0x44000700, 0x00000000), +/* USB_OC0# */ _PAD_CFG_STRUCT(GPP_E9, 0x44000702, 0x00000000), +/* USB_OC1# */ _PAD_CFG_STRUCT(GPP_E10, 0x44000702, 0x00000000), +/* USB_OC2# */ _PAD_CFG_STRUCT(GPP_E11, 0x44000702, 0x00000000), +/* USB_OC3# */ _PAD_CFG_STRUCT(GPP_E12, 0x44000702, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F0, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F1, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F2, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F3, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F4, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F5, 0x80100102, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F6, 0x84000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F7, 0x84000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F8, 0x84000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F9, 0x84000102, 0x00000000), +/* SATA_SCLOCK */ _PAD_CFG_STRUCT(GPP_F10, 0x44000700, 0x00000000), +/* SATA_SLOAD */ _PAD_CFG_STRUCT(GPP_F11, 0x44000700, 0x00000000), +/* SATA_SDATAOUT1 */ _PAD_CFG_STRUCT(GPP_F12, 0x44000700, 0x00000000), +/* SATA_SDATAOUT2 */ _PAD_CFG_STRUCT(GPP_F13, 0x44000700, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F14, 0x44000300, 0x00000000), +/* USB_OC4# */ _PAD_CFG_STRUCT(GPP_F15, 0x44000702, 0x00000000), +/* USB_OC5# */ _PAD_CFG_STRUCT(GPP_F16, 0x44000702, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F17, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F18, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F19, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F20, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F21, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F22, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F23, 0x04000200, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G0, 0x44000100, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G1, 0x44000100, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G2, 0x44000102, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G3, 0x44000102, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G4, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G5, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G6, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G7, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G8, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G9, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G10, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G11, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G12, 0x84000100, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G13, 0x84000100, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G14, 0x84000102, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G15, 0x84000100, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G16, 0x84000100, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G17, 0x44000300, 0x00000000), +/* NMI# */ _PAD_CFG_STRUCT(GPP_G18, 0x44000700, 0x00000000), +/* SMI# */ _PAD_CFG_STRUCT(GPP_G19, 0x44000700, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G20, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G21, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G22, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G23, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H0, 0x44000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H1, 0x84000103, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H2, 0x44000201, 0x00000000), +/* SRCCLKREQ9# */ _PAD_CFG_STRUCT(GPP_H3, 0x44000602, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H4, 0x84000103, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H5, 0x84000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H6, 0x84000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H7, 0x84000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H8, 0x84000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H9, 0x84000201, 0x00000000), +/* SML2CLK */ _PAD_CFG_STRUCT(GPP_H10, 0x44000702, 0x00000000), +/* SML2DATA */ _PAD_CFG_STRUCT(GPP_H11, 0x44000702, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H12, 0x44000300, 0x00000000), +/* SML3CLK */ _PAD_CFG_STRUCT(GPP_H13, 0x44000702, 0x00000000), +/* SML3DATA */ _PAD_CFG_STRUCT(GPP_H14, 0x44000702, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H15, 0x44000300, 0x00000000), +/* SML4CLK */ _PAD_CFG_STRUCT(GPP_H16, 0x44000702, 0x00000000), +/* SML4DATA */ _PAD_CFG_STRUCT(GPP_H17, 0x44000702, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H18, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H19, 0x84000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H20, 0x84000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H21, 0x84000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H22, 0x84000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H23, 0x84000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPD0, 0x04000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPD1, 0x04000300, 0x00000000), +/* LAN_WAKE# */ _PAD_CFG_STRUCT(GPD2, 0x04000702, 0x00000000), +/* PWRBTN# */ _PAD_CFG_STRUCT(GPD3, 0x04000702, 0x00000000), +/* SLP_S3# */ _PAD_CFG_STRUCT(GPD4, 0x04000700, 0x00000000), +/* SLP_S4# */ _PAD_CFG_STRUCT(GPD5, 0x04000700, 0x00000000), +/* SLP_A# */ _PAD_CFG_STRUCT(GPD6, 0x04000700, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPD7, 0x04000301, 0x00000000), +/* SUSCLK */ _PAD_CFG_STRUCT(GPD8, 0x04000700, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPD9, 0x04000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPD10, 0x04000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPD11, 0x04000300, 0x00000000), +/* DDPB_HPD0 */ _PAD_CFG_STRUCT(GPP_I0, 0x44000700, 0x00000000), +/* DDPC_HPD1 */ _PAD_CFG_STRUCT(GPP_I1, 0x44000700, 0x00000000), +/* DDPD_HPD2 */ _PAD_CFG_STRUCT(GPP_I2, 0x44000700, 0x00000000), +/* DDPE_HPD3 */ _PAD_CFG_STRUCT(GPP_I3, 0x84000700, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_I4, 0x44000300, 0x00000000), +/* DDPB_CTRLCLK */ _PAD_CFG_STRUCT(GPP_I5, 0x44000700, 0x00000000), +/* DDPB_CTRLDATA */ _PAD_CFG_STRUCT(GPP_I6, 0x44000700, 0x00000000), +/* DDPC_CTRLCLK */ _PAD_CFG_STRUCT(GPP_I7, 0x44000700, 0x00000000), +/* DDPC_CTRLDATA */ _PAD_CFG_STRUCT(GPP_I8, 0x44000700, 0x00000000), +/* DDPD_CTRLCLK */ _PAD_CFG_STRUCT(GPP_I9, 0x44000700, 0x00000000), +/* DDPD_CTRLDATA */ _PAD_CFG_STRUCT(GPP_I10, 0x44000700, 0x00000000), +}; + + +/*** XXX TODO XXX */ +/* Early pad configuration in romstage. */ +static const struct pad_config early_gpio_table[] = { +/* LPC */ + +/* LAD0 */ _PAD_CFG_STRUCT(GPP_A1, 0x44000702, 0x00000000), +/* LAD1 */ _PAD_CFG_STRUCT(GPP_A2, 0x44000700, 0x00000000), +/* LAD2 */ _PAD_CFG_STRUCT(GPP_A3, 0x44000702, 0x00000000), +/* LAD3 */ _PAD_CFG_STRUCT(GPP_A4, 0x44000700, 0x00000000), +/* LFRAME# */ _PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x00000000), +/* SERIRQ */ _PAD_CFG_STRUCT(GPP_A6, 0x44000700, 0x00000000), +/* CLKRUN# */ _PAD_CFG_STRUCT(GPP_A8, 0x44000700, 0x00000000), +/* CLKOUT_LPC0 */ _PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x00000000), +/* CLKOUT_LPC1 */ _PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x00000000), +}; + +#endif /* _GPIO_ASUS_P10S_I_H */ diff --git a/src/mainboard/asus/p10s-series/variants/p10s-i/overridetree.cb b/src/mainboard/asus/p10s-series/variants/p10s-i/overridetree.cb new file mode 100644 index 0000000..2e722e4 --- /dev/null +++ b/src/mainboard/asus/p10s-series/variants/p10s-i/overridetree.cb @@ -0,0 +1,143 @@ +chip soc/intel/skylake + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_B" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + + register "gen1_dec" = "0x007c0a01" # Super IO SWC + register "gen2_dec" = "0x000c0ca1" # IPMI KCS + register "gen3_dec" = "0x000c03e1" # UART3 + register "gen4_dec" = "0x000c02e1" # UART4 + + # PCIe configuration +# # Enable JPCIE1 + register "PcieRpEnable[0]" = "1" + register "PcieRpClkReqSupport[0]" = "0" + +# # Enable ASpeed PCI bridge +# register "PcieRpEnable[2]" = "1" +# register "PcieRpClkReqSupport[2]" = "0" + +# # Enable X550T (10GbE) +# register "PcieRpEnable[4]" = "1" +# register "PcieRpClkReqSupport[4]" = "0" + + # Enable I210 + register "PcieRpEnable[5]" = "1" + register "PcieRpClkReqSupport[5]" = "0" + + # Enable I210 + register "PcieRpEnable[6]" = "1" + register "PcieRpClkReqSupport[6]" = "0" + + # Enable M.2 + register "PcieRpEnable[8]" = "1" + register "PcieRpClkReqSupport[8]" = "0" + + # FIXME: find out why FSP crashes without this + register "PchHdaVcType" = "Vc1" + + # USB configuration + # USB2/3 + register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" + + # ? + register "usb2_ports[14]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[15]" = "USB2_PORT_MID(OC0)" + + # USB4/5 + register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" + register "usb2_ports[3]" = "USB2_PORT_MID(OC1)" + + # USB0/1 + register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" + register "usb2_ports[5]" = "USB2_PORT_MID(OC2)" + + # USB9/10 (USB3.0) + register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" + register "usb2_ports[12]" = "USB2_PORT_MID(OC3)" + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC3)" + + # USB6/7 (USB3.0) + register "usb2_ports[10]" = "USB2_PORT_MID(OC4)" + register "usb2_ports[11]" = "USB2_PORT_MID(OC4)" + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC4)" + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC4)" + + # USB8 (USB3.0) + register "usb2_ports[9]" = "USB2_PORT_MID(OC5)" + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC5)" + + # IPMI USB HUB + register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" + + device domain 0 on + device pci 01.0 on # CPU PCIe Slot + smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthShort" "CPU SLOT7 PCI-E 3.0 X16" "SlotDataBusWidth16X" + end + device pci 1c.0 on # PCI Express Port 1 + device pci 00.0 on # Aspeed PCI Bridge + device pci 00.0 on end # Aspeed 2400 VGA + end + end + device pci 1c.5 on # PCI Express Port 5 + device pci 00.0 on end # 1GbE + end + device pci 1c.6 on # PCI Express Port 6 + device pci 00.0 on end # 1GbE + end + device pci 1d.0 on # PCI Express Port 9 + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2 2242" "SlotDataBusWidth4X" + end + device pci 1f.0 on # LPC Interface + chip drivers/ipmi + # On cold boot it takes a while for the BMC to start the IPMI service + register "wait_for_bmc" = "1" + register "bmc_boot_timeout" = "60" + device pnp ca2.0 on end # IPMI KCS + end + chip superio/common + device pnp 2e.0 on + chip superio/aspeed/ast2400 + device pnp 2e.2 on # SUART1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # SUART2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.4 on # SWC + io 0x60 = 0xa00 + io 0x62 = 0xa10 + io 0x64 = 0xa20 + io 0x66 = 0xa30 + irq 0x70 = 0xb + end + device pnp 2e.5 off end # KBC + device pnp 2e.7 on end # GPIO + device pnp 2e.b on # SUART3 + io 0x60 = 0x3e8 + irq 0x70 = 4 + end + device pnp 2e.c on # SUART4 + io 0x60 = 0x2e8 + irq 0x70 = 3 + end + device pnp 2e.d on end # iLPC2AHB + device pnp 2e.e on # Mailbox + io 0x60 = 0xa40 + irq 0x70 = 0x00 + end + end + end + end + end + end +end diff --git a/src/mainboard/asus/p10s-series/variants/p10s-m/Makefile.inc b/src/mainboard/asus/p10s-series/variants/p10s-m/Makefile.inc new file mode 100644 index 0000000..f3c87b2 --- /dev/null +++ b/src/mainboard/asus/p10s-series/variants/p10s-m/Makefile.inc @@ -0,0 +1 @@ +ramstage-y += mainboard.c diff --git a/src/mainboard/asus/p10s-series/variants/p10s-m/board_info.txt b/src/mainboard/asus/p10s-series/variants/p10s-m/board_info.txt new file mode 100644 index 0000000..b868459 --- /dev/null +++ b/src/mainboard/asus/p10s-series/variants/p10s-m/board_info.txt @@ -0,0 +1,7 @@ +Category: server +Vendor name: ASUS +Board name: P10S-M +Board URL: https://www.asus.com/us/Commercial-Servers-Workstations/P10S-M/ +ROM protocol: SPI +ROM socketed: y +Flashrom support: y diff --git a/src/mainboard/asus/p10s-series/variants/p10s-m/include/variant/gpio.h b/src/mainboard/asus/p10s-series/variants/p10s-m/include/variant/gpio.h new file mode 100644 index 0000000..4c551d1 --- /dev/null +++ b/src/mainboard/asus/p10s-series/variants/p10s-m/include/variant/gpio.h @@ -0,0 +1,269 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef _GPIO_ASUS_P10S_M_H +#define _GPIO_ASUS_P10S_M_H + +#include <soc/gpe.h> +#include <soc/gpio.h> + +static const struct pad_config gpio_table[] = { + /* GPIO Group GPP_A */ + _PAD_CFG_STRUCT(GPP_A0, 0x44000700, 0x00000010), /* RCIN# */ + _PAD_CFG_STRUCT(GPP_A1, 0x44000700, 0x00000010), /* LAD0 */ + _PAD_CFG_STRUCT(GPP_A2, 0x44000700, 0x00000010), /* LAD1 */ + _PAD_CFG_STRUCT(GPP_A3, 0x44000700, 0x00000010), /* LAD2 */ + _PAD_CFG_STRUCT(GPP_A4, 0x44000700, 0x00000010), /* LAD3 */ + _PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x00000010), /* LFRAME# */ + _PAD_CFG_STRUCT(GPP_A6, 0x44000700, 0x00000010), /* SERIRQ */ + _PAD_CFG_STRUCT(GPP_A7, 0x44000700, 0x00000010), /* PIRQA# */ + _PAD_CFG_STRUCT(GPP_A8, 0x44000700, 0x00000010), /* CLKRUN# */ + _PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x00000010), /* CLKOUT_LPC0 */ + _PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x00000010), /* CLKOUT_LPC1 */ + _PAD_CFG_STRUCT(GPP_A11, 0x44000700, 0x00000010), /* PME# */ + _PAD_CFG_STRUCT(GPP_A12, 0x84000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_A13, 0x44000700, 0x00000010), /* SUSWARN#/SUSPWRDNACK */ + _PAD_CFG_STRUCT(GPP_A14, 0x44000700, 0x00000010), /* SUS_STAT# */ + _PAD_CFG_STRUCT(GPP_A15, 0x44000700, 0x00000010), /* SUS_ACK# */ + _PAD_CFG_STRUCT(GPP_A16, 0x44000700, 0x00000010), /* CLKOUT_48 */ + _PAD_CFG_STRUCT(GPP_A17, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_A18, 0x84000100, 0x00000010), /* GPIO */ + /* reserved */ + //_PAD_CFG_STRUCT(GPP_A19, 0xffffffff, 0xffffffff), /* ISH_GP1 */ + _PAD_CFG_STRUCT(GPP_A20, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_A21, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_A22, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_A23, 0x44000300, 0x00000010), /* GPIO */ + + /* GPIO Group GPP_B */ + _PAD_CFG_STRUCT(GPP_B0, 0x44000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B1, 0x44000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B2, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B3, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B4, 0x44000301, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B5, 0x44000301, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B6, 0x84000301, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B7, 0x44000301, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B8, 0x44000301, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B9, 0x44000301, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B10, 0x44000301, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B11, 0x44000200, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B12, 0x44000700, 0x00000010), /* SLP_S0# */ + _PAD_CFG_STRUCT(GPP_B13, 0x44000700, 0x00000010), /* PLTRST# */ + _PAD_CFG_STRUCT(GPP_B14, 0x84000700, 0x00000010), /* SPKR */ + _PAD_CFG_STRUCT(GPP_B15, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B16, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B17, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B18, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B19, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B20, 0x84000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B21, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B22, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B23, 0x40000b00, 0x00000010), /* PCHHOT# */ + + /* GPIO Group GPP_C */ + /* reserved */ + //_PAD_CFG_STRUCT(GPP_C0, 0x44000700, 0x00000010), /* SMBCLK */ + //_PAD_CFG_STRUCT(GPP_C1, 0x44000700, 0x00000010), /* SMBDATA */ + _PAD_CFG_STRUCT(GPP_C2, 0x44000300, 0x00000010), /* GPIO */ + /* reserved */ + //_PAD_CFG_STRUCT(GPP_C3, 0x44000700, 0x00000010), /* SML0CLK */ + //_PAD_CFG_STRUCT(GPP_C4, 0x44000700, 0x00000010), /* SML0DATA */ + _PAD_CFG_STRUCT(GPP_C5, 0x44000201, 0x00000010), /* GPIO */ + /* reserved */ + //_PAD_CFG_STRUCT(GPP_C6, 0x44000700, 0x00000010), /* SML1CLK */ + //_PAD_CFG_STRUCT(GPP_C7, 0x44000700, 0x00000010), /* SML1DATA */ + _PAD_CFG_STRUCT(GPP_C8, 0x84000100, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C9, 0x84000100, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C10, 0x84000100, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C11, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C12, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C13, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C14, 0x84000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C15, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C16, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C17, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C18, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C19, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C20, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C21, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C22, 0x42040100, 0x00003010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C23, 0x84000300, 0x00000010), /* GPIO */ + + /* GPIO Group GPP_D */ + _PAD_CFG_STRUCT(GPP_D0, 0x84000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D1, 0x44000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D2, 0x42020100, 0x00003000), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D3, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D4, 0x84000200, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D5, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D6, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D7, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D8, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D9, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D10, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D11, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D12, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D13, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D14, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D15, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D16, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D17, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D18, 0x84000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D19, 0x84000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D20, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D21, 0x44000200, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D22, 0x04000100, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D23, 0x44000300, 0x00000010), /* GPIO */ + + /* GPIO Group GPP_E */ + _PAD_CFG_STRUCT(GPP_E0, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_E1, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_E2, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_E3, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_E4, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_E5, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_E6, 0x82020100, 0x00003000), /* GPIO */ + _PAD_CFG_STRUCT(GPP_E7, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_E8, 0x44000700, 0x00000010), /* SATA_LED# */ + _PAD_CFG_STRUCT(GPP_E9, 0x44000700, 0x00000010), /* USB_OC0# */ + _PAD_CFG_STRUCT(GPP_E10, 0x44000700, 0x00000010), /* USB_OC1# */ + _PAD_CFG_STRUCT(GPP_E11, 0x44000700, 0x00000010), /* USB_OC2# */ + _PAD_CFG_STRUCT(GPP_E12, 0x44000700, 0x00000010), /* USB_OC3# */ + + /* GPIO Group GPP_F */ + _PAD_CFG_STRUCT(GPP_F0, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F1, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F2, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F3, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F4, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F5, 0x80100100, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F6, 0x84000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F7, 0x84000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F8, 0x84000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F9, 0x84000100, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F10, 0x44000700, 0x00000010), /* SATA_SCLOCK */ + _PAD_CFG_STRUCT(GPP_F11, 0x44000700, 0x00000010), /* SATA_SLOAD */ + _PAD_CFG_STRUCT(GPP_F12, 0x44000700, 0x00000010), /* SATA_SDATAOUT1 */ + _PAD_CFG_STRUCT(GPP_F13, 0x44000700, 0x00000010), /* SATA_SDATAOUT2 */ + _PAD_CFG_STRUCT(GPP_F14, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F15, 0x44000700, 0x00000010), /* USB_OC4# */ + _PAD_CFG_STRUCT(GPP_F16, 0x44000700, 0x00000010), /* USB_OC5# */ + _PAD_CFG_STRUCT(GPP_F17, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F18, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F19, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F20, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F21, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F22, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F23, 0x04000200, 0x00000010), /* GPIO */ + + /* GPIO Group GPP_G */ + _PAD_CFG_STRUCT(GPP_G0, 0x44000100, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G1, 0x44000100, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G2, 0x44000100, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G3, 0x44000100, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G4, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G5, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G6, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G7, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G8, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G9, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G10, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G11, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G12, 0x84000100, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G13, 0x84000100, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G14, 0x84000100, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G15, 0x84000100, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G16, 0x84000100, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G17, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G18, 0x44000700, 0x00000010), /* NMI# */ + _PAD_CFG_STRUCT(GPP_G19, 0x44000700, 0x00000010), /* SMI# */ + _PAD_CFG_STRUCT(GPP_G20, 0x44000300, 0x00000000), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G21, 0x44000300, 0x00000000), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G22, 0x44000300, 0x00000000), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G23, 0x44000300, 0x00000010), /* GPIO */ + + /* GPIO Group GPP_H */ + _PAD_CFG_STRUCT(GPP_H0, 0x44000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H1, 0x84000101, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H2, 0x44000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H3, 0x44000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H4, 0x84000101, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H5, 0x84000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H6, 0x84000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H7, 0x84000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H8, 0x84000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H9, 0x84000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H10, 0x44000700, 0x00000010), /* SML2CLK */ + _PAD_CFG_STRUCT(GPP_H11, 0x44000700, 0x00000010), /* SML2DATA */ + _PAD_CFG_STRUCT(GPP_H12, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H13, 0x44000700, 0x00000010), /* SML3CLK */ + _PAD_CFG_STRUCT(GPP_H14, 0x44000700, 0x00000010), /* SML3DATA */ + _PAD_CFG_STRUCT(GPP_H15, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H16, 0x44000700, 0x00000010), /* SML4CLK */ + _PAD_CFG_STRUCT(GPP_H17, 0x44000700, 0x00000010), /* SML4DATA */ + _PAD_CFG_STRUCT(GPP_H18, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H19, 0x84000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H20, 0x84000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H21, 0x84000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H22, 0x84000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H23, 0x84000201, 0x00000010), /* GPIO */ + + /* GPIO Group GPP_I */ + _PAD_CFG_STRUCT(GPP_I0, 0x44000700, 0x00000010), /* DDPB_HPD0 */ + _PAD_CFG_STRUCT(GPP_I1, 0x44000700, 0x00000010), /* DDPC_HPD1 */ + _PAD_CFG_STRUCT(GPP_I2, 0x44000700, 0x00000010), /* DDPD_HPD2 */ + _PAD_CFG_STRUCT(GPP_I3, 0x84000700, 0x00000010), /* DDPE_HPD3 */ + _PAD_CFG_STRUCT(GPP_I4, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_I5, 0x44000700, 0x00000010), /* DDPB_CTRLCLK */ + _PAD_CFG_STRUCT(GPP_I6, 0x44000700, 0x00000010), /* DDPB_CTRLDATA */ + _PAD_CFG_STRUCT(GPP_I7, 0x44000700, 0x00000010), /* DDPC_CTRLCLK */ + _PAD_CFG_STRUCT(GPP_I8, 0x44000700, 0x00000010), /* DDPC_CTRLDATA */ + _PAD_CFG_STRUCT(GPP_I9, 0x44000700, 0x00000010), /* DDPD_CTRLCLK */ + _PAD_CFG_STRUCT(GPP_I10, 0x44000700, 0x00000010), /* DDPD_CTRLDATA */ + + /* GPIO Group GPD */ + _PAD_CFG_STRUCT(GPD0, 0x04000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPD1, 0x04000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPD2, 0x04000700, 0x00000010), /* LAN_WAKE# */ + _PAD_CFG_STRUCT(GPD3, 0x04000700, 0x00000010), /* PWRBTN# */ + _PAD_CFG_STRUCT(GPD4, 0x04000700, 0x00000010), /* SLP_S3# */ + _PAD_CFG_STRUCT(GPD5, 0x04000700, 0x00000010), /* SLP_S4# */ + _PAD_CFG_STRUCT(GPD6, 0x04000700, 0x00000010), /* SLP_A# */ + _PAD_CFG_STRUCT(GPD7, 0x04000301, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPD8, 0x04000700, 0x00000010), /* SUSCLK */ + _PAD_CFG_STRUCT(GPD9, 0x04000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPD10, 0x04000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPD11, 0x04000300, 0x00000010), /* GPIO */ +}; + +/* Early pad configuration in romstage. */ +static const struct pad_config early_gpio_table[] = { + /* GPIO Group GPP_A */ + /* LPC */ + _PAD_CFG_STRUCT(GPP_A1, 0x44000700, 0x00000010), /* LAD0 */ + _PAD_CFG_STRUCT(GPP_A2, 0x44000700, 0x00000010), /* LAD1 */ + _PAD_CFG_STRUCT(GPP_A3, 0x44000700, 0x00000010), /* LAD2 */ + _PAD_CFG_STRUCT(GPP_A4, 0x44000700, 0x00000010), /* LAD3 */ + _PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x00000010), /* LFRAME# */ + _PAD_CFG_STRUCT(GPP_A8, 0x44000700, 0x00000010), /* CLKRUN# */ + _PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x00000010), /* CLKOUT_LPC0 */ + _PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x00000010), /* CLKOUT_LPC1 */ + + /* Serial interrupt */ + _PAD_CFG_STRUCT(GPP_A6, 0x44000700, 0x00000010), /* SERIRQ */ +}; + +#endif /* _GPIO_ASUS_P10S_M_H */ diff --git a/src/mainboard/asus/p10s-series/variants/p10s-m/mainboard.c b/src/mainboard/asus/p10s-series/variants/p10s-m/mainboard.c new file mode 100644 index 0000000..7cf8883 --- /dev/null +++ b/src/mainboard/asus/p10s-series/variants/p10s-m/mainboard.c @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <mainboard.h> +#include <device/device.h> +#include <intelblocks/itss.h> +#include <intelblocks/pcr.h> +#include <soc/itss.h> +#include <soc/pcr_ids.h> + +void variant_mainboard_init(struct device *dev) +{ + /* TODO: + * Find out why the polarities from gpio.h gets overwritten by FSP. + * This sets irq polarity to the same values as vendor + * but I do not know if this is really needed.... + */ + itss_set_irq_polarity(33, 0); + itss_set_irq_polarity(34, 0); + + // TODO: NMI; is this needed? vendor sets it + pcr_write32(0xae, 0x01e4, 0x00000004); + pcr_write32(0xae, 0x01e8, 0x00000040); +} diff --git a/src/mainboard/asus/p10s-series/variants/p10s-m/overridetree.cb b/src/mainboard/asus/p10s-series/variants/p10s-m/overridetree.cb new file mode 100644 index 0000000..ea90e0b --- /dev/null +++ b/src/mainboard/asus/p10s-series/variants/p10s-m/overridetree.cb @@ -0,0 +1,124 @@ +chip soc/intel/skylake + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_G" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + + register "gen1_dec" = "0x007c0a01" # Super IO SWC + register "gen2_dec" = "0x000c0ca1" # IPMI KCS + register "gen3_dec" = "0x000c03e1" # UART3 + register "gen4_dec" = "0x000c02e1" # UART4 + + # PCIe configuration + register "PcieRpEnable[0]" = "1" # Enable PCH PCIe Port 1 / PCH SLOT4 + register "PcieRpEnable[4]" = "1" # Enable PCH PCIe Port 5 / PCH SLOT5 + register "PcieRpEnable[8]" = "1" # Enable PCH PCIe Port 9 / GbE 1 + register "PcieRpEnable[9]" = "1" # Enable PCH PCIe Port 10 / GbE 2 + register "PcieRpEnable[10]" = "1" # Enable PCH PCIe Port 11 / Aspeed 2400 VGA + + # USB configuration + # USB0/1 + register "usb2_ports[5]" = "USB2_PORT_MID(OC2)" + register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" + + # USB2/3 + register "usb2_ports[3]" = "USB2_PORT_MID(OC1)" + register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" + + # USB4/5 + register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" + + # USB6/7 (USB3.0) + register "usb2_ports[11]" = "USB2_PORT_MID(OC4)" + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC4)" + register "usb2_ports[10]" = "USB2_PORT_MID(OC4)" + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC4)" + + # USB8/9 (USB3.0) + register "usb2_ports[1]" = "USB2_PORT_MID(OC3)" + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC3)" + register "usb2_ports[0]" = "USB2_PORT_MID(OC3)" + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" + + # USB10 (USB3.0) + register "usb2_ports[9]" = "USB2_PORT_MID(OC5)" + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC5)" + + # IPMI USB HUB + register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" + + device domain 0 on + device pci 01.0 on # CPU PCIe Port (x16) / PCIe Slot 6 (JPCIE6) + smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong" "CPU SLOT6 PCI-E 3.0 X8(IN X16)" "SlotDataBusWidth8X" + end + device pci 01.1 on # CPU PCIe Port (x8) / PCIe Slot 7 (JPCIE7) + smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "CPU SLOT7 PCI-E 3.0 X8" "SlotDataBusWidth8X" + end + device pci 1c.0 on # PCH PCIe Port 1 / PCIe Slot 4 (JPCIE4) + smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "PCH SLOT4 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X" + end + device pci 1c.4 on # PCH PCIe Port 5 / PCIe Slot 5 (JPCIE5) + smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "PCH SLOT5 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X" + end + device pci 1d.0 on # PCH PCIe Port 9 + device pci 00.0 on end # GbE 1 + end + device pci 1d.1 on # PCH PCIe Port 10 + device pci 00.1 on end # GbE 2 + end + device pci 1d.2 on # PCH PCIe Port 11 + device pci 00.0 on # Aspeed PCI Bridge + device pci 00.0 on end # Aspeed 2400 VGA + end + end + device pci 1f.0 on # LPC Interface + chip drivers/ipmi + # On cold boot it takes a while for the BMC to start the IPMI service + register "wait_for_bmc" = "1" + register "bmc_boot_timeout" = "60" + device pnp ca2.0 on end # IPMI KCS + end + chip superio/common + device pnp 2e.0 on + chip superio/aspeed/ast2400 + device pnp 2e.2 on # SUART1 / COM1 (ext) + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # SUART2 / COM2 (int) + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.4 on # SWC + io 0x60 = 0xa00 + io 0x62 = 0xa10 + io 0x64 = 0xa20 + io 0x66 = 0xa30 + irq 0x70 = 0xb + end + device pnp 2e.5 off end # KBC + device pnp 2e.7 on end # GPIO + device pnp 2e.b on # SUART3 + io 0x60 = 0x3e8 + irq 0x70 = 4 + end + device pnp 2e.c on # SUART4 + io 0x60 = 0x2e8 + irq 0x70 = 3 + end + device pnp 2e.d on end # iLPC2AHB + device pnp 2e.e on # Mailbox + io 0x60 = 0xa40 + irq 0x70 = 0x00 + end + end + end + end + end + end +end diff --git a/src/mainboard/asus/p10s-series/vboot-ro-rwab.fmd b/src/mainboard/asus/p10s-series/vboot-ro-rwab.fmd new file mode 100644 index 0000000..a295680 --- /dev/null +++ b/src/mainboard/asus/p10s-series/vboot-ro-rwab.fmd @@ -0,0 +1,36 @@ +FLASH 16M { + SI_ALL@0x0 0x500000 { + SI_DESC@0x0 0x1000 + SI_ME@0x1000 0x4ff000 + } + SI_BIOS@0x500000 0xb00000 { + RW_SECTION_A@0x0 0x33e000 { + VBLOCK_A@0x0 0x20000 + FW_MAIN_A(CBFS)@0x20000 0x31dfc0 + RW_FWID_A@0x33dfc0 0x40 + } + RW_SECTION_B@0x33e000 0x33e000 { + VBLOCK_B@0x0 0x20000 + FW_MAIN_B(CBFS)@0x20000 0x31dfc0 + RW_FWID_B@0x33dfc0 0x40 + } + MISC_RW@0x67d000 0x62000 { + UNIFIED_MRC_CACHE@0x0 0x20000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + } + RW_VPD(PRESERVE)@0x20000 0x2000 + SMMSTORE(PRESERVE)@0x22000 0x40000 + } + WP_RO@0x6df000 0x421000 { + RO_VPD(PRESERVE)@0x0 0x4000 + RO_SECTION@0x4000 0x41d000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + GBB@0x1000 0xef000 + COREBOOT(CBFS)@0xf0000 0x32d000 + } + } + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/37995 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd20e69f16421518143b9d80b2a0d821ec37703e Gerrit-Change-Number: 37995 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Cody-Little <kcodyjr(a)gmail.com> Gerrit-MessageType: newchange

4 12

Change in coreboot[master]: soc/intel/common: Make use of clflush in common platform_segment_loaded
by Subrata Banik (Code Review) 07 Aug '23

07 Aug '23

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34992 ) Change subject: soc/intel/common: Make use of clflush in common platform_segment_loaded ...................................................................... soc/intel/common: Make use of clflush in common platform_segment_loaded This patch clear cache lines based on platform_segment_loaded() supplied start and size values before loading the targeted stage. This changes is required to fix hang issues appeared due to marking DRAM ranges as WB (CONFIG_MARK_DRAM_CACHE_WB) to speed up next stage loading/ decompression/execution time. Idea is to run clflush on those ranges just before tearing down the CAR (running invd instruction) and after that postcar frame will set up new MTRR ranges. Change-Id: I591f21cb4199477af271f0dd6c073e1c11831bfd Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/common/block/cpu/Kconfig M src/soc/intel/common/block/cpu/Makefile.inc A src/soc/intel/common/block/cpu/car/car.c 3 files changed, 71 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/34992/1 diff --git a/src/soc/intel/common/block/cpu/Kconfig b/src/soc/intel/common/block/cpu/Kconfig index 8cc572d..0d1506b 100644 --- a/src/soc/intel/common/block/cpu/Kconfig +++ b/src/soc/intel/common/block/cpu/Kconfig @@ -66,3 +66,15 @@ help This option allows FSP to make use of MP services PPI published by coreboot to perform multiprocessor initialization. + +config MARK_DRAM_CACHE_WB + bool + default n + help + This option allows you to select how DRAM intermediate cache is set up. + Till discovering DRAM ranges, system will make use of CAR and CAR tear + down will handle by postcar/ramstage, that means entire postcar/ramstage + stage will execute from UC range. Intention here is to optimize the boot + flow hence enabling the caching for applicable DRAM ranges before CAR + tear down and setting up new DRAM based MTRR range. MTRR type WB + provides best optimization. diff --git a/src/soc/intel/common/block/cpu/Makefile.inc b/src/soc/intel/common/block/cpu/Makefile.inc index a6c4f37..63a2ac9 100644 --- a/src/soc/intel/common/block/cpu/Makefile.inc +++ b/src/soc/intel/common/block/cpu/Makefile.inc @@ -5,6 +5,7 @@ romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CAR) += car/exit_car.S romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += cpulib.c +romstage-$(CONFIG_MARK_DRAM_CACHE_WB) += car.c postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CAR) += car/exit_car.S postcar-$(CONFIG_FSP_CAR) += car/exit_car_fsp.S diff --git a/src/soc/intel/common/block/cpu/car/car.c b/src/soc/intel/common/block/cpu/car/car.c new file mode 100644 index 0000000..82d8e9a --- /dev/null +++ b/src/soc/intel/common/block/cpu/car/car.c @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <assert.h> +#include <cbmem.h> +#include <cpu/x86/cache.h> +#include <program_loading.h> + +static inline int is_usable_dram_addr(uintptr_t addr) +{ + return (addr < (uintptr_t) cbmem_top()); +} + +/* + * CLFLUSH the impacted WB'ed cache lines before loading postcar/ramstage + * in order to avoid getting stuck while tearing down (invd) the CAR. + */ +static void flush_cache(uintptr_t start, size_t size) +{ + uintptr_t end; + uintptr_t addr; + + end = start + (ALIGN_DOWN(size + 4096, 4096)); + for (addr = start; addr < end; addr += 64) + clflush((void *)addr); +} + +void platform_segment_loaded(uintptr_t start, size_t size, int flags) +{ + /* Bail out if this is not the final segment. */ + if (!(flags & SEG_FINAL)) + return; + + char start_dram_check = is_usable_dram_addr(start); + char end_dram_check = is_usable_dram_addr(start + size - 1); + + /* + * Bail out if loaded program segment does not lie in + * usable DRAM region. + */ + if (!start_dram_check && !end_dram_check) + return; + + flush_cache(start, size); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/34992 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I591f21cb4199477af271f0dd6c073e1c11831bfd Gerrit-Change-Number: 34992 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: mb/lenovo/{t410,x201}: Make X201 a variant board of T410
by Maccraft123 (Code Review) 07 Aug '23

07 Aug '23

Maccraft123 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36871 ) Change subject: mb/lenovo/{t410,x201}: Make X201 a variant board of T410 ...................................................................... mb/lenovo/{t410,x201}: Make X201 a variant board of T410 T410 and X201 boards are similar enough to be variants in the same mainboard tree. So I did it. Change-Id: Icfa1818812347ceb4e2de5cc4a3130537a4e13e7 Signed-off-by: Maciej Matuszczyj <maccraft123mc(a)gmail.com> --- A .tmpconfig.lintiC3nbS M src/mainboard/lenovo/t410/Kconfig M src/mainboard/lenovo/t410/Kconfig.name M src/mainboard/lenovo/t410/Makefile.inc M src/mainboard/lenovo/t410/dock.c M src/mainboard/lenovo/t410/hda_verb.c M src/mainboard/lenovo/t410/mainboard.c M src/mainboard/lenovo/t410/romstage.c C src/mainboard/lenovo/t410/variants/t410/board_info.txt R src/mainboard/lenovo/t410/variants/t410/data.vbt R src/mainboard/lenovo/t410/variants/t410/devicetree.cb R src/mainboard/lenovo/t410/variants/t410/gpio.c R src/mainboard/lenovo/t410/variants/x201/board_info.txt R src/mainboard/lenovo/t410/variants/x201/data.vbt R src/mainboard/lenovo/t410/variants/x201/devicetree.cb R src/mainboard/lenovo/t410/variants/x201/gpio.c D src/mainboard/lenovo/x201/Kconfig D src/mainboard/lenovo/x201/Kconfig.name D src/mainboard/lenovo/x201/Makefile.inc D src/mainboard/lenovo/x201/acpi/dock.asl D src/mainboard/lenovo/x201/acpi/ec.asl D src/mainboard/lenovo/x201/acpi/gpe.asl D src/mainboard/lenovo/x201/acpi/platform.asl D src/mainboard/lenovo/x201/acpi/superio.asl D src/mainboard/lenovo/x201/acpi_tables.c D src/mainboard/lenovo/x201/cmos.default D src/mainboard/lenovo/x201/cmos.layout D src/mainboard/lenovo/x201/dock.c D src/mainboard/lenovo/x201/dock.h D src/mainboard/lenovo/x201/dsdt.asl D src/mainboard/lenovo/x201/early_init.c D src/mainboard/lenovo/x201/gma-mainboard.ads D src/mainboard/lenovo/x201/hda_verb.c D src/mainboard/lenovo/x201/mainboard.c D src/mainboard/lenovo/x201/romstage.c D src/mainboard/lenovo/x201/smihandler.c D src/mainboard/lenovo/x201/thermal.h D src/mainboard/lenovo/x201/vboot-rwa.fmd 38 files changed, 106 insertions(+), 1,132 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/36871/1 diff --git a/.tmpconfig.lintiC3nbS b/.tmpconfig.lintiC3nbS new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/.tmpconfig.lintiC3nbS diff --git a/src/mainboard/lenovo/t410/Kconfig b/src/mainboard/lenovo/t410/Kconfig index 329d08d..3b21f1b 100644 --- a/src/mainboard/lenovo/t410/Kconfig +++ b/src/mainboard/lenovo/t410/Kconfig @@ -1,4 +1,4 @@ -if BOARD_LENOVO_T410 +if BOARD_LENOVO_T410 || BOARD_LENOVO_X201 config BOARD_SPECIFIC_OPTIONS def_bool y @@ -14,6 +14,7 @@ select HAVE_ACPI_TABLES select INTEL_INT15 select HAVE_ACPI_RESUME + select SUPERIO_NSC_PC87382 if BOARD_LENOVO_X201 select DRIVERS_LENOVO_WACOM select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 @@ -38,6 +39,10 @@ hex default 0x2a +config DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" + config FMDFILE string default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT @@ -48,7 +53,8 @@ config MAINBOARD_PART_NUMBER string - default "ThinkPad T410" + default "ThinkPad T410" if BOARD_LENOVO_T410 + default "ThinkPad X201" if BOARD_LENOVO_X201 config USBDEBUG_HCD_INDEX int @@ -66,4 +72,10 @@ int default 10 +# Without the Intel ME's EFFS partition some PCIe devices (like the USB and SATA +# controllers) don't work as expected +config ME_CLEANER_ARGS + string + default "-S -w EFFS" + endif diff --git a/src/mainboard/lenovo/t410/Kconfig.name b/src/mainboard/lenovo/t410/Kconfig.name index d79cf39..531f21f 100644 --- a/src/mainboard/lenovo/t410/Kconfig.name +++ b/src/mainboard/lenovo/t410/Kconfig.name @@ -1,2 +1,5 @@ config BOARD_LENOVO_T410 bool "ThinkPad T410" + +config BOARD_LENOVO_X201 + bool "ThinkPad X201" diff --git a/src/mainboard/lenovo/t410/Makefile.inc b/src/mainboard/lenovo/t410/Makefile.inc index 518d91a..9ff4abe 100644 --- a/src/mainboard/lenovo/t410/Makefile.inc +++ b/src/mainboard/lenovo/t410/Makefile.inc @@ -21,4 +21,5 @@ romstage-y += dock.c ramstage-y += dock.c -romstage-y += gpio.c +romstage-$(CONFIG_MAINBOARD_LENOVO_X201) += variants/x201/gpio.c +romstage-$(CONFIG_MAINBOARD_LENOVO_T410) += variants/t410/gpio.c diff --git a/src/mainboard/lenovo/t410/dock.c b/src/mainboard/lenovo/t410/dock.c index 1575aa1..5c5f731 100644 --- a/src/mainboard/lenovo/t410/dock.c +++ b/src/mainboard/lenovo/t410/dock.c @@ -3,6 +3,7 @@ * * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> * Copyright (C) 2013 Vladimir Serbinenko <phcoder(a)gmail.com> + * Copyright (C) 2019 Maciej Matuszczyk * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -37,6 +38,9 @@ ec_set_bit(0x02, 0); ec_set_bit(0x1a, 0); ec_set_bit(0xfe, 4); + #if CONFIG(BOARD_LENOVO_X201) + set_gpio(28, GPIO_LEVEL_HICH); // Might also work ok t410, + #endif } void dock_disconnect(void) @@ -45,6 +49,9 @@ ec_clr_bit(0x02, 0); ec_clr_bit(0x1a, 0); ec_clr_bit(0xfe, 4); + #if CONFIG(BOARD_LENOVO_X201) + set_gpio(28, GPIO_LEVEL_LOW); + #endif } int dock_present(void) diff --git a/src/mainboard/lenovo/t410/hda_verb.c b/src/mainboard/lenovo/t410/hda_verb.c index 752e5da..c12e8b4 100644 --- a/src/mainboard/lenovo/t410/hda_verb.c +++ b/src/mainboard/lenovo/t410/hda_verb.c @@ -19,15 +19,27 @@ const u32 cim_verb_data[] = { /* coreboot specific header */ 0x14F15069, /* Codec Vendor / Device ID: Conexant CX20585 */ + #if CONFIG(BOARD_LENOVO_T410) 0x17AA214C, /* Subsystem ID */ + #elif CONFIG(BOARD_LENOVO_X201) + 0x17AA2155, /* Subsystem ID */ + #endif 0x0000000B, /* Number of 4 dword sets */ + #if CONFIG(BOARD_LENOVO_T410) AZALIA_SUBVENDOR(0x0, 0x17AA214C), + #elif CONFIG(BOARD_LENOVO_X201) + AZALIA_SUBVENDOR(0x0, 0x17AA2155), + #endif AZALIA_PIN_CFG(0x0, 0x19, 0x042110F0), AZALIA_PIN_CFG(0x0, 0x1A, 0x61A190F0), AZALIA_PIN_CFG(0x0, 0x1B, 0x04A110F0), AZALIA_PIN_CFG(0x0, 0x1C, 0x612140F0), + #if CONFIG(BOARD_LENOVO_T410) AZALIA_PIN_CFG(0x0, 0x1D, 0x40F001F0), + #elif CONFIG(BOARD_LENOVO_X201) + AZALIA_PIN_CFG(0x0, 0x1D, 0x601700F0), + #endif AZALIA_PIN_CFG(0x0, 0x1E, 0x40F001F0), AZALIA_PIN_CFG(0x0, 0x1F, 0x901701F0), AZALIA_PIN_CFG(0x0, 0x20, 0x40F001F0), @@ -35,7 +47,11 @@ AZALIA_PIN_CFG(0x0, 0x23, 0x90A601F0), 0x80862804, /* Codec Vendor / Device ID: Intel Ibexpeak HDMI. */ + #if CONFIG(BOARD_LENOVO_T410) 0x17AA21B5, /* Subsystem ID */ + #elif CONFIG(BOARD_LENOVO_X201) + 0x17aa21b5, /* Subsystem ID */ + #endif 0x00000004, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0x3, 0x17AA21B5), diff --git a/src/mainboard/lenovo/t410/mainboard.c b/src/mainboard/lenovo/t410/mainboard.c index 8b6a737..d961db1 100644 --- a/src/mainboard/lenovo/t410/mainboard.c +++ b/src/mainboard/lenovo/t410/mainboard.c @@ -4,6 +4,7 @@ * Copyright (C) 2007-2009 coresystems GmbH * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> * Copyright (C) 2013 Vladimir Serbinenko <phcoder(a)gmail.com> + * Copyright (C) 2019 Maciej Matuszczyk * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -17,12 +18,28 @@ */ #include <device/device.h> -#include <arch/acpi.h> -#include <drivers/intel/gma/int15.h> +#include <device/pci_ops.h> +#include <ec/acpi/ec.h> +#include <northbridge/intel/nehalem/nehalem.h> +#include <southbridge/intel/bd82x6x/pch.h> #include "dock.h" +#include <drivers/intel/gma/int15.h> +#include <cpu/x86/lapic.h> +#include <drivers/lenovo/lenovo.h> + +static void fill_ssdt(struct device *device) +{ + drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB", 0); +} static void mainboard_enable(struct device *dev) { + dev->ops->acpi_fill_ssdt_generator = fill_ssdt; + + /* If we're resuming from suspend, blink suspend LED */ + if (acpi_is_wakeup_s3()) + ec_write(0x0c, 0xc7); + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_LFP, 2); diff --git a/src/mainboard/lenovo/t410/romstage.c b/src/mainboard/lenovo/t410/romstage.c index 7c796de..df4228b 100644 --- a/src/mainboard/lenovo/t410/romstage.c +++ b/src/mainboard/lenovo/t410/romstage.c @@ -19,11 +19,11 @@ #include <stdint.h> #include <device/pci_ops.h> #include <southbridge/intel/ibexpeak/pch.h> -#include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h> #include <northbridge/intel/nehalem/nehalem.h> const struct southbridge_usb_port mainboard_usb_ports[] = { /* Enabled, Current table lookup index, OC map */ + #if CONFIG(BOARD_LENOVO_T410) { 1, IF1_557, 0 }, { 1, IF1_55F, 1 }, { 1, IF1_74B, 3 }, @@ -38,8 +38,26 @@ { 1, IF1_74B, 7 }, { 1, IF1_557, 7 }, { 1, IF1_55F, 7 }, + #elif CONFIG(BOARD_LENOVO_X201) + { 1, IF1_557, 0 }, + { 1, IF1_55F, 1 }, + { 1, IF1_74B, 3 }, + { 1, IF1_74B, 3 }, + { 1, IF1_557, 3 }, + { 1, IF1_14B, 3 }, + { 1, IF1_74B, 3 }, + { 1, IF1_74B, 3 }, + { 1, IF1_74B, 4 }, + { 1, IF1_74B, 5 }, + { 1, IF1_55F, 7 }, + { 1, IF1_55F, 7 }, + { 1, IF1_557, 7 }, + { 1, IF1_55F, 7 }, + #endif }; +#if CONFIG(BOARD_LENOVO_T410) +#include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h> static void hybrid_graphics_init(void) { bool peg, igd; @@ -62,14 +80,38 @@ pci_write_config32(PCI_DEV(0, 0, 0), D0F0_DEVEN, reg32); } +#endif + +static void set_fsb_frequency(void) +{ + u8 block[5]; + u16 fsbfreq = 62879; + smbus_block_read(0x69, 0, 5, block); + block[0] = fsbfreq; + block[1] = fsbfreq >> 8; + + smbus_block_write(0x69, 0, 5, block); +} void mainboard_pre_raminit(void) { + #if CONFIG(BOARD_LENOVO_T410) hybrid_graphics_init(); + #elif CONFIG(BOARD_LENOVO_X201) + outb((inb(DEFAULT_GPIOBASE | 0x3a) & ~0x2) | 0x20, + DEFAULT_GPIOBASE | 0x3a); + outb(0x50, 0x15ec); + outb(inb(0x15ee) & 0x70, 0x15ee); + + set_fsb_frequency(); } void mainboard_get_spd_map(u8 *spd_addrmap) { spd_addrmap[0] = 0x50; + #if CONFIG(BOARD_LENOVO_T410) spd_addrmap[2] = 0x52; + #elif CONFIG(BOARD_LENOVO_X201) + spd_addrmap[2] = 0x51; + #endif } diff --git a/src/mainboard/lenovo/x201/board_info.txt b/src/mainboard/lenovo/t410/variants/t410/board_info.txt similarity index 75% copy from src/mainboard/lenovo/x201/board_info.txt copy to src/mainboard/lenovo/t410/variants/t410/board_info.txt index b33cbaf..f27808b 100644 --- a/src/mainboard/lenovo/x201/board_info.txt +++ b/src/mainboard/lenovo/t410/variants/t410/board_info.txt @@ -1,5 +1,5 @@ Category: laptop -ROM package: SOIC-8 +ROM package: SOIC-8 / WSON-8 ROM protocol: SPI ROM socketed: n Flashrom support: n diff --git a/src/mainboard/lenovo/t410/data.vbt b/src/mainboard/lenovo/t410/variants/t410/data.vbt similarity index 100% rename from src/mainboard/lenovo/t410/data.vbt rename to src/mainboard/lenovo/t410/variants/t410/data.vbt Binary files differ diff --git a/src/mainboard/lenovo/t410/devicetree.cb b/src/mainboard/lenovo/t410/variants/t410/devicetree.cb similarity index 100% rename from src/mainboard/lenovo/t410/devicetree.cb rename to src/mainboard/lenovo/t410/variants/t410/devicetree.cb diff --git a/src/mainboard/lenovo/t410/gpio.c b/src/mainboard/lenovo/t410/variants/t410/gpio.c similarity index 100% rename from src/mainboard/lenovo/t410/gpio.c rename to src/mainboard/lenovo/t410/variants/t410/gpio.c diff --git a/src/mainboard/lenovo/x201/board_info.txt b/src/mainboard/lenovo/t410/variants/x201/board_info.txt similarity index 81% rename from src/mainboard/lenovo/x201/board_info.txt rename to src/mainboard/lenovo/t410/variants/x201/board_info.txt index b33cbaf..7eb5a66 100644 --- a/src/mainboard/lenovo/x201/board_info.txt +++ b/src/mainboard/lenovo/t410/variants/x201/board_info.txt @@ -2,5 +2,5 @@ ROM package: SOIC-8 ROM protocol: SPI ROM socketed: n -Flashrom support: n +Flashrom support: y Release year: 2010 diff --git a/src/mainboard/lenovo/x201/data.vbt b/src/mainboard/lenovo/t410/variants/x201/data.vbt similarity index 100% rename from src/mainboard/lenovo/x201/data.vbt rename to src/mainboard/lenovo/t410/variants/x201/data.vbt Binary files differ diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/t410/variants/x201/devicetree.cb similarity index 100% rename from src/mainboard/lenovo/x201/devicetree.cb rename to src/mainboard/lenovo/t410/variants/x201/devicetree.cb diff --git a/src/mainboard/lenovo/x201/gpio.c b/src/mainboard/lenovo/t410/variants/x201/gpio.c similarity index 100% rename from src/mainboard/lenovo/x201/gpio.c rename to src/mainboard/lenovo/t410/variants/x201/gpio.c diff --git a/src/mainboard/lenovo/x201/Kconfig b/src/mainboard/lenovo/x201/Kconfig deleted file mode 100644 index e40c0d3..0000000 --- a/src/mainboard/lenovo/x201/Kconfig +++ /dev/null @@ -1,71 +0,0 @@ -if BOARD_LENOVO_X201 - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select SYSTEM_TYPE_LAPTOP - select NORTHBRIDGE_INTEL_NEHALEM - select SOUTHBRIDGE_INTEL_IBEXPEAK - select EC_LENOVO_PMH7 - select EC_LENOVO_H8 - select NO_UART_ON_SUPERIO - select HAVE_OPTION_TABLE - select HAVE_CMOS_DEFAULT - select BOARD_ROMSIZE_KB_8192 - select HAVE_ACPI_TABLES - select INTEL_INT15 - select HAVE_ACPI_RESUME - select MAINBOARD_HAS_LIBGFXINIT - select SUPERIO_NSC_PC87382 - select DRIVERS_LENOVO_WACOM - select MAINBOARD_HAS_LPC_TPM - select MAINBOARD_HAS_TPM1 - select INTEL_GMA_HAVE_VBT - select MAINBOARD_USES_IFD_GBE_REGION - select H8_HAS_BAT_TRESHOLDS_IMPL - -config VBOOT - select VBOOT_VBNV_CMOS - select GBB_FLAG_DISABLE_LID_SHUTDOWN - select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC - select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC - select GBB_FLAG_DISABLE_FWMP - select HAS_RECOVERY_MRC_CACHE - -config VBOOT_SLOTS_RW_A - default y - -config VBOOT_VBNV_OFFSET - hex - default 0x2a - -config FMDFILE - string - default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT - -config MAINBOARD_DIR - string - default lenovo/x201 - -config MAINBOARD_PART_NUMBER - string - default "ThinkPad X201" - -config USBDEBUG_HCD_INDEX - int - default 2 - -config DRAM_RESET_GATE_GPIO - int - default 10 - -config MAX_CPUS - int - default 4 - -# Without the Intel ME's EFFS partition some PCIe devices (like the USB and SATA -# controllers) don't work as expected -config ME_CLEANER_ARGS - string - default "-S -w EFFS" - -endif diff --git a/src/mainboard/lenovo/x201/Kconfig.name b/src/mainboard/lenovo/x201/Kconfig.name deleted file mode 100644 index a73d224..0000000 --- a/src/mainboard/lenovo/x201/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_LENOVO_X201 - bool "ThinkPad X201 / X201i / X201s / X201t" diff --git a/src/mainboard/lenovo/x201/Makefile.inc b/src/mainboard/lenovo/x201/Makefile.inc deleted file mode 100644 index 548beff..0000000 --- a/src/mainboard/lenovo/x201/Makefile.inc +++ /dev/null @@ -1,24 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007-2008 coresystems GmbH -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -bootblock-y += early_init.c - -smm-y += dock.c -smm-y += smihandler.c -romstage-y += dock.c -ramstage-y += dock.c -romstage-y += gpio.c - -ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/lenovo/x201/acpi/dock.asl b/src/mainboard/lenovo/x201/acpi/dock.asl deleted file mode 100644 index 2bba821..0000000 --- a/src/mainboard/lenovo/x201/acpi/dock.asl +++ /dev/null @@ -1,72 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Scope (\_SB) -{ - Device(DOCK) - { - Name(_HID, "ACPI0003") - Name(_UID, 0x00) - Name(_PCL, Package() { \_SB } ) - - Method(_DCK, 1, NotSerialized) - { - if (Arg0) { - /* connect dock */ - Store (1, \GP28) - Store (1, \_SB.PCI0.LPCB.EC.DKR1) - Store (1, \_SB.PCI0.LPCB.EC.DKR2) - Store (1, \_SB.PCI0.LPCB.EC.DKR3) - } else { - /* disconnect dock */ - Store (0, \GP28) - Store (0, \_SB.PCI0.LPCB.EC.DKR1) - Store (0, \_SB.PCI0.LPCB.EC.DKR2) - Store (0, \_SB.PCI0.LPCB.EC.DKR3) - } - Xor(Arg0, \_SB.PCI0.LPCB.EC.DKR1, Local0) - Return (Local0) - } - - Method(_STA, 0, NotSerialized) - { - Return (\_SB.PCI0.LPCB.EC.DKR1) - } - } -} - -Scope(\_SB.PCI0.LPCB.EC) -{ - Method(_Q18, 0, NotSerialized) - { - Notify(\_SB.DOCK, 3) - } - - Method(_Q45, 0, NotSerialized) - { - Notify(\_SB.DOCK, 3) - } - - Method(_Q58, 0, NotSerialized) - { - Notify(\_SB.DOCK, 0) - } - - Method(_Q37, 0, NotSerialized) - { - Notify(\_SB.DOCK, 0) - } -} diff --git a/src/mainboard/lenovo/x201/acpi/ec.asl b/src/mainboard/lenovo/x201/acpi/ec.asl deleted file mode 100644 index 411a0ec..0000000 --- a/src/mainboard/lenovo/x201/acpi/ec.asl +++ /dev/null @@ -1,24 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <ec/lenovo/h8/acpi/ec.asl> - -Scope(\_SB.PCI0.LPCB.EC) -{ -} - -#define H8_BAT_THRESHOLDS_BIT7 -#include <ec/lenovo/h8/acpi/thinkpad_bat_thresholds_24.asl> diff --git a/src/mainboard/lenovo/x201/acpi/gpe.asl b/src/mainboard/lenovo/x201/acpi/gpe.asl deleted file mode 100644 index 5c900ca..0000000 --- a/src/mainboard/lenovo/x201/acpi/gpe.asl +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Scope (\_GPE) -{ - Method(_L18, 0, NotSerialized) - { - /* Read EC register to clear wake status */ - Store(\_SB.PCI0.LPCB.EC.WAKE, Local0) - /* So that we don't get a warning that Local0 is unused. */ - Increment (Local0) - } -} diff --git a/src/mainboard/lenovo/x201/acpi/platform.asl b/src/mainboard/lenovo/x201/acpi/platform.asl deleted file mode 100644 index bcd6de6..0000000 --- a/src/mainboard/lenovo/x201/acpi/platform.asl +++ /dev/null @@ -1,132 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* The _PTS method (Prepare To Sleep) is called before the OS is - * entering a sleep state. The sleep state number is passed in Arg0 - */ - -Method(_PTS,1) -{ - \_SB.PCI0.LPCB.EC.MUTE(1) - \_SB.PCI0.LPCB.EC.USBP(0) - \_SB.PCI0.LPCB.EC.RADI(0) -} - -/* The _WAK method is called on system wakeup */ - -Method(_WAK,1) -{ - /* ME may not be up yet. */ - Store (0, \_TZ.MEB1) - Store (0, \_TZ.MEB2) - - /* Wake the HKEY to init BT/WWAN */ - \_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0) - - /* Not implemented. */ - Return(Package(){0,0}) -} - -Method(UCMS, 1, Serialized) -{ - Switch(ToInteger(Arg0)) - { - Case (0x0c) /* Turn on ThinkLight */ - { - \_SB.PCI0.LPCB.EC.LGHT(1) - } - Case (0x0d) /* Turn off ThinkLight */ - { - \_SB.PCI0.LPCB.EC.LGHT(0) - } - } -} - -/* System Bus */ - -Scope(\_SB) -{ - /* This method is placed on the top level, so we can make sure it's the - * first executed _INI method. - */ - Method(_INI, 0) - { - /* The DTS data in NVS is probably not up to date. - * Update temperature values and make sure AP thermal - * interrupts can happen - */ - - /* TRAP(71) */ /* TODO */ - - /* Determine the Operating System and save the value in OSYS. - * We have to do this in order to be able to work around - * certain windows bugs. - * - * OSYS value | Operating System - * -----------+------------------ - * 2000 | Windows 2000 - * 2001 | Windows XP(+SP1) - * 2002 | Windows XP SP2 - * 2006 | Windows Vista - * ???? | Windows 7 - */ - - /* Let's assume we're running at least Windows 2000 */ - Store (2000, OSYS) - - If (CondRefOf(_OSI)) { - If (_OSI("Windows 2001")) { - Store (2001, OSYS) - } - - If (_OSI("Windows 2001 SP1")) { - Store (2001, OSYS) - } - - If (_OSI("Windows 2001 SP2")) { - Store (2002, OSYS) - } - - If (_OSI("Windows 2001.1")) { - Store (2001, OSYS) - } - - If (_OSI("Windows 2001.1 SP1")) { - Store (2001, OSYS) - } - - If (_OSI("Windows 2006")) { - Store (2006, OSYS) - } - - If (_OSI("Windows 2006.1")) { - Store (2006, OSYS) - } - - If (_OSI("Windows 2006 SP1")) { - Store (2006, OSYS) - } - - If (_OSI("Windows 2009")) { - Store (2009, OSYS) - } - - If (_OSI("Windows 2012")) { - Store (2012, OSYS) - } - } - } -} diff --git a/src/mainboard/lenovo/x201/acpi/superio.asl b/src/mainboard/lenovo/x201/acpi/superio.asl deleted file mode 100644 index f2b35ba..0000000 --- a/src/mainboard/lenovo/x201/acpi/superio.asl +++ /dev/null @@ -1 +0,0 @@ -#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/lenovo/x201/acpi_tables.c b/src/mainboard/lenovo/x201/acpi_tables.c deleted file mode 100644 index 6fd47d7..0000000 --- a/src/mainboard/lenovo/x201/acpi_tables.c +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2013 Vladimir Serbinenko <phcoder(a)gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <southbridge/intel/ibexpeak/nvs.h> -#include "thermal.h" - -static void acpi_update_thermal_table(global_nvs_t *gnvs) -{ - gnvs->tcrt = CRITICAL_TEMPERATURE; - gnvs->tpsv = PASSIVE_TEMPERATURE; -} - -void acpi_create_gnvs(global_nvs_t * gnvs) -{ - acpi_update_thermal_table(gnvs); -} diff --git a/src/mainboard/lenovo/x201/cmos.default b/src/mainboard/lenovo/x201/cmos.default deleted file mode 100644 index 2cf484f..0000000 --- a/src/mainboard/lenovo/x201/cmos.default +++ /dev/null @@ -1,17 +0,0 @@ -boot_option=Fallback -debug_level=Debug -power_on_after_fail=Disable -nmi=Enable -volume=0x3 -first_battery=Primary -bluetooth=Enable -wwan=Enable -wlan=Enable -touchpad=Enable -trackpoint=Enable -fn_ctrl_swap=Disable -sticky_fn=Disable -power_management_beeps=Enable -low_battery_beep=Enable -sata_mode=AHCI -usb_always_on=Disable diff --git a/src/mainboard/lenovo/x201/cmos.layout b/src/mainboard/lenovo/x201/cmos.layout deleted file mode 100644 index 990db6d..0000000 --- a/src/mainboard/lenovo/x201/cmos.layout +++ /dev/null @@ -1,128 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007-2008 coresystems GmbH -## Copyright (C) 2013 Vladimir Serbinenko -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -# ----------------------------------------------------------------- -entries - -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused - -# ----------------------------------------------------------------- -# RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? - -# ----------------------------------------------------------------- -# coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused - -#400 8 r 0 reserved for century byte - -# coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail - -# coreboot config options: EC -411 1 e 8 first_battery -412 1 e 1 bluetooth -413 1 e 1 wwan -414 1 e 1 touchpad -415 1 e 1 wlan -416 1 e 1 trackpoint -417 1 e 1 fn_ctrl_swap -418 1 e 1 sticky_fn -419 1 e 1 power_management_beeps -420 1 e 1 low_battery_beep -421 1 e 9 sata_mode -422 2 e 11 usb_always_on -#423 1 r 1 unused - -# coreboot config options: northbridge -424 3 e 10 gfx_uma_size -#427 5 r 0 unused -432 8 h 0 volume - -# VBOOT -448 128 r 0 vbnv - -# coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved - -# ----------------------------------------------------------------- - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -8 0 Secondary -8 1 Primary -9 0 AHCI -9 1 Compatible -10 0 32M -10 1 48M -10 2 64M -10 3 128M -10 5 96M -10 6 160M -11 0 Disable -11 1 AC and battery -11 2 AC only - -# ----------------------------------------------------------------- -checksums - -checksum 392 415 984 diff --git a/src/mainboard/lenovo/x201/dock.c b/src/mainboard/lenovo/x201/dock.c deleted file mode 100644 index 58510ce..0000000 --- a/src/mainboard/lenovo/x201/dock.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> - * Copyright (C) 2013 Vladimir Serbinenko <phcoder(a)gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <device/device.h> -#include "dock.h" -#include <southbridge/intel/common/gpio.h> -#include <ec/lenovo/h8/h8.h> -#include <ec/acpi/ec.h> - -void init_dock(void) -{ - if (dock_present()) { - printk(BIOS_DEBUG, "dock is connected\n"); - dock_connect(); - } else - printk(BIOS_DEBUG, "dock is not connected\n"); -} - -void dock_connect(void) -{ - ec_set_bit(0x02, 0); - ec_set_bit(0x1a, 0); - ec_set_bit(0xfe, 4); - - set_gpio(28, GPIO_LEVEL_HIGH); -} - -void dock_disconnect(void) -{ - ec_clr_bit(0x02, 0); - ec_clr_bit(0x1a, 0); - ec_clr_bit(0xfe, 4); - - set_gpio(28, GPIO_LEVEL_LOW); -} - -int dock_present(void) -{ - const int dock_id_gpio[] = { 3, 4, 5, -1}; - - return get_gpios(dock_id_gpio) != 7; -} diff --git a/src/mainboard/lenovo/x201/dock.h b/src/mainboard/lenovo/x201/dock.h deleted file mode 100644 index 6a08d81..0000000 --- a/src/mainboard/lenovo/x201/dock.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef THINKPAD_X201_DOCK_H -#define THINKPAD_X201_DOCK_H -void init_dock(void); -void dock_connect(void); -void dock_disconnect(void); -int dock_present(void); -#endif diff --git a/src/mainboard/lenovo/x201/dsdt.asl b/src/mainboard/lenovo/x201/dsdt.asl deleted file mode 100644 index 9d0204e..0000000 --- a/src/mainboard/lenovo/x201/dsdt.asl +++ /dev/null @@ -1,94 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define THINKPAD_EC_GPE 17 -#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB -#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB -#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 -#define EC_LENOVO_H8_ME_WORKAROUND 1 - -#include <arch/acpi.h> -DefinitionBlock( - "dsdt.aml", - "DSDT", - 0x02, /* DSDT revision: ACPI v2.0 and up */ - OEM_ID, - ACPI_TABLE_CREATOR, - 0x20130325 /* OEM revision */ -) -{ - #include <southbridge/intel/common/acpi/platform.asl> - - /* Some generic macros */ - #include "acpi/platform.asl" - - /* global NVS and variables */ - #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> - - /* General Purpose Events */ - #include "acpi/gpe.asl" - - #include <cpu/intel/common/acpi/cpu.asl> - - Scope (\_SB) { - Device (PCI0) - { - #include <northbridge/intel/nehalem/acpi/nehalem.asl> - #include <southbridge/intel/bd82x6x/acpi/pch.asl> - - #include <drivers/intel/gma/acpi/default_brightness_levels.asl> - } - Device (UNCR) - { - Name (_BBN, 0xFF) - Name (RID, 0x00) - Name (_HID, EisaId ("PNP0A03")) - Name (_CRS, ResourceTemplate () - { - WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0x0000, /* Granularity */ - 0x00FF, /* Range Minimum */ - 0x00FF, /* Range Maximum */ - 0x0000, /* Translation Offset */ - 0x0001, /* Length */ - ,, ) - }) - Device (SAD) - { - Name (_ADR, 0x01) - Name (RID, 0x00) - OperationRegion (SADC, PCI_Config, 0x00, 0x0100) - Field (SADC, DWordAcc, NoLock, Preserve) - { - Offset (0x40), - PAM0, 8, - PAM1, 8, - PAM2, 8, - PAM3, 8, - PAM4, 8, - PAM5, 8, - PAM6, 8 - } - } - } - } - - /* Chipset specific sleep states */ - #include <southbridge/intel/common/acpi/sleepstates.asl> - - /* Dock support code */ - #include "acpi/dock.asl" -} diff --git a/src/mainboard/lenovo/x201/early_init.c b/src/mainboard/lenovo/x201/early_init.c deleted file mode 100644 index 7383381..0000000 --- a/src/mainboard/lenovo/x201/early_init.c +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> - * Copyright (C) 2013 Vladimir Serbinenko <phcoder(a)gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <bootblock_common.h> -#include <ec/acpi/ec.h> - -void bootblock_mainboard_early_init(void) -{ - /* Enable USB Power. We need to do it early for usbdebug to work. */ - ec_set_bit(0x3b, 4); -} diff --git a/src/mainboard/lenovo/x201/gma-mainboard.ads b/src/mainboard/lenovo/x201/gma-mainboard.ads deleted file mode 100644 index 9c2a3cb..0000000 --- a/src/mainboard/lenovo/x201/gma-mainboard.ads +++ /dev/null @@ -1,30 +0,0 @@ --- --- This file is part of the coreboot project. --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- - -with HW.GFX.GMA; -with HW.GFX.GMA.Display_Probing; - -use HW.GFX.GMA; -use HW.GFX.GMA.Display_Probing; - -private package GMA.Mainboard is - - ports : constant Port_List := - (DP2, -- DP++ connector on the dock - HDMI2, - Analog, - Internal, - others => Disabled); - -end GMA.Mainboard; diff --git a/src/mainboard/lenovo/x201/hda_verb.c b/src/mainboard/lenovo/x201/hda_verb.c deleted file mode 100644 index 820e2c5..0000000 --- a/src/mainboard/lenovo/x201/hda_verb.c +++ /dev/null @@ -1,77 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Vladimir Serbinenko. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License, - * or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/azalia_device.h> - -const u32 cim_verb_data[] = { - /* coreboot specific header */ - 0x14F15069, /* Codec Vendor / Device ID: Conexant CX20585 */ - 0x17AA2155, /* Subsystem ID */ - 0x0000000B, /* Number of 4 dword sets */ - - /* NID 0x01: Subsystem ID. */ - AZALIA_SUBVENDOR(0x0, 0x17AA2155), - - /* NID 0x19: Headphone jack. */ - AZALIA_PIN_CFG(0x0, 0x19, 0x042140F0), - - /* NID 0x1A: Dock mic jack. */ - AZALIA_PIN_CFG(0x0, 0x1A, 0x61A190F0), - - /* NID 0x1B: Mic jack. */ - AZALIA_PIN_CFG(0x0, 0x1B, 0x04A190F0), - - /* NID 0x1C: Dock headphone jack. */ - AZALIA_PIN_CFG(0x0, 0x1C, 0x612140F0), - - /* NID 0x1D: EAPD detect. */ - AZALIA_PIN_CFG(0x0, 0x1D, 0x601700F0), - - /* NID 0x1E */ - AZALIA_PIN_CFG(0x0, 0x1E, 0x40F001F0), - - /* NID 0x1F */ - AZALIA_PIN_CFG(0x0, 0x1F, 0x901701F0), - - /* NID 0x20 */ - AZALIA_PIN_CFG(0x0, 0x20, 0x40F001F0), - - /* NID 0x22 */ - AZALIA_PIN_CFG(0x0, 0x22, 0x40F001F0), - - /* NID 0x23: Internal mic boost volume. */ - AZALIA_PIN_CFG(0x0, 0x23, 0x90A601F0), - - 0x80862804, /* Codec Vendor / Device ID: Intel Ibexpeak HDMI. */ - 0x17aa21b5, /* Subsystem ID */ - 0x00000004, /* Number of 4 dword sets */ - - /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x17aa21b5 */ - AZALIA_SUBVENDOR(0x3, 0x17AA21B5), - - /* NID 0x04. */ - AZALIA_PIN_CFG(0x3, 0x04, 0x58560010), - - /* NID 0x05. */ - AZALIA_PIN_CFG(0x3, 0x05, 0x18560020), - - /* NID 0x06. */ - AZALIA_PIN_CFG(0x3, 0x06, 0x58560030), -}; - -const u32 pc_beep_verbs[0] = {}; - -AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/lenovo/x201/mainboard.c b/src/mainboard/lenovo/x201/mainboard.c deleted file mode 100644 index a403237..0000000 --- a/src/mainboard/lenovo/x201/mainboard.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> - * Copyright (C) 2013 Vladimir Serbinenko <phcoder(a)gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/device.h> -#include <device/pci_ops.h> -#include <ec/acpi/ec.h> -#include <northbridge/intel/nehalem/nehalem.h> -#include <southbridge/intel/bd82x6x/pch.h> -#include "dock.h" -#include <drivers/intel/gma/int15.h> -#include <cpu/x86/lapic.h> -#include <drivers/lenovo/lenovo.h> - -static void fill_ssdt(struct device *device) -{ - drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB", 0); -} - -static void mainboard_enable(struct device *dev) -{ - dev->ops->acpi_fill_ssdt_generator = fill_ssdt; - - /* If we're resuming from suspend, blink suspend LED */ - if (acpi_is_wakeup_s3()) - ec_write(0x0c, 0xc7); - - install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, - GMA_INT15_PANEL_FIT_DEFAULT, - GMA_INT15_BOOT_DISPLAY_LFP, 2); - - init_dock(); -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c deleted file mode 100644 index 99875ed..0000000 --- a/src/mainboard/lenovo/x201/romstage.c +++ /dev/null @@ -1,70 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> - * Copyright (C) 2013 Vladimir Serbinenko <phcoder(a)gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <arch/io.h> -#include <device/pci_ops.h> -#include <ec/acpi/ec.h> - -#include <southbridge/intel/ibexpeak/pch.h> -#include <northbridge/intel/nehalem/nehalem.h> - -const struct southbridge_usb_port mainboard_usb_ports[] = { - /* Enabled, Current table lookup index, OC map */ - { 1, IF1_557, 0 }, - { 1, IF1_55F, 1 }, - { 1, IF1_74B, 3 }, - { 1, IF1_74B, 3 }, - { 1, IF1_557, 3 }, - { 1, IF1_14B, 3 }, - { 1, IF1_74B, 3 }, - { 1, IF1_74B, 3 }, - { 1, IF1_74B, 4 }, - { 1, IF1_74B, 5 }, - { 1, IF1_55F, 7 }, - { 1, IF1_55F, 7 }, - { 1, IF1_557, 7 }, - { 1, IF1_55F, 7 }, -}; - -static void set_fsb_frequency(void) -{ - u8 block[5]; - u16 fsbfreq = 62879; - smbus_block_read(0x69, 0, 5, block); - block[0] = fsbfreq; - block[1] = fsbfreq >> 8; - - smbus_block_write(0x69, 0, 5, block); -} - -void mainboard_pre_raminit(void) -{ - outb((inb(DEFAULT_GPIOBASE | 0x3a) & ~0x2) | 0x20, - DEFAULT_GPIOBASE | 0x3a); - outb(0x50, 0x15ec); - outb(inb(0x15ee) & 0x70, 0x15ee); - - set_fsb_frequency(); -} - -void mainboard_get_spd_map(u8 *spd_addrmap) -{ - spd_addrmap[0] = 0x50; - spd_addrmap[2] = 0x51; -} diff --git a/src/mainboard/lenovo/x201/smihandler.c b/src/mainboard/lenovo/x201/smihandler.c deleted file mode 100644 index 4ba10b4..0000000 --- a/src/mainboard/lenovo/x201/smihandler.c +++ /dev/null @@ -1,110 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <console/console.h> -#include <cpu/x86/smm.h> -#include <southbridge/intel/ibexpeak/nvs.h> -#include <southbridge/intel/common/pmutil.h> -#include <northbridge/intel/nehalem/nehalem.h> -#include <ec/acpi/ec.h> -#include <ec/lenovo/h8/h8.h> -#include <delay.h> -#include "dock.h" - -#define GPE_EC_SCI 1 -#define GPE_EC_WAKE 13 - -static void mainboard_smi_handle_ec_sci(void) -{ - u8 status = inb(EC_SC); - u8 event; - - if (!(status & EC_SCI_EVT)) - return; - - event = ec_query(); - printk(BIOS_DEBUG, "EC event %02x\n", event); - - switch (event) { - case 0x18: - /* Fn-F9 key */ - case 0x27: - /* Power loss */ - case 0x50: - /* Undock Key */ - ec_clr_bit(0x03, 2); - dock_disconnect(); - break; - case 0x37: - case 0x58: - /* Dock Event */ - ec_clr_bit(0x03, 2); - udelay(250000); - dock_connect(); - ec_set_bit(0x03, 2); - /* set dock LED to indicate status */ - ec_write(0x0c, 0x09); - ec_write(0x0c, 0x88); - break; - default: - break; - } -} - -void mainboard_smi_gpi(u32 gpi_sts) -{ - if (gpi_sts & (1 << GPE_EC_SCI)) - mainboard_smi_handle_ec_sci(); -} - -int mainboard_smi_apmc(u8 data) -{ - switch (data) { - case APM_CNT_ACPI_ENABLE: - /* use 0x1600/0x1604 to prevent races with userspace */ - ec_set_ports(0x1604, 0x1600); - /* route H8SCI to SCI */ - gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SCI); - /* discard all events, and enable attention */ - ec_write(0x80, 0x01); - break; - case APM_CNT_ACPI_DISABLE: - /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't - provide a EC query function */ - ec_set_ports(0x66, 0x62); - /* route H8SCI# to SMI */ - gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SMI); - /* discard all events, and enable attention */ - ec_write(0x80, 0x01); - break; - default: - break; - } - return 0; -} - -void mainboard_smi_sleep(u8 slp_typ) -{ - if (slp_typ == 3) { - u8 ec_wake = ec_read(0x32); - /* If EC wake events are enabled, enable wake on EC WAKE GPE. */ - if (ec_wake & 0x14) { - /* Redirect EC WAKE GPE to SCI. */ - gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI); - } - } -} diff --git a/src/mainboard/lenovo/x201/thermal.h b/src/mainboard/lenovo/x201/thermal.h deleted file mode 100644 index 72953fd..0000000 --- a/src/mainboard/lenovo/x201/thermal.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko - * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> - * Copyright (C) 2017 James Ye <jye836(a)gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MAINBOARD_THERMAL_H -#define MAINBOARD_THERMAL_H - -/* Temperature which OS will shutdown at */ -#define CRITICAL_TEMPERATURE 100 - -/* Temperature which OS will throttle CPU */ -#define PASSIVE_TEMPERATURE 90 - -#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/x201/vboot-rwa.fmd b/src/mainboard/lenovo/x201/vboot-rwa.fmd deleted file mode 100644 index 0d1aa5d..0000000 --- a/src/mainboard/lenovo/x201/vboot-rwa.fmd +++ /dev/null @@ -1,30 +0,0 @@ -FLASH@0xff800000 0x800000 { - SI_ALL@0x0 0x500000 { - SI_DESC@0x0 0x1000 - SI_GBE@0x1000 0x2000 - SI_ME@0x3000 0x4ed000 - } - SI_BIOS@0x500000 0x300000 { - RW_SECTION_A 0x180000 { - VBLOCK_A 0x10000 - FW_MAIN_A(CBFS) - RW_FWID_A 0x40 - } - UNIFIED_MRC_CACHE 0x20000 { - RECOVERY_MRC_CACHE 0x10000 - RW_MRC_CACHE 0x10000 - } - RW_VPD(PRESERVE) 0x1000 - SMMSTORE(PRESERVE) 0x40000 - WP_RO { - RO_VPD(PRESERVE) 0x1000 - RO_SECTION { - FMAP 0x800 - RO_FRID 0x40 - RO_PADDING 0x7c0 - GBB 0x1e000 - COREBOOT(CBFS) - } - } - } -} -- To view, visit https://review.coreboot.org/c/coreboot/+/36871 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icfa1818812347ceb4e2de5cc4a3130537a4e13e7 Gerrit-Change-Number: 36871 Gerrit-PatchSet: 1 Gerrit-Owner: Maccraft123 <maccraft123mc(a)gmail.com> Gerrit-MessageType: newchange

5 36

Change in coreboot[master]: [NOTFORMERGE]mb/*/*: Drop BINARYPI_LEGACY_WRAPPER boards
by Arthur Heymans (Code Review) 07 Aug '23

07 Aug '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37076 ) Change subject: [NOTFORMERGE]mb/*/*: Drop BINARYPI_LEGACY_WRAPPER boards ...................................................................... [NOTFORMERGE]mb/*/*: Drop BINARYPI_LEGACY_WRAPPER boards Change-Id: Ia3ffc6ef36bc42f58515dfb2674633c167c732fd Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- D src/mainboard/amd/bettong/BiosCallOuts.c D src/mainboard/amd/bettong/BiosCallOuts.h D src/mainboard/amd/bettong/Kconfig D src/mainboard/amd/bettong/Kconfig.name D src/mainboard/amd/bettong/Makefile.inc D src/mainboard/amd/bettong/OemCustomize.c D src/mainboard/amd/bettong/README D src/mainboard/amd/bettong/acpi/carrizo_fch.asl D src/mainboard/amd/bettong/acpi/gpe.asl D src/mainboard/amd/bettong/acpi/mainboard.asl D src/mainboard/amd/bettong/acpi/routing.asl D src/mainboard/amd/bettong/acpi/sleep.asl D src/mainboard/amd/bettong/acpi/usb_oc.asl D src/mainboard/amd/bettong/acpi_tables.c D src/mainboard/amd/bettong/board_info.txt D src/mainboard/amd/bettong/boardid.c D src/mainboard/amd/bettong/cmos.layout D src/mainboard/amd/bettong/devicetree.cb D src/mainboard/amd/bettong/dsdt.asl D src/mainboard/amd/bettong/fchec.c D src/mainboard/amd/bettong/irq_tables.c D src/mainboard/amd/bettong/mainboard.c D src/mainboard/amd/bettong/mptable.c D src/mainboard/amd/bettong/romstage.c D src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c D src/mainboard/amd/db-ft3b-lc/Kconfig D src/mainboard/amd/db-ft3b-lc/Kconfig.name D src/mainboard/amd/db-ft3b-lc/Makefile.inc D src/mainboard/amd/db-ft3b-lc/Memphis_MEM4G16D3EABG.spd.hex D src/mainboard/amd/db-ft3b-lc/OemCustomize.c D src/mainboard/amd/db-ft3b-lc/acpi/gpe.asl D src/mainboard/amd/db-ft3b-lc/acpi/ide.asl D src/mainboard/amd/db-ft3b-lc/acpi/mainboard.asl D src/mainboard/amd/db-ft3b-lc/acpi/routing.asl D src/mainboard/amd/db-ft3b-lc/acpi/si.asl D src/mainboard/amd/db-ft3b-lc/acpi/sleep.asl D src/mainboard/amd/db-ft3b-lc/acpi/thermal.asl D src/mainboard/amd/db-ft3b-lc/acpi/usb_oc.asl D src/mainboard/amd/db-ft3b-lc/acpi_tables.c D src/mainboard/amd/db-ft3b-lc/board_info.txt D src/mainboard/amd/db-ft3b-lc/cmos.layout D src/mainboard/amd/db-ft3b-lc/devicetree.cb D src/mainboard/amd/db-ft3b-lc/dsdt.asl D src/mainboard/amd/db-ft3b-lc/irq_tables.c D src/mainboard/amd/db-ft3b-lc/mainboard.c D src/mainboard/amd/db-ft3b-lc/mptable.c D src/mainboard/amd/db-ft3b-lc/romstage.c D src/mainboard/amd/lamar/BiosCallOuts.c D src/mainboard/amd/lamar/Kconfig D src/mainboard/amd/lamar/Kconfig.name D src/mainboard/amd/lamar/Makefile.inc D src/mainboard/amd/lamar/OemCustomize.c D src/mainboard/amd/lamar/acpi/gpe.asl D src/mainboard/amd/lamar/acpi/mainboard.asl D src/mainboard/amd/lamar/acpi/routing.asl D src/mainboard/amd/lamar/acpi/si.asl D src/mainboard/amd/lamar/acpi/sleep.asl D src/mainboard/amd/lamar/acpi/thermal.asl D src/mainboard/amd/lamar/acpi/usb_oc.asl D src/mainboard/amd/lamar/acpi_tables.c D src/mainboard/amd/lamar/board_info.txt D src/mainboard/amd/lamar/cmos.layout D src/mainboard/amd/lamar/devicetree.cb D src/mainboard/amd/lamar/dsdt.asl D src/mainboard/amd/lamar/irq_tables.c D src/mainboard/amd/lamar/mainboard.c D src/mainboard/amd/lamar/mptable.c D src/mainboard/amd/lamar/romstage.c D src/mainboard/amd/olivehillplus/BiosCallOuts.c D src/mainboard/amd/olivehillplus/Kconfig D src/mainboard/amd/olivehillplus/Kconfig.name D src/mainboard/amd/olivehillplus/Makefile.inc D src/mainboard/amd/olivehillplus/OemCustomize.c D src/mainboard/amd/olivehillplus/acpi/gpe.asl D src/mainboard/amd/olivehillplus/acpi/ide.asl D src/mainboard/amd/olivehillplus/acpi/mainboard.asl D src/mainboard/amd/olivehillplus/acpi/routing.asl D src/mainboard/amd/olivehillplus/acpi/si.asl D src/mainboard/amd/olivehillplus/acpi/sleep.asl D src/mainboard/amd/olivehillplus/acpi/thermal.asl D src/mainboard/amd/olivehillplus/acpi/usb_oc.asl D src/mainboard/amd/olivehillplus/acpi_tables.c D src/mainboard/amd/olivehillplus/board_info.txt D src/mainboard/amd/olivehillplus/cmos.layout D src/mainboard/amd/olivehillplus/devicetree.cb D src/mainboard/amd/olivehillplus/dsdt.asl D src/mainboard/amd/olivehillplus/irq_tables.c D src/mainboard/amd/olivehillplus/mainboard.c D src/mainboard/amd/olivehillplus/mptable.c D src/mainboard/amd/olivehillplus/romstage.c D src/mainboard/bap/ode_e21XX/BAP_Q7_1066.spd.hex D src/mainboard/bap/ode_e21XX/BAP_Q7_1333.spd.hex D src/mainboard/bap/ode_e21XX/BAP_Q7_800.spd.hex D src/mainboard/bap/ode_e21XX/BiosCallOuts.c D src/mainboard/bap/ode_e21XX/Kconfig D src/mainboard/bap/ode_e21XX/Kconfig.name D src/mainboard/bap/ode_e21XX/Makefile.inc D src/mainboard/bap/ode_e21XX/OemCustomize.c D src/mainboard/bap/ode_e21XX/acpi/gpe.asl D src/mainboard/bap/ode_e21XX/acpi/ide.asl D src/mainboard/bap/ode_e21XX/acpi/mainboard.asl D src/mainboard/bap/ode_e21XX/acpi/routing.asl D src/mainboard/bap/ode_e21XX/acpi/si.asl D src/mainboard/bap/ode_e21XX/acpi/sleep.asl D src/mainboard/bap/ode_e21XX/acpi/superio.asl D src/mainboard/bap/ode_e21XX/acpi/thermal.asl D src/mainboard/bap/ode_e21XX/acpi/usb_oc.asl D src/mainboard/bap/ode_e21XX/acpi_tables.c D src/mainboard/bap/ode_e21XX/board_info.txt D src/mainboard/bap/ode_e21XX/cmos.layout D src/mainboard/bap/ode_e21XX/devicetree.cb D src/mainboard/bap/ode_e21XX/dsdt.asl D src/mainboard/bap/ode_e21XX/irq_tables.c D src/mainboard/bap/ode_e21XX/mainboard.c D src/mainboard/bap/ode_e21XX/mptable.c D src/mainboard/bap/ode_e21XX/romstage.c D src/mainboard/pcengines/apu2/BiosCallOuts.c D src/mainboard/pcengines/apu2/Kconfig D src/mainboard/pcengines/apu2/Kconfig.name D src/mainboard/pcengines/apu2/Makefile.inc D src/mainboard/pcengines/apu2/OemCustomize.c D src/mainboard/pcengines/apu2/acpi/gpe.asl D src/mainboard/pcengines/apu2/acpi/mainboard.asl D src/mainboard/pcengines/apu2/acpi/routing.asl D src/mainboard/pcengines/apu2/acpi/si.asl D src/mainboard/pcengines/apu2/acpi/sleep.asl D src/mainboard/pcengines/apu2/acpi/usb_oc.asl D src/mainboard/pcengines/apu2/acpi_tables.c D src/mainboard/pcengines/apu2/board_info.txt D src/mainboard/pcengines/apu2/cmos.layout D src/mainboard/pcengines/apu2/dsdt.asl D src/mainboard/pcengines/apu2/gpio_ftns.c D src/mainboard/pcengines/apu2/gpio_ftns.h D src/mainboard/pcengines/apu2/irq_tables.c D src/mainboard/pcengines/apu2/mainboard.c D src/mainboard/pcengines/apu2/mptable.c D src/mainboard/pcengines/apu2/romstage.c D src/mainboard/pcengines/apu2/spd/HYNIX-2G-1333.spd.hex D src/mainboard/pcengines/apu2/spd/HYNIX-4G-1333-ECC.spd.hex D src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb D src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb D src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb D src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb 143 files changed, 0 insertions(+), 12,816 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/37076/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/37076 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia3ffc6ef36bc42f58515dfb2674633c167c732fd Gerrit-Change-Number: 37076 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-MessageType: newchange

2 1

Change in coreboot[master]: mb/google/octopus: test
by Regan Chang (Code Review) 07 Aug '23

07 Aug '23

Regan Chang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37268 ) Change subject: mb/google/octopus: test ...................................................................... mb/google/octopus: test Create new variant for Lick . Nothing is changed in the variant files. Signed-off-by: Regan Chang <regan.chang(a)lcfc.corp-partner.google.com> Change-Id: I6b1a79b022a0c698174dd08f3c11769a4fd6833c --- A compile.status M src/mainboard/google/octopus/Kconfig M src/mainboard/google/octopus/Kconfig.name A src/mainboard/google/octopus/variants/lick/Makefile.inc A src/mainboard/google/octopus/variants/lick/gpio.c A src/mainboard/google/octopus/variants/lick/include/variant/acpi/dptf.asl A src/mainboard/google/octopus/variants/lick/include/variant/ec.h A src/mainboard/google/octopus/variants/lick/include/variant/gpio.h A src/mainboard/google/octopus/variants/lick/mainboard.c A src/mainboard/google/octopus/variants/lick/overridetree.cb A src/mainboard/google/octopus/variants/lick/variant.c 11 files changed, 408 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/37268/1 diff --git a/compile.status b/compile.status new file mode 100644 index 0000000..74bb638 --- /dev/null +++ b/compile.status @@ -0,0 +1 @@ +failed diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig index 65a641b..f97b66d 100644 --- a/src/mainboard/google/octopus/Kconfig +++ b/src/mainboard/google/octopus/Kconfig @@ -63,6 +63,7 @@ default "octopus" if BOARD_GOOGLE_OCTOPUS default "garg" if BOARD_GOOGLE_GARG default "dood" if BOARD_GOOGLE_DOOD + default "lick" if BOARD_GOOGLE_LICK config DEVICETREE string @@ -85,6 +86,7 @@ default "Octopus" if BOARD_GOOGLE_OCTOPUS default "Garg" if BOARD_GOOGLE_GARG default "Dood" if BOARD_GOOGLE_DOOD + default "Lick" if BOARD_GOOGLE_LICK config MAINBOARD_FAMILY string @@ -119,6 +121,7 @@ default y if BOARD_GOOGLE_OCTOPUS default y if BOARD_GOOGLE_PHASER default y if BOARD_GOOGLE_YORP + default y if BOARD_GOOGLE_LICK config DRAM_PART_IN_CBI_BOARD_ID_MIN int @@ -129,5 +132,6 @@ default 3 if BOARD_GOOGLE_BOBBA default 1 if BOARD_GOOGLE_MEEP default 255 if BOARD_GOOGLE_OCTOPUS + default 2 if BOARD_GOOGLE_LICK endif # BOARD_GOOGLE_OCTOPUS diff --git a/src/mainboard/google/octopus/Kconfig.name b/src/mainboard/google/octopus/Kconfig.name index 8a8d339..b1f589d 100644 --- a/src/mainboard/google/octopus/Kconfig.name +++ b/src/mainboard/google/octopus/Kconfig.name @@ -64,3 +64,9 @@ select BASEBOARD_OCTOPUS_LAPTOP select BOARD_GOOGLE_BASEBOARD_OCTOPUS select NHLT_DA7219 if INCLUDE_NHLT_BLOBS + +config BOARD_GOOGLE_LICK + bool "-> Lick" + select BASEBOARD_OCTOPUS_LAPTOP + select BOARD_GOOGLE_BASEBOARD_OCTOPUS + select NHLT_DA7219 if INCLUDE_NHLT_BLOBS diff --git a/src/mainboard/google/octopus/variants/lick/Makefile.inc b/src/mainboard/google/octopus/variants/lick/Makefile.inc new file mode 100644 index 0000000..37270eb --- /dev/null +++ b/src/mainboard/google/octopus/variants/lick/Makefile.inc @@ -0,0 +1,5 @@ +bootblock-y += gpio.c + +ramstage-y += variant.c +ramstage-y += gpio.c +ramstage-y += mainboard.c diff --git a/src/mainboard/google/octopus/variants/lick/gpio.c b/src/mainboard/google/octopus/variants/lick/gpio.c new file mode 100644 index 0000000..281bde0 --- /dev/null +++ b/src/mainboard/google/octopus/variants/lick/gpio.c @@ -0,0 +1,90 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <boardid.h> +#include <gpio.h> +#include <soc/gpio.h> +#include <ec/google/chromeec/ec.h> + +#define SKU_UNKNOWN 0xFFFFFFFF + +static const struct pad_config default_override_table[] = { + PAD_NC(GPIO_52, UP_20K), + PAD_NC(GPIO_53, UP_20K), + PAD_NC(GPIO_67, UP_20K), + PAD_NC(GPIO_117, UP_20K), + PAD_NC(GPIO_143, UP_20K), + + /* EN_PP3300_TOUCHSCREEN */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 0, DEEP, NONE, Tx0RxDCRx0, + DISPUPD), + + PAD_NC(GPIO_161, DN_20K), + + PAD_NC(GPIO_213, DN_20K), + PAD_NC(GPIO_214, DN_20K), +}; + +static const struct pad_config sku1_default_override_table[] = { + /* disable I2C7 SCL and SDA */ + PAD_NC(GPIO_114, UP_20K), /* LPSS_I2C7_SDA */ + PAD_NC(GPIO_115, UP_20K), /* LPSS_I2C7_SCL */ + + PAD_NC(GPIO_52, UP_20K), + PAD_NC(GPIO_53, UP_20K), + PAD_NC(GPIO_67, UP_20K), + PAD_NC(GPIO_117, UP_20K), + PAD_NC(GPIO_143, UP_20K), + + /* EN_PP3300_TOUCHSCREEN */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 0, DEEP, NONE, Tx0RxDCRx0, + DISPUPD), + + PAD_NC(GPIO_161, DN_20K), + + /* EN_PP3300_WLAN_L */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_178, 0, DEEP, NONE, Tx0RxDCRx0, + DISPUPD), + + PAD_NC(GPIO_213, DN_20K), + PAD_NC(GPIO_214, DN_20K), +}; + +bool no_touchscreen_sku(uint32_t sku_id) +{ + if ((sku_id == 1) || (sku_id == 6)) + return true; + else + return false; +} + +const struct pad_config *variant_override_gpio_table(size_t *num) +{ + const struct pad_config *c; + uint32_t sku_id = SKU_UNKNOWN; + + google_chromeec_cbi_get_sku_id(&sku_id); + if (no_touchscreen_sku(sku_id)) { + c = sku1_default_override_table; + *num = ARRAY_SIZE(sku1_default_override_table); + } else { + c = default_override_table; + *num = ARRAY_SIZE(default_override_table); + } + + return c; +} diff --git a/src/mainboard/google/octopus/variants/lick/include/variant/acpi/dptf.asl b/src/mainboard/google/octopus/variants/lick/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..cc17d56 --- /dev/null +++ b/src/mainboard/google/octopus/variants/lick/include/variant/acpi/dptf.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/acpi/dptf.asl> diff --git a/src/mainboard/google/octopus/variants/lick/include/variant/ec.h b/src/mainboard/google/octopus/variants/lick/include/variant/ec.h new file mode 100644 index 0000000..16f931b --- /dev/null +++ b/src/mainboard/google/octopus/variants/lick/include/variant/ec.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/octopus/variants/lick/include/variant/gpio.h b/src/mainboard/google/octopus/variants/lick/include/variant/gpio.h new file mode 100644 index 0000000..1fd1e11 --- /dev/null +++ b/src/mainboard/google/octopus/variants/lick/include/variant/gpio.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include <baseboard/gpio.h> + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/octopus/variants/lick/mainboard.c b/src/mainboard/google/octopus/variants/lick/mainboard.c new file mode 100644 index 0000000..2d44830 --- /dev/null +++ b/src/mainboard/google/octopus/variants/lick/mainboard.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <boardid.h> +#include <ec/google/chromeec/ec.h> +#include <sar.h> + +const char *get_wifi_sar_cbfs_filename(void) +{ + const char *filename = NULL; + uint32_t sku_id; + + if (google_chromeec_cbi_get_sku_id(&sku_id)) + return NULL; + + if (sku_id == 5) + filename = "wifi_sar-laser.hex"; + + return filename; +} diff --git a/src/mainboard/google/octopus/variants/lick/overridetree.cb b/src/mainboard/google/octopus/variants/lick/overridetree.cb new file mode 100644 index 0000000..625c2a6 --- /dev/null +++ b/src/mainboard/google/octopus/variants/lick/overridetree.cb @@ -0,0 +1,176 @@ +chip soc/intel/apollolake + + # EMMC Tx CMD Delay + # Refer to EDS-Vol2-16.32. + # [14:8] steps of delay for DDR mode, each 125ps. + # [6:0] steps of delay for SDR mode, each 125ps. + register "emmc_tx_cmd_cntl" = "0x505" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-16.33. + # [14:8] steps of delay for HS400, each 125ps. + # [6:0] steps of delay for SDR104/HS200, each 125ps. + register "emmc_tx_data_cntl1" = "0x0b0c" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-16.34. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_tx_data_cntl2" = "0x1c282929" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-16.35. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_rx_cmd_data_cntl1" = "0x00181b1b" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-16.37. + # [17:16] stands for Rx Clock before Output Buffer + # [14:8] steps of delay for Auto Tuning Mode, each 125ps. + # [6:0] steps of delay for HS200, each 125ps. + register "emmc_rx_cmd_data_cntl2" = "0x10028" + + # EMMC Rx Strobe Delay + # Refer to EDS-Vol2-16.36. + # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps. + # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps. + register "emmc_rx_strobe_cntl" = "0x0b0b" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | Digitizer | + #| I2C5 | Audio | + #| I2C6 | Trackpad | + #| I2C7 | Touchscreen | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 66, + .fall_time_ns = 90, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 104, + .fall_time_ns = 52, + }, + .i2c[6] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 66, + .fall_time_ns = 90, + .data_hold_time_ns = 350, + }, + .i2c[7] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 76, + .fall_time_ns = 164, + }, + }" + + device domain 0 on + device pci 16.0 on + chip drivers/i2c/hid + register "generic.hid" = ""WCOM50C1"" + register "generic.desc" = ""WCOM Digitizer"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_139_IRQ)" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" + register "generic.reset_delay_ms" = "20" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x1" + device i2c 0x9 on end + end + end # - I2C 0 + device pci 17.1 on + chip drivers/i2c/da7219 + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_137_IRQ)" + register "btn_cfg" = "50" + register "mic_det_thr" = "500" + register "jack_ins_deb" = "20" + register "jack_det_rate" = ""32ms_64ms"" + register "jack_rem_deb" = "1" + register "a_d_btn_thr" = "0xa" + register "d_b_btn_thr" = "0x16" + register "b_c_btn_thr" = "0x21" + register "c_mic_btn_thr" = "0x3e" + register "btn_avg" = "4" + register "adc_1bit_rpt" = "1" + register "micbias_lvl" = "2600" + register "mic_amp_in_sel" = ""diff"" + device i2c 1a on end + end + end # - I2C 5 + device pci 17.2 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPIO_135_IRQ)" + register "wake" = "GPE0_DW3_27" + register "probed" = "1" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPIO_135_IRQ)" + register "generic.wake" = "GPE0_DW3_27" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 0x2c on end + end + end # - I2C 6 + device pci 17.3 on + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" + register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" + register "reset_delay_ms" = "20" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" + register "enable_delay_ms" = "1" + register "has_power_resource" = "1" + device i2c 10 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""SYTS7817"" + register "generic.desc" = ""Synaptics Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" + register "generic.reset_delay_ms" = "45" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 20 on end + end + chip drivers/i2c/generic + register "hid" = ""RAYD0001"" + register "desc" = ""Raydium Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" + register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" + register "reset_delay_ms" = "1" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" + register "enable_delay_ms" = "50" + register "has_power_resource" = "1" + device i2c 39 on end + end + end # - I2C 7 + end +end diff --git a/src/mainboard/google/octopus/variants/lick/variant.c b/src/mainboard/google/octopus/variants/lick/variant.c new file mode 100644 index 0000000..aeefda5 --- /dev/null +++ b/src/mainboard/google/octopus/variants/lick/variant.c @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/variants.h> +#include <soc/pci_devs.h> +#include <ec/google/chromeec/ec.h> + +#define SKU_UNKNOWN 0xFFFFFFFF + +void variant_update_devtree(struct device *dev) +{ + uint32_t sku_id = SKU_UNKNOWN; + struct device *touchscreen_i2c_host; + + touchscreen_i2c_host = pcidev_path_on_root(PCH_DEVFN_I2C7); + + if (touchscreen_i2c_host == NULL) + return; + + /* SKU ID 1, 6 does not have a touchscreen device, hence disable it. */ + google_chromeec_cbi_get_sku_id(&sku_id); + if (no_touchscreen_sku(sku_id)) + touchscreen_i2c_host->enabled = 0; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/37268 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b1a79b022a0c698174dd08f3c11769a4fd6833c Gerrit-Change-Number: 37268 Gerrit-PatchSet: 1 Gerrit-Owner: Regan Chang <regan.chang(a)lcfc.corp-partner.google.com> Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: arch/x86: Move generic functions from postcar_loader.c to stage_loader.c
by Subrata Banik (Code Review) 07 Aug '23

07 Aug '23

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34751 ) Change subject: arch/x86: Move generic functions from postcar_loader.c to stage_loader.c ...................................................................... arch/x86: Move generic functions from postcar_loader.c to stage_loader.c This patch moves few generic functions (finalize_load and stack_push) from postcar_loader.c to stage_loader.c file so that other callers can also use these functions. Change-Id: I4d2200d95e68c0eb01681b8f9b71b3d30d122c43 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/arch/x86/Makefile.inc A src/arch/x86/include/arch/stage_loader.h M src/arch/x86/postcar_loader.c A src/arch/x86/stage_loader.c 4 files changed, 62 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/34751/1 diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 32e0173..2fad75e 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -239,6 +239,7 @@ romstage-y += memset.c romstage-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c romstage-y += postcar_loader.c +romstage-y += stage_loader.c romstage-$(CONFIG_COLLECT_TIMESTAMPS_TSC) += timestamp.c romstage-$(CONFIG_ARCH_ROMSTAGE_X86_32) += walkcbfs.S diff --git a/src/arch/x86/include/arch/stage_loader.h b/src/arch/x86/include/arch/stage_loader.h new file mode 100644 index 0000000..23ac6e9 --- /dev/null +++ b/src/arch/x86/include/arch/stage_loader.h @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef STAGE_LOADER_H +#define STAGE_LOADER_H + +#include <arch/cpu.h> + +static inline void stack_push(struct postcar_frame *pcf, uint32_t val) +{ + uint32_t *ptr; + + pcf->stack -= sizeof(val); + ptr = (void *)pcf->stack; + *ptr = val; +} + +void finalize_load(uintptr_t *stack_top_ptr, uintptr_t stack_top); + +#endif /* STAGE_LOADER_H */ diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c index 35e139f..3f42298 100644 --- a/src/arch/x86/postcar_loader.c +++ b/src/arch/x86/postcar_loader.c @@ -13,7 +13,7 @@ * GNU General Public License for more details. */ -#include <arch/cpu.h> +#include <arch/stage_loader.h> #include <cbmem.h> #include <console/console.h> #include <cpu/cpu.h> @@ -25,15 +25,6 @@ #include <stage_cache.h> #include <timestamp.h> -static inline void stack_push(struct postcar_frame *pcf, uint32_t val) -{ - uint32_t *ptr; - - pcf->stack -= sizeof(val); - ptr = (void *)pcf->stack; - *ptr = val; -} - static void postcar_frame_prepare(struct postcar_frame *pcf) { msr_t msr; @@ -131,17 +122,6 @@ return (void *) pcf->stack; } -static void finalize_load(uintptr_t *stack_top_ptr, uintptr_t stack_top) -{ - *stack_top_ptr = stack_top; - /* - * Signal to rest of system that another update was made to the - * postcar program prior to running it. - */ - prog_segment_loaded((uintptr_t)stack_top_ptr, sizeof(uintptr_t), - SEG_FINAL); -} - static void load_postcar_cbfs(struct prog *prog, struct postcar_frame *pcf) { struct rmod_stage_load rsl = { diff --git a/src/arch/x86/stage_loader.c b/src/arch/x86/stage_loader.c new file mode 100644 index 0000000..ca6a987 --- /dev/null +++ b/src/arch/x86/stage_loader.c @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/stage_loader.h> +#include <stage_cache.h> + +void finalize_load(uintptr_t *stack_top_ptr, uintptr_t stack_top) +{ + *stack_top_ptr = stack_top; + /* + * Signal to rest of system that another update was made to the + * postcar program prior to running it. + */ + prog_segment_loaded((uintptr_t)stack_top_ptr, sizeof(uintptr_t), + SEG_FINAL); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/34751 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d2200d95e68c0eb01681b8f9b71b3d30d122c43 Gerrit-Change-Number: 34751 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

3 21

Change in coreboot[4.8_branch]: cpu/allwinner: Prepend the BOOT0 header to the bootblock.bin
by Arthur Heymans (Code Review) 07 Aug '23

07 Aug '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35401 ) Change subject: cpu/allwinner: Prepend the BOOT0 header to the bootblock.bin ...................................................................... cpu/allwinner: Prepend the BOOT0 header to the bootblock.bin Instead of prepending the BOOT0 header to the full coreboot.rom to create a new file called BOOT0, prepend to the bootblock.bin that gets included in BOOTBLOCK FMAP region. Change-Id: I974a6aaa1a340c6b26f78b9d038be0f580331831 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/allwinner/a10/Makefile.inc 1 file changed, 3 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/35401/1 diff --git a/src/cpu/allwinner/a10/Makefile.inc b/src/cpu/allwinner/a10/Makefile.inc index a6cd4b4..9f5f6ac 100644 --- a/src/cpu/allwinner/a10/Makefile.inc +++ b/src/cpu/allwinner/a10/Makefile.inc @@ -25,8 +25,6 @@ romstage-y += uart.c uart_console.c ramstage-y += uart.c uart_console.c -real-target: $(obj)/BOOT0 - get_bootblock_size= \ $(eval bb_s=$(shell $(CBFSTOOL) $(1) print | grep bootblocksize | \ sed 's/[^0-9 ]//g')) \ @@ -46,11 +44,11 @@ # under util/arm_boot_tools/mksunxiboot. The boot ROM will load at most 24KiB of # data to SRAM. The BOOT0 header takes 32 bytes, so bootblock is limited to # 24KiB - 32 bytes. -# TODO: make mksunxiboot take the bootblock size as a parameter # TODO: print an error if bootblock is too large (maybe place ROMSTAGE at the # exact offset needed to collide with the bootblock) # FIXME: A10 loads 24KiB. According to Oliver other chips load a little more # -$(obj)/BOOT0: $(obj)/coreboot.rom $(MKSUNXIBOOT) - @printf " BOOT0 $(subst $(obj)/,,$(^))\n" + +$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin $(MKSUNXIBOOT) + @printf " Prepending BOOT0 header $(subst $(obj)/,,$(^))\n" $(MKSUNXIBOOT) $(word 1, $^) $@ -- To view, visit https://review.coreboot.org/c/coreboot/+/35401 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.8_branch Gerrit-Change-Id: I974a6aaa1a340c6b26f78b9d038be0f580331831 Gerrit-Change-Number: 35401 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: configs: Build config to run nvramcui with seabios on qemu
by Name of user not set (Code Review) 07 Aug '23

07 Aug '23

Name of user not set #1002476 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35850 ) Change subject: configs: Build config to run nvramcui with seabios on qemu ...................................................................... configs: Build config to run nvramcui with seabios on qemu Provide additional build config to run nvramcui as a secondary payload with seabios on qemu. It resolves `Could not find Coreboot Option Table`. Fixes: https://ticket.coreboot.org/issues/97 Change-Id: Ifae854bdc0092276c85ca198a33f0003cc3c1d0b Signed-off-by: Himanshu Sahdev <himanshusah(a)hcl.com> --- A configs/config.emulation_qemu_x86_i440fx_nvramcui 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/35850/1 diff --git a/configs/config.emulation_qemu_x86_i440fx_nvramcui b/configs/config.emulation_qemu_x86_i440fx_nvramcui new file mode 100644 index 0000000..bccef90 --- /dev/null +++ b/configs/config.emulation_qemu_x86_i440fx_nvramcui @@ -0,0 +1,2 @@ +CONFIG_USE_OPTION_TABLE=y +CONFIG_NVRAMCUI_SECONDARY_PAYLOAD=y -- To view, visit https://review.coreboot.org/c/coreboot/+/35850 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifae854bdc0092276c85ca198a33f0003cc3c1d0b Gerrit-Change-Number: 35850 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1002476 Gerrit-MessageType: newchange

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